Samsung S5PC110, Manual

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S5PC110_UM 1 DMA CONTROLLER
1-21
1.2.1.7 Configuration Register4 for DMA_PERI(0,1) (CR4, R)
• CR4 for DMA_PERI0, R, Address = 0xE090_0E10
• CR4 for DMA_PERI1, R, Address = 0xE0A0_0E10
CR4 Bit Description Initial State
PNS [31:0] Specifies the security state of peripheral request interfaces.
Bit [N] = 1: Assigns peripheral request interface N to non-
secure state.
32’hffff_ffff
0xFFFF_FFFF
1.2.1.8 Configuration Register DN for DMA_PERI(0,1) (CRdn, R)
• CRDn for DMA_PERI0, R, Address = 0xE090_0E14
• CRDn for DMA_PERI1, R, Address = 0xE0A0_0E14
CRDn Bit Description Initial State
data_buffer_dep [29:20] Specifies the number of lines that data buffer contains.
b000000111 = 8 lines
0x7
rd_q_dep [19:16] Specifies the depth of read queue.
b0111 = 8 lines
0x7
rd_cap [14:12] Specifies the read issuing capability that programs the number
of outstanding read transactions.
b011 = 4
0x3
wr_q_dep [11:8] Specifies the depth of write queue.
b0111 = 8 lines
0x7
wr_cap [6:4] Specifies the write issuing capability that programs the number
of outstanding write transactions.
b011 = 4
0x3
data_width [2:0] Specifies the data bus width of AXI interface.
b010 = 32-bit
0x2