S5PC110_UM
5 4BG3D
5-7
5.1.5.3 Pixel Data Master
The PDM initiates “rasterize processing” within the system. It consists of the ISP and Pixel Presenter (PP)
modules. Each pixel pipeline processes pixels for a different half of a given tile, which allows for optimum
efficiency within each pipe due to locality of data.
5.1.5.4 VDM Data Master
The VDM initiates “transform and lighting processing” within the system. The VDM module reads an input control
stream, which contains triangle index data and state data. The state data indicates the PDS program, size of the
vertices, and amount of USSE output buffer resource available to the VDM. The triangle data is parsed to
determine unique indices that must be processed by the USSE. These are grouped together according to the
configuration provided by the driver and presented to the DMS.
5.1.5.5 General Purpose Data Master
The GPDM responds to events within the system. Each event causes an interrupt to the host or synchronized
execution of a program on the PDS. The program may or may not cause a subsequent task to be executed on the
USSE.
5.1.5.6 PDS
The DMS and PDS controls whether vertices, pixels, or imaging data operations are processed by the USSE. It
controls the order, location, and size of these operations. It also controls two operations: fetching essential data
for the USSE and allocating resources.
5.1.5.7 USSE
USSE is a user programmable processing unit. Although general in nature, its instructions and features are
optimized for three types of tasks, namely, processing vertices (vertex shading), processing pixels (pixel shading),
and imaging processing.
5.1.5.8 Multi-Level Cache
The multi-level cache is a level cache consisting of two modules, namely, the Main Cache and the Mux, Arbiter,
Demux, De-Compression Unit (MADD).
MADD is a wrapper around the main cache module that manages and formats requests to and from the cache. It
also provides Level 0 caching for texture and USSE requests.
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...