Samsung S5PC110, Manual

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S5PC110_UM 10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
10-119
10.3.6.60 Rx Related Register (CEC_ RX_CTRL, R/W, Address = E1B0_00C0)
CEC_RX_CTRL_0 Bit Description Initial State
Reset [7] Specifies the CEC Rx reset bit.
0 = No effect
1 = Immediately resets CEC Rx related registers and
state machines to its reset value. It will be cleared after
one clock 0
Check_Sampling_Error [6] Specifies the CEC Rx sampling error check enable bit.
0 = Does not check sampling error
1 = Checks sampling error while receiving data bits
CEC Rx samples the CEC bus three times (at 1.00, 1.05,
and 1.10 ms) and checks whether the three samples are
identical.
0
Check_Low_Time_Error [5] Specifies the CEC Rx low-time error check enable bit.
0 = Does not check low-time error
1 = Checks low-time error while receiving data bits
In receiving each bit from the CEC bus, CEC Rx checks
the duration of logical 0 from the starting of one bit
transfer (falling edge on the CEC bus). Rx checks
whether the duration is longer than the maximum time the
CEC bus can be in logical 0 (max 1.7 ms). 0
Check_Start_Bit_Error [4] Specifies the CEC Rx start bit error check enable bit
0 = Does not check start bit error.
1 = Checks start bit error while receiving a start bit.
After receiving a start bit from the CEC bus, CEC Rx
checks the duration of logical 0 and 1 of start bit (as
specified in CEC specification on page CEC-8). Rx
checks whether the duration meets the specification.
0
- [3:2] Reserved 2b00
Rx_Host_Busy [1] Specifies the CEC Rx host busy bit.
0 = Rx receives incoming message and sends
acknowledgement.
1 = A host processor is unavailable to receive and
process CEC messages. Rx sends “not acknowledged”
signal to a message initiator to indicate that a host
processor is unavailable and to receive and process CEC
messages. 0
Rx_Enable [0] Specifies the CEC Rx start bit.
0 = Disables Rx
1 = Enables CEC Rx module to receive a message
This bit is cleared after receiving a message. 0