S5PC110_UM
2 IIS MULTI AUDIO INTERFACE
2-21
2.9.1.1 IIS Interface Control Register (IISCON, R/W, Address = 0xEEE3_0000)
IISCON
Bit
Description
R/W
Initial State
SW_RST
[31]
IIS s/w reset control. This should be set to 1 after IIS clock
is stable.
0 = Reset IIS module (default)
1 = Un-reset IIS module
Before reading SFR of IIS, user must set this bit.
R/W 0
Reserved [30:27] -
R
0x0
FRXOFSTATUS
[26]
RX FIFO Over Flow Interrupt Status. And this is used by
interrupt clear bit. When this is high, you can do interrupt
clear by writing '1'.
0 = Interrupt does not occur.
1 = Interrupt occurs
R/W 0
FRXOFINTEN
[25]
Enables RX FIFO Overflow Interrupt
0 = Disables RXFIFO Overflow INT
1 = Enables RXFIFO Overflow INT
R/W 0
FTXSUR
STATUS
[24]
Secondary TX FIFO_S under-run interrupt status. This is
used by interrupt clear bit. When this is high, you can clear
interrupt clear by writing '1'.
0 = Interrupt does not occur.
1 = Interrupt occurs.
R/W 0
FTXSURINTEN [23]
Secondary
TX
FIFO_S Under-run Interrupt Enable
0 = TXFIFO_S Under-run INT disable
1 = TXFIFO_S Under-run INT enable
R/W 0
FTXSEMPT
[22]
Secondary TX FIFO_S empty Status Indication
0 = TX FIFO_S is not empty(Ready to transmit Data)
1 = TX FIFO_S is empty (Not Ready to transmit Data)
R 0
FTXSFULL
[21]
Secondary TX FIFO_S full Status Indication
0 = TX FIFO_S is not full
1 = TX FIFO_S is full
R 0
TXSDMAPAUSE
[20]
Tx External DMA operation for secondary TX FIFIO_S
pause command. Note that when this bit is activated, the
External DMA request will be halted after current on-going
External DMA transfer is completed.
0 = No pause External DMA operation for TX FIFO_S
1 = Pause External DMA operation for TX FIFO_S
Note: IISDMAEN SFR performs Internal DMA stop control.
R/W 0
Reserved [19]
Reserved.
This value must be 0.
R/W
0
TXSDMACTIVE
[18]
Tx External DMA active for secondary TX FIFO_S (start
External DMA request). Note that when this bit is set from
high to low, the External DMA operation will be forced to
stop immediately.
0 = Inactive
1 = Active
R/W 0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...