Samsung S5PC110, Manual

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S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT
5-16
Critical path delay of ARM Core in S5PC110X is about 1.70ns in the worst condition. Delay of NOR2X1 cell is
about 0.04609ns. One delay tap has four NOR2X1 cells and each delay tap gives 0.184ns delay. Delay tap
structure is as shown in
Figure 5-6
.
Figure 5-6 HPM Delay Tap structure in S5PC110
HPM has a predelay module that includes 32 delay tap-like delay elements and a delayline module that includes
32 delay taps. To correlate with ARM core, 14-th tap should be selected with setting predelay_sel[2:0] of HPM
3’b000 when HPM clock ratio is equal to 1.