Samsung S5PC110, Manual

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S5PC110_UM 5 4BG3D
5-10
5.1.6 BLOCK DIAGRAM OF INTEGRATION INFORMATION
G3D
MEM_BUS
SYS_BUS Interconnect
bus
CMU
Interrupt controller
IRQ
BUS_CLK
CORE_CLK
RESETN
S5PC110
G3D
MEM_BUS
SYS_BUS Interconnect
bus
CMU
Interrupt controller
IRQ
BUS_CLK
CORE_CLK
RESETN
S5PC110
Figure 5-2 Block Diagram of Integration Information with Related Block
The Clock Management Unit (CMU) comprises of two blocks: BUS_CLK (for bus interface part) and CORE_CLK
(for G3D internal function part). Both clocks are supported in 200Mhz clock domain, but you can set the two clocks
with different clocks. BUS_CLK and CORE_CLK can be fully asynchronous.
G3D block has six controllable clock domains partitioned internally to functional areas of the design. It
automatically controls clock gating if some blocks are not used at that time.
G3D block has its own power domain. If you do not use G3D block, then you can turn off the G3D block
thoroughly by setting PMU. The detail power states are summarized in
Table 5-2
. You can see the detailed
explanation of power mode in Chapter, “PMU”.
Table 5-2 Power Mode Summary About G3D
Power
Mode
NORMAL IDLE DEEP-IDLE STOP
DEEP-
STOP
SLEEP
G3D
Power on/ Clock
gating/ Power
gating
KEEP power
state in
NORMAL
mode
(NOTE)
KEEP power
state in
NORMAL mode/
Power gating
Clock
gating/
Power
gating
Power
gating
Power off
NOTE:
KEEP power state in NORMAL mode means power-on G3D in NORMAL mode is still power-on, clock-gated G3D in
NORMAL mode is still clock-gated, and power-gated G3D in NORMAL mode is still power-gated.