Samsung S5PC110, Manual

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S5PC110_UM 1 DRAM CONTROLLER
1-36
Use DQS cleaning to remove high-Z state of DQS.
P H Y
C o n tr o l le r
FF
D Q
C K
d e la y
lin e
t o e a ch
da t a sli ce
G A T E O
G A T E I
ct r l_ g at e
D Q S
d a t a _ sl ic e
IO
IO
IO
io _g a t e _ ou t
i o _g a t e _i n
io _ d q s_ i n
I /O
IO
IO
M e m o r y
IO
A D C T /
C M D
IO
C K / C K
B
IO
IO
IO
D Q S
C le a n
de l ay
li n e
F F
D Q
C K
D Q
I/
O
PKG
Board
B
onding
Co
re
tA t B tC t D
tE t B tC t D
tA t D L
tE
C K
io _ ck _o u t
A B C D
F e e d - b a c k
t A C
NOTE:
DQS Cleaning Scheme
Figure 1-12 Board Level Connection Diagram for DQS Cleaning
•
tA
: I/O output delay
•
tB
: Package bonding wire delay
•
tC
: Package board delay
•
tD
: Board trace delay
•
tE
: I/O input delay
•
tDL
: delay line delay
•
tAC
: minimum CK-to-DQS timing of LPDDR/DDR2 memory spec. (LPDDR
≈
1ns, DDR2
≈
0.5tCK)
•
tFS
: Fine step delay in DLL, From
PhyStatus0
.ctrl_lock_value[9:0], tFS is calculated.
−
If ctrl_half = 0, tFS = tCK / ctrl_lock_value[9:0].
−
If ctrl_half = 1, tFS = tCK*0.5 / ctrl_lock_value[9:0] ctrl_shiftc
controls PVT-independent delay
amount(tF) and
ctrl_offsetc
controls PVT-dependent delay amount(tV).