Samsung S5PC110, Manual

Page: 1590 / 2426

S5PC110_UM 9 8BMIXER
9-10
Wide Narrow
CSCY2R
(601)
R = Y + 1.371(Cr-128)
G = Y – 0.698(Cr-128) – 0.336(Cb-128)
B = Y + 1.732(Cb-128) R = 1.164(Y-16) + 1.596(Cr-128)
G = 1.164(Y-16) – 0.813(Cr-128) – 0.391(Cb-128)
B = 1.164(Y-16) + 2.018(Cb-128)
CSCY2R
(709)
R = Y + 1.540(Cr-128)
G = Y – 0.459(Cr-128) – 0.183(Cb-128)
B = Y + 1.816(Cb-128) R = 1.164(Y-16) + 1.793(Cr-128)
G = 1.164(Y-16) – 0.534(Cr-128) – 0.213(Cb-128)
B = 1.164(Y-16) + 2.115(Cb-128)
NOTE:
This table refers to Video Demystified( Keith Jack ).
9.2.2.3 MIXER_INT_EN Register (MIXER_INT_EN, R/W, Address = 0xF920_0008)
MIXER_INTR Bit Description Initial State
Reserved [31:12] Reserved, read as zero, do not modify 0
INT_EN_VSYNC [11] The vertical sync. interrupt enable. ( Write only )
0 = Disable interrupt
1 = Enable interrupt 0
INT_EN_VP [10] The VP underflow interrupt enable.
0 = Disables interrupt
1 = Enables interrupt
Setting this bit to ‘0’ disables only the interrupt request to
host controller. It does not mask the change of the
MIXER_INT_STATUS[10] bit status 0
INT_EN_GRP1 [9] The graphic layer1 line buffer underflow interrupt enable.
0 = Disables interrupt
1 = Enables interrupt
Setting this bit to ‘0’ disables only the interrupt request to
host controller. It does not mask the change of the
MIXER_INT_STATUS[9] bit status 0
INT_EN_GRP0 [8] The graphic layer0 line buffer underflow interrupt enable.
0 = Disables interrupt
1 = Enables interrupt
Setting this bit to ‘0’ disables only the interrupt request to
host controller. It does not mask the change of the
MIXER_INT_STATUS[8] bit status 0
Reserved [7:0] Reserved. 0