Samsung S5PC110, Manual

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S5PC110_UM 5 USB2.0 HS OTG
5-54
5.8.4.2 Host Frame Interval Register (HFIR, R/W, Address = 0xEC00_0404)
This register stores the frame interval information for the current speed to which the core has enumerated
HFNUM Bit Description R/W Initial State
Reserved [31:16] - - 16’h0
FrInt [15:0] Frame Interval
The value that the application programs to this field specifies the
interval between two consecutive SOFs (FS) or micro- SOFs
(HS) or Keep-Alive tokens (HS). This field contains the number
of PHY clocks that constitute the required frame interval. The
default value set in this field for a FS operation if the PHY clock
frequency is 60 MHz. The application can write a value to this
register only after the Port Enable bit of the Host Port Control
and Status register (HPRT.PrtEnaPort) has been set. If no value
is programmed, the core calculates the value based on the PHY
clock specified in the FS/ LS PHY Clock Select field of the Host
Configuration register (HCFG.FSLSPclkSel). Do not change the
value of this field after the initial configuration.
•
125 μ s * (PHY clock frequency for HS)
•
1 ms * (PHY clock frequency for FS/LS)
R/W 16'h0B8F
5.8.4.3 Host Frame Number/Frame Time Remaining Register (HFNUM, R, Address = 0xEC00_0408)
This register indicates the current frame number. It also indicates the time remaining in the current frame.
HFNUM Bit Description R/W Initial State
FrRem [31:16] Frame Time Remaining
Indicates the amount of time remaining in the current
microframe (HS) or frame (FS/ LS), in terms of PHY clocks. This
field decrements on each PHY clock. If it reaches zero, this field
is reloaded with the value in the Frame Interval register and a
new SOF is transmitted on the USB.
R 16'h0
FrNum [15:0] Frame Number
This field increment if a new SOF is transmitted on the USB, and
is reset to 0 if it reaches 16'h3FFF.
R 16'h0