S5PC110_UM
5 COMPACT FLASH CONTROLLER
5-23
5.11.2.8 ATA Transfer Count Number (ATA_XFR_NUM, R/W, Address = 0xE820_0034)
ATA_XFR_NUM
Bit
Description
R/W
Initial State
xfr_num
[31:1] Data transfer number.
To transfer 1-sector (512-byte), you should set 32’h1ff.
R/W 0x00000000
Reserved [0]
Reserved
R
0x0
5.11.2.9 ATA Current Transfer Count (ATA_XFR_CNT, R, Address = 0xE820_0038)
ATA_XFR_CNT
Bit
Description
R/W
Initial State
xfr_cnt
[31:1] Current remaining transfer counter. This value counts
down from ATA_XFR_NUM. It goes to zero if all pre-
defined data are transferred.
In case of read transfer, ATA_XFR_NUM decreases by
1(2-byte).
In case of write transfer, ATA_XFR_NUM decreases by
16(32-byte), because the AHB burst size is 8.
R 0x00000000
Reserved [0]
Reserved
R
0x0
5.11.2.10 Start Address of the Track Buffer (ATA_TBUF_BASE, R/W, Address = 0xE820_003C)
ATA_TBUF_BASE
Bit
Description
R/W
Initial State
track_buffer_base
[31:2] Start address of track buffer (4 byte unit)
R/W
0x00000000
Reserved [1:0]
Reserved
R
0x0
5.11.2.11 Size of the Track Buffer (ATA_TBUF_SIZE, R/W, Address = 0xE820_0040)
ATA_TBUF_SIZE
Bit
Description
R/W
Initial State
track_buffer_size
[31:5] Size of track buffer (32 byte unit)
This should be set to “size_of_data_in_bytes – 1”. For
example, to transfer 1-sector (512-byte, 32’h200), you
should set 32’h1FF ( = 32’h200 – 1).
R/W 0x0000000
Reserved [4:0]
Reserved
R
0x00
5.11.2.12 Start Address of the Source Buffer (ATA_SBUF_BASE, R/W, Address = 0xE820_0044)
ATA_SBUF_BASE
Bit
Description
R/W
Initial State
src_buffer_base
[31:2] Start address of source buffer (4byte unit)
R/W
0x00000000
Reserved [1:0]
Reserved
R
0x0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...