Samsung S5PC110, Manual

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S5PC110_UM 5 USB2.0 HS OTG
5-77
5.8.7.13 Device Control IN Endpoint 0 Control Register (DIEPCTL0, R/W, Address = 0xEC00_0900)
This section describes the Control IN Endpoint 0 Control register. Nonzero control endpoints use registers for
endpoints 1-15.
DIEPCTL0 Bit Description R/W Initial State
EPEna [31] Endpoint Enable
Indicates that data is ready to be transmitted on the endpoint.
The core clears this bit before setting any of the following
interrupts on this endpoint.
•
Endpoint Disabled
•
Transfer Completed
R_WS_
SC
1'b0
EPDis [30] Endpoint Disable
The application sets this bit to stop transmitting data on an
endpoint, even before the transfer for that endpoint is complete.
The application must wait for the Endpoint Disabled interrupt
before treating the endpoint as disabled. The core clears this bit
before setting the Endpoint Disabled Interrupt. The application
must set this bit only if Endpoint Enable is already set for this
endpoint.
R_WS_
SC
1'b0
Reserved [29:28] - - 2'b0
SetNAK [27] Set NAK
A write to this bit sets the NAK bit for the endpoint.
Using this bit, the application controls the transmission of NAK
handshakes on an endpoint. The core also sets this bit for an
endpoint after a SETUP packet is received on that endpoint.
W 1'b0
CNAK [26] Clear NAK
A write to this bit clears the NAK bit for the endpoint.
W 1'b0
TxFNum [25:22] TxFIFO Number
This value is set to the FIFO number that is assigned to IN
Endpoint 0.
R 4'h0
Stall [21] STALL Handshake
The application sets this bit, and the core clears it, if a SETUP
token is received for this endpoint. If a NAK bit, Global Non-
Periodic IN NAK, or Global OUT NAK is set along with this bit,
the STALL bit takes priority.
R_WS_
SC
1'b0
Reserved [20] - - 1'b0
EPType [19:18] Endpoint Type
Hardcoded to 00 for control
R 2'h0