Samsung S5PC110, Manual

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S5PC110_UM 1 DRAM CONTROLLER
1-25
1.4.1.1 Controller Control Register (ConControl, R/W, Address = 0xF000_0000, 0xF140_0000)
CONCONTROL Bit Description R/W
Initial
State
Reserved [31:28] Should be zero 0x0
timeout_cnt [27:16] Default Timeout Cycles
0xn = n aclk cycles (aclk: AXI clock)
This counter prevents transactions in command queue from
starvation. This counter starts if a new AXI transaction comes
into a queue. If the counter becomes zero, the corresponding
transaction becomes the highest priority command of all the
transactions in the command queue. This is a default timeout
counter and overridden by the QoS counter if the ARID/AWID
matched with the QoS ID comes into the command queue.
Refer to
“1.2.5 Quality of Service”
.
R/W 0xFFF
rd_fetch [15:12] Read Data Fetch Cycles
0xn = n mclk cycles (mclk: Memory clock)
This register is for the unpredictable latency of read data
coming from memory devices by tDQSCK variation or the
board flying time. The read fetch delay of PHY read FIFO
must be controlled by this parameter. The controller will fetch
read data from PHY after (read_l n) mclk cycles.
Refer to
“1.2.6 Read Data Capture”
.
R/W 0x1
qos_fast_en [11] Enables adaptive QoS
0x0 = Disables
0x1 = Enables
If enabled, the controller loads QoS counter value from
QoSControl.qos_cnt_f instead of QoSControl.qos_cnt if the
corresponding input pin qos_fast is turned on. Refer to
“1.2.5
Quality of Service”
.
R/W 0x0
dq_swap [10] DQ Swap
0x0 = Disables
0x1 = Enables
If enabled, the controller reverses the bit order of memory data
pins. (For example, DQ[31] <-> DQ[0], DQ[30] <-> DQ[1])
R/W 0x0
chip1_empty [9] Command Queue Status of Chip1
0x0 = Not Empty
0x1 = Empty
There is no AXI transaction corresponding to chip1 memory in
the command queue entries R 0x1
chip0_empty [8] Command Queue Status of Chip0
0x0 = Not Empty
0x1 = Empty
There is no AXI transaction corresponding to chip0 memory in
the command queue entries R 0x1