S5PC110_UM
4 POWER MANAGEMENT
4-33
4.9 RESET CONTROL
4.9.1 RESET TYPES
S5PC110 has four types of resets and reset generator can place the system into one of five reset states.
There are five reset states, namely:
•
Hardware Reset - The hardware reset is generated when XnRESET is driven to low. It is an uncompromised,
ungated, and total reset that is used to drive S5PC110 to a known initial state.
•
Watchdog Reset - Reset signal by watchdog timer
•
Software Reset - Reset signal by setting special control register
•
Warm reset - Reset signal by XnWRESET pin.
•
Wakeup Reset - Reset signal generated when a module that has normal F/Fs is powered down, and the
module is powered up again by wakeup events; but in sleep mode, wakeup reset is generated to all modules
that were powered off regardless of normal F/F or retention F/F.
Five resets have the following priorities:
Hardware Reset > Watchdog Reset > Warm Reset > Software Reset > Wakeup Reset
4.9.2 HARDWARE RESET
Hardware reset is asserted when the XnRESET pin is driven to low, and all units in the system (except RTC
function module) are reset to known states.
During the hardware reset, the following actions take place:
•
All internal registers and Cortex-A8 go into their pre-defined reset state.
•
All pins get their reset state.
•
The XnRSTOUT pin is asserted when XnRESET is driven.
Hardware reset is asserted when an external source drives the XnRESET input pin low. XnRESET is non-
maskable, and therefore is always applicable. Upon assertion of XnRESET, S5PC110 enters into reset state
regardless of the previous state. For hardware reset to be asserted actually, XnRESET must be held long enough
to allow internal stabilization and propagation of the reset state.
Caution:
Power regulator for system must be stable prior to the deassertion of XnRESET. If power regulator for
system is not stable, it damages to S5PC110 and its operation is not guaranteed.
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...