Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor lxxxvii
— Chapter 37, “Buffer Descriptors and Connection Tables,” describes the structure and
configuration of the buffer descriptors (BDs) and the transmit and receive connection tables
(TCTs and RCTs) used with ATM.
— Chapter 38, “ATM Parameter RAM,” describes how the parameter RAM is used to configure
the four SCCs for serial ATM and the UTOPIA interface. The CP also uses parameter RAM to
store operational and temporary values used during SAR activities.
— Chapter 39, “ATM Controller,” describes the address mapping mechanisms of the ATM
controller to support connection tables for both single- and multi-PHY interfaces, and the
commands provided to control ATM transmit and receive operations on a channel-by-channel
basis.
— Chapter 40, “ATM Pace Control,” describes how the ATM pace control unit (APC) processes
traffic parameters of each channel and defines the multiplex timing for all the channels.
— Chapter 41, “ATM Exceptions,” describes how the circular ATM interrupt queue operates with
an event register (SCCE or IDSR1) to provide an interrupt model for ATM operations.
— Chapter 42, “Interface Configuration,” describes the programming of registers and parameters
for ATM operations through both the UTOPIA and serial interfaces.
— Chapter 43, “UTOPIA Interface,” describes the single- and multi-classic SAR MPHY ATM
operation, including the UTOPIA modes and the signals provided for UTOPIA support.
— Chapter 44, “AAL2 Implementation,” describes the implementation of AAL2.
• Part VII, “Fast Ethernet Controller (FEC),” describes the MPC885 support for 10/100 base-T
Ethernet. It consists of the following chapter:
— Chapter 45, “Fast Ethernet Controller (FEC),” describes the Fast Ethernet Controller, which is
implemented on all MPC885 parts. It provides general descriptions of supported operations,
full descriptions of the supporting registers, and initialization information.
• Part VIII, “Integrated Security Engine (SEC Lite),” describes the MPC885 implementation of the
security engine. It contains the following chapters:
— Chapter 46, “SEC Lite Overview,” gives a high-level description of the MPC885 SEC Lite and
the features.
— Chapter 47, “SEC Lite Address Map,” describes the memory used by the SEC Lite.
— Chapter 48, “SEC Lite Execution Units,” describes the Data Encryption Standard execution
unit (DEU), the Advanced Encryption Standard execution unit (AESU), and the message digest
execution unit (MDEU).
— Chapter 49, “SEC Lite Descriptors,” describes the descriptors used to take SEC Lite through
the security operations.
— Chapter 50, “SEC Lite Crypto-Channel,” describes how the crypto-channel manages data
associated with one of more execution units.
— Chapter 51, “SEC Lite Controller,” describes the responsibility of the controller within the
SEC Lite to oversee the operations of the execution units (EUs), the interface to the host
processor, and the management of the crypto-channel.