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System Development and Debugging

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor

53-25

53.3.2.1.4

Freeze

The freeze indication means that the processor is in debug mode (normal processor execution of user code
is frozen). Freeze state is indicated on FRZ and is generated synchronously to the system clock. This
indication can be used to halt any off-chip device while in debug mode and is a handshake between the
debug tool and port. In addition to FRZ, the freeze state is indicated by the value 0b11 on VFLS[0–1],
shown in

Figure 53-8

.

Internal freeze status can also be monitored through status in the data shifted out of the debug port.

53.3.2.2

Development Port Registers

The development port consists logically of three registers:

•

The trap enable control register (TECR)

•

The development port instruction register (DPIR)

•

Development port data register (DPDR)

DPIR and DPDR are both implemented as the development port shift register, which also acts as a
temporary holding register for data to be stored in the TECR.

53.3.2.2.1

Development Port Shift Register

Instructions and data are serially shifted into the 35-bit development port shift register from the DSDI.
DSCK or CLKOUT is the shift clock, depending on the debug port clock mode. See

Section 53.3.2.3,

“Development Port Serial Communications–Clock Mode.”

The instructions or data are then transferred in parallel to the core and TECR. When the processor enters
debug mode it fetches instructions from DPIR that cause an access to the development port shift register.
These instructions are serially loaded into the shift register from DSDI using DSCK or CLKOUT as the
shift clock. Similarly, data is transferred to the core. Data is shifted into the shift register and read by the
processor by executing mfspr[DPDR]. Data is also parallel loaded into the development port shift register
from the core by executing mtspr[DPDR]. It is then serially shifted out to DSDO using DSCK or
CLKOUT as the shift clock.

53.3.2.2.2

Trap Enable Control Register (TECR)

The TECR is a 9-bit register that is loaded from the development port shift register. The contents of TECR
drives the six trap enable signals, two breakpoint signals, and VSYNC signal to the core. The transfer data
to TECR commands send the appropriate bits to the TECR. The TECR is not accessed by the core, but

VFLS0 • 1

2 • SRESET

FRZ • 1

2 • SRESET

GND • 3

4 • DSCK

GND • 3

4 • DSCK

GND • 5

6 • VFLS1

GND • 5

6 • FRZ

HRESET • 7

8 • DSDI

HRESET • 7

8 • DSDI

V

DD

• 9

10 • DSDO

V

DD

• 9

10 • DSDO

Figure 53-8. Development Port/BDM Connector Pinout Options

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Summary of Contents for PowerQUICC MPC870

Page 1: ...MPC885 PowerQUICC Family Reference Manual Supports MPC885 MPC880 MPC875 MPC870 MPC885RM Rev 2 04 2006 ...

Page 2: ...or surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescal...

Page 3: ... Control 14 Memory Controller 15 PCMCIA Interface 16 Part V Communications Processor Module V Communications Processor Module and CPM Timers 17 Communications Processor 18 SDMA Channels and IDMA Emulation 19 Serial Interface 20 Serial Communications Controllers 21 SCC UART Mode 22 SCC HDLC Mode 23 SCC AppleTalk Mode 24 SCC Asynchronous HDLC Mode and IrDA 25 SCC BISYNC Mode 26 SCC Ethernet Mode 27 ...

Page 4: ...wer Control 15 Memory Controller 16 PCMCIA Interface V Part V Communications Processor Module 17 Communications Processor Module and CPM Timers 18 Communications Processor 19 SDMA Channels and IDMA Emulation 20 Serial Interface 21 Serial Communications Controllers 22 SCC UART Mode 23 SCC HDLC Mode 24 SCC AppleTalk Mode 25 SCC Asynchronous HDLC Mode and IrDA 26 SCC BISYNC Mode 27 SCC Ethernet Mode ...

Page 5: ...III SEC Lite Overview 46 SEC Lite Address Map 47 SEC Lite Execution Units 48 SEC Lite Descriptors 49 SEC Lite Crypto Channel 50 SEC Lite Controller 51 Fast Ethernet Controller FEC 52 Part IX System Debugging and Testing Support IX System Development and Debugging 53 IEEE 1149 1 Test Access Port 54 Byte Ordering A Serial Communications Performance B Register Quick Reference Guide C Instruction Set ...

Page 6: ...ite 46 SEC Lite Overview 47 SEC Lite Address Map 48 SEC Lite Execution Units 49 SEC Lite Descriptors 50 SEC Lite Crypto Channel 51 SEC Lite Controller 52 Fast Ethernet Controller FEC IX Part IX System Debugging and Testing Support 53 System Development and Debugging 54 IEEE 1149 1 Test Access Port A Byte Ordering B Serial Communications Performance C Register Quick Reference Guide D Instruction Se...

Page 7: ...y Conventions xciii Part I Overview Chapter 1 MPC885 Overview 1 1 Features 1 2 1 2 Embedded MPC8xx Core 1 15 1 3 System Interface Unit SIU 1 16 1 4 PCMCIA Controller 1 17 1 5 Power Management 1 17 1 6 Security Engine 1 17 1 7 Fast Ethernet Controller FEC 1 18 1 8 Universal Serial Bus USB 1 18 1 9 Communications Processor Module CPM 1 18 1 10 ATM Capabilities 1 19 Chapter 2 Memory Map Part II MPC8x...

Page 8: ... 3 12 3 6 3 5 Unaligned Accesses 3 12 3 6 3 6 Atomic Update Primitives 3 13 3 7 The MPC885 and Implementation of the PowerPC Architecture 3 14 Chapter 4 MPC8xx Core Register Set 4 1 MPC885 Register Implementation 4 1 4 1 1 PowerPC Registers User Registers 4 1 4 1 1 1 PowerPC User Level Register Bit Assignments 4 2 4 1 1 1 1 Condition Register CR 4 2 4 1 1 1 2 Condition Register CR0 Field Definitio...

Page 9: ...ISA Instructions 5 7 5 2 4 1 Integer Instructions 5 7 5 2 4 1 1 Integer Arithmetic Instructions 5 7 5 2 4 1 2 Integer Compare Instructions 5 8 5 2 4 1 3 Integer Logical Instructions 5 9 5 2 4 1 4 Integer Rotate and Shift Instructions 5 10 5 2 4 2 Load and Store Instructions 5 11 5 2 4 2 1 Integer Load and Store Address Generation 5 11 5 2 4 2 2 Register Indirect Integer Load Instructions 5 11 5 2 ...

Page 10: ...d Exceptions 6 4 6 1 2 1 System Reset Interrupt 0x00100 6 4 6 1 2 2 Machine Check Interrupt 0x00200 6 5 6 1 2 3 DSI Exception 0x00300 6 6 6 1 2 4 ISI Exception 0x00400 6 6 6 1 2 5 External Interrupt Exception 0x00500 6 6 6 1 2 6 Alignment Exception 0x00600 6 7 6 1 2 6 1 Integer Alignment Exceptions 6 8 6 1 2 7 Program Exception 0x00700 6 8 6 1 2 8 Decrementer Exception 0x00900 6 9 6 1 2 9 System C...

Page 11: ...Data Cache Tags and Copyback Buffer 7 14 7 3 2 2 DC_CST Commands 7 15 7 3 2 2 1 Data Cache Enable Disable Commands 7 15 7 3 2 2 2 Data Cache Load and Lock Cache Block Command 7 15 7 3 2 2 3 Data Cache Unlock Cache Block Command 7 16 7 3 2 2 4 Data Cache Unlock All Command 7 16 7 3 2 2 5 Data Cache Invalidate All Command 7 16 7 3 2 2 6 Data Cache Flush Cache Block Command 7 17 7 4 Cache Control Ins...

Page 12: ...with a Software Monitor Debugger 7 28 Chapter 8 Memory Management Unit 8 1 Features 8 1 8 2 PowerPC Architecture Compliance 8 2 8 3 Address Translation 8 2 8 3 1 Translation Disabled 8 2 8 3 2 Translation Enabled 8 3 8 3 3 TLB Operation 8 5 8 4 Using Access Protection Groups 8 6 8 5 Protection Resolution Modes 8 7 8 6 Memory Attributes 8 8 8 7 Translation Table Structure 8 8 8 7 1 Level One Descri...

Page 13: ...10 TLB Manipulation 8 31 8 10 1 TLB Reload 8 31 8 10 1 1 Translation Reload Examples 8 32 8 10 2 Locking TLB Entries 8 33 8 10 3 Loading Locked TLB Entries 8 33 8 10 4 TLB Invalidation 8 33 Chapter 9 Instruction Execution Timing 9 1 Instruction Execution Timing Examples 9 1 9 1 1 Data Cache Load with a Data Dependency 9 1 9 1 2 Writeback Arbitration 9 2 9 1 3 Private Writeback Bus Load 9 2 9 1 4 F...

Page 14: ...0 5 4 2 SIU Interrupt Mask Register SIMASK 10 16 10 5 4 3 SIU Interrupt Edge Level Register SIEL 10 17 10 5 4 4 SIU Interrupt Vector Register SIVEC 10 17 10 6 The Bus Monitor 10 19 10 7 Software Watchdog Timer 10 20 10 7 1 Software Service Register SWSR 10 21 10 8 The Decrementer 10 22 10 8 1 Decrementer Register DEC 10 22 10 9 Timebase 10 23 10 9 1 Timebase Register TBU and TBL 10 23 10 9 2 Timeb...

Page 15: ...11 10 11 4 TRST Considerations 11 10 Part IV Hardware Interface Chapter 12 External Signals 12 1 MPC885 MPC880 Signals 12 1 12 1 1 MPC885 MPC880 Signals and Pin Numbers 12 1 12 1 2 MPC885 MPC880 System Bus Signals 12 4 12 2 MPC875 MPC870 Signals 12 23 12 2 1 MPC875 MPC870 Signals and Pin Numbers 12 23 12 2 2 MPC875 MPC870 System Bus Signals 12 26 12 3 Reset Behavior 12 39 12 4 Active Pull Up Buffe...

Page 16: ...6 13 4 6 2 Bus Grant BG 13 26 13 4 6 3 Bus Busy BB 13 27 13 4 6 4 External Bus Parking 13 29 13 4 7 Address Transfer Phase Related Signals 13 29 13 4 7 1 Transfer Start TS 13 29 13 4 7 2 Address Bus 13 30 13 4 7 3 Transfer Attributes 13 30 13 4 7 3 1 Read Write RD WR 13 30 13 4 7 3 2 Burst Indicator BURST 13 30 13 4 7 3 3 Transfer Size TSIZ 13 30 13 4 7 3 4 Address Types AT 13 30 13 4 7 3 5 Burst ...

Page 17: ...k BRGCLK 14 13 14 3 1 5 Synchronization Clock SYNCCLK SYNCCLKS 14 13 14 3 2 PIT Clock PITCLK 14 14 14 3 3 Time Base and Decrementer Clock TMBCLK 14 15 14 4 Power Distribution 14 15 14 4 1 I O Buffer Power VDDH 14 16 14 4 2 Internal Logic Power VDDL 14 16 14 4 3 Clock Synthesizer Power VDDSYN VSSSYN VSSSYN1 14 16 14 5 Power Control 14 17 14 5 1 Normal High Mode 14 17 14 5 2 Normal Low Mode 14 17 14...

Page 18: ... 23 15 5 1 4 Output Enable OE Timing 15 26 15 5 1 5 Programmable Wait State Configuration 15 26 15 5 1 6 Extended Hold Time on Read Accesses 15 26 15 5 2 Boot Chip Select Operation 15 29 15 5 3 External Asynchronous Master Support 15 30 15 5 4 Special Case Bursting with External Transfer Acknowledge 15 31 15 6 User Programmable Machines UPMs 15 32 15 6 1 Requests 15 33 15 6 1 1 Internal External M...

Page 19: ...Mechanism for Asynchronous External Masters 15 56 15 8 4 3 Special Signal for External Address Multiplexer Control 15 56 15 8 5 External Master Examples 15 57 15 8 5 1 External Masters and the GPCM 15 57 15 8 5 2 External Masters and the UPM 15 58 15 9 Memory System Interface Examples 15 63 15 9 1 Page Mode DRAM Interface Example 15 63 15 9 2 Page Mode Extended Data Out Interface Example 15 74 Cha...

Page 20: ... Reference Count 17 6 17 2 2 3 Timer Capture 17 6 17 2 2 4 Timer Gating 17 6 17 2 2 5 Cascaded Mode 17 7 17 2 2 6 Timer 1 and SPKROUT 17 7 17 2 3 CPM Timer Register Set 17 7 17 2 3 1 Timer Global Configuration Register TGCR 17 8 17 2 4 Timer Mode Registers TMR1 TMR4 17 9 17 2 4 1 Timer Reference Registers TRR1 TRR4 17 10 17 2 4 2 Timer Capture Registers TCR1 TCR4 17 10 17 2 4 3 Timer Counter Regis...

Page 21: ...able Entries 18 17 18 8 4 RISC Timer Event Register RTER Mask Register RTMR 18 17 18 8 5 PWM Mode 18 18 18 8 6 RISC Timer Initialization 18 18 18 8 7 RISC Timer Interrupt Handling 18 19 18 8 8 Using the RISC Timers to Track CP Loading 18 19 Chapter 19 SDMA Channels and IDMA Emulation 19 1 SDMA Channels 19 1 19 1 1 SDMA Transfers 19 2 19 1 2 U Bus Arbitration and the SDMA Channels 19 3 19 2 SDMA Re...

Page 22: ... IDMA Transfer 19 18 19 3 10 Interrupts During an IDMA Bus Transfer 19 18 Chapter 20 Serial Interface 20 1 SI Features 20 2 20 2 TSA Implementation 20 4 20 2 1 TSA Signals 20 7 20 2 2 Enabling Connections to the TSA 20 8 20 2 3 SI RAM 20 8 20 2 3 1 Disabling and Reenabling the TSA 20 9 20 2 3 2 One TDM Channel with Static Frames 20 9 20 2 3 3 Two TDM Channels with Static Frames 20 9 20 2 3 4 SI RA...

Page 23: ...r GSMR 21 3 21 2 2 Protocol Specific Mode Register PSMR 21 10 21 2 3 Data Synchronization Register DSR 21 10 21 2 4 Transmit on Demand Register TODR 21 10 21 3 SCC Buffer Descriptors BDs 21 11 21 4 SCC Parameter RAM 21 13 21 4 1 Function Code Registers RFCR and TFCR 21 15 21 4 2 Handling SCC Interrupts 21 15 21 4 3 SCC Initialization 21 16 21 4 4 Controlling SCC Timing with RTS CTS and CD 21 17 21...

Page 24: ...ling Errors in the SCC UART Controller 22 12 22 16 UART Mode Register PSMR 22 13 22 17 SCC UART Receive Buffer Descriptor RxBD 22 15 22 18 SCC UART Transmit Buffer Descriptor TxBD 22 18 22 19 SCC UART Event Register SCCE and Mask Register SCCM 22 19 22 20 SCC UART Status Register SCCS 22 22 22 21 SCC UART Programming Example 22 22 22 22 S Records Loader Application 22 23 Chapter 23 SCC HDLC Mode 2...

Page 25: ...alk Bus 24 1 24 2 Features 24 2 24 3 Connecting to AppleTalk 24 2 24 4 Programming the SCC in AppleTalk Mode 24 3 24 4 1 Programming the GSMR 24 3 24 4 2 Programming the PSMR 24 4 24 4 3 Programming the TODR 24 4 24 4 4 SCC AppleTalk Programming Example 24 4 Chapter 25 SCC Asynchronous HDLC Mode and IrDA 25 1 Asynchronous HDLC Features 25 1 25 2 Asynchronous HDLC Frame Transmission Processing 25 1...

Page 26: ...C BISYNC Channel Frame Transmission 26 2 26 3 SCC BISYNC Channel Frame Reception 26 3 26 4 SCC BISYNC Parameter RAM 26 3 26 5 SCC BISYNC Commands 26 5 26 6 SCC BISYNC Control Character Recognition 26 6 26 7 BISYNC SYNC Register BSYNC 26 7 26 8 SCC BISYNC DLE Register BDLE 26 8 26 9 Sending and Receiving the Synchronization Sequence 26 8 26 10 Handling Errors in the SCC BISYNC 26 9 26 11 BISYNC Mod...

Page 27: ...ogramming Example 27 22 Chapter 28 SCC Transparent Mode 28 1 Features 28 1 28 2 SCC Transparent Channel Frame Reception Process 28 2 28 3 Achieving Synchronization in Transparent Mode 28 2 28 3 1 Synchronization in NMSI Mode 28 3 28 3 1 1 In Line Synchronization Pattern 28 3 28 3 1 2 External Synchronization Signals 28 3 28 3 1 2 1 External Synchronization Example 28 4 28 3 1 3 Transparent Mode wi...

Page 28: ...9 29 2 6 Handling Interrupts in the SMC 29 9 29 3 SMC in UART Mode 29 9 29 3 1 SMC UART Features 29 10 29 3 2 SMC UART Specific Parameter RAM 29 10 29 3 3 SMC UART Channel Transmission Process 29 11 29 3 4 SMC UART Channel Reception Process 29 11 29 3 5 Data Handling Modes Character and Message Oriented 29 12 29 3 6 SMC UART Commands 29 12 29 3 7 Sending a Break 29 13 29 3 8 Sending a Preamble 29 ...

Page 29: ...ss 29 32 29 5 3 2 SMC GCI C I Channel Reception Process 29 33 29 5 4 SMC GCI Commands 29 33 29 5 5 SMC GCI Monitor Channel RxBD 29 33 29 5 6 SMC GCI Monitor Channel TxBD 29 34 29 5 7 SMC GCI C I Channel RxBD 29 34 29 5 8 SMC GCI C I Channel TxBD 29 35 29 5 9 SMC GCI Event Register SMCE Mask Register SMCM 29 35 Chapter 30 Serial Peripheral Interface SPI 30 1 Features 30 1 30 2 SPI Clocking and Sign...

Page 30: ... Host controller 31 11 31 8 USB Function and Host Parameter RAM Memory Map 31 11 31 9 Endpoint Parameter Block Pointer EPxPTR 31 12 31 10 Endpoint Parameter Block 31 13 31 10 1 Frame Number FRAME_N 31 14 31 10 1 1 Frame Number in Function Mode 31 14 31 10 1 2 Frame Number In Host Mode 31 14 31 10 2 USB Function Code Registers RFCR and TFCR 31 15 31 11 USB Function Programming Model 31 16 31 11 1 U...

Page 31: ...Considerations 32 5 32 4 I2 C Registers 32 5 32 4 1 I2 C Mode Register I2MOD 32 6 32 4 2 I2 C Address Register I2ADD 32 7 32 4 3 I2 C Baud Rate Generator Register I2BRG 32 7 32 4 4 I2 C Event Mask Registers I2CER I2CMR 32 7 32 4 5 I2 C Command Register I2COM 32 8 32 5 I2 C Parameter RAM 32 9 32 6 I2 C Commands 32 11 32 7 I2 C Buffer Descriptor BD Tables 32 11 32 7 1 I2 C Buffer Descriptors BDs 32 ...

Page 32: ...2 Pulsed Handshake Timing 33 17 33 8 Transparent Transfers 33 19 33 9 Implementing Centronics 33 19 33 9 1 PIP as a Centronics Transmitter 33 20 33 9 1 1 Centronics Tx Errors and the PIPE 33 21 33 9 2 PIP as a Centronics Receiver 33 21 33 9 2 1 Centronics Rx Errors and the PIPE 33 22 Chapter 34 Parallel I O Ports 34 1 Features 34 2 34 2 Port A 34 2 34 2 1 Port A Registers 34 3 34 2 1 1 Port A Open...

Page 33: ... Port E Data Register PEDAT 34 22 34 6 1 3 Port E Data Direction Register PEDIR 34 23 34 6 1 4 Port E Pin Assignment Register PEPAR 34 24 34 6 2 Port E Special Options Register PESO 34 25 Chapter 35 CPM Interrupt Controller 35 1 Features 35 1 35 2 CPM Interrupt Source Priorities 35 2 35 2 1 Programming Relative Priority Grouping and Spreading 35 3 35 2 2 Highest Priority Interrupt 35 4 35 2 3 Nest...

Page 34: ... 36 8 36 7 Serial ATM Operation 36 9 36 7 1 Serial ATM Transmit Overview 36 9 36 7 2 Serial ATM Receive Overview 36 9 36 7 2 1 Cell Delineation 36 10 36 7 3 Cell Payload Scrambling Descrambling 36 10 36 8 ATM Pace Control APC 36 10 36 9 Internal and External Channels Extended Channel Mode 36 11 36 10 ATM Port to Port PTP Cell Switching 36 11 36 11 Memory to Memory SAR 36 12 36 12 General ATM Initi...

Page 35: ...Address Mapping 39 1 39 1 1 Internal Look up Mechanism SRSTATE EXT 0 39 1 39 1 1 1 Adding a New Internal Channel 39 2 39 1 1 2 Removing an Internal Channel 39 2 39 1 2 Address Compression SRSTATE EXT ACP 11 39 2 39 1 2 1 First Level Addressing Table FLT 39 3 39 1 2 2 Second Level Addressing Tables SLTs 39 3 39 1 2 3 Address Compression Example 39 4 39 1 2 4 Preventing Channel Aliasing 39 4 39 1 2 ...

Page 36: ...40 1 1 APC Implementation 40 3 40 1 2 APC Parameters 40 4 40 1 3 Programming APC Scheduling Table Size and NCITS 40 5 40 1 4 Defining APC Slot Time 40 6 40 1 5 Programming Rates for CBR Channels 40 6 40 1 6 Programming Rates for VBR Channels 40 7 40 1 7 Programming Rates for UBR Channels 40 8 40 1 8 APC Initialization and Operating Considerations 40 9 40 1 9 Modifying Channel Transmit Pace 40 9 40...

Page 37: ...TxClav Slave RxClav and PHY Address Signals 42 3 42 2 3 Port C MasterRxClav Slave TxClav Signal 42 4 42 2 4 Port D UTOPIA Data and Control Signals 42 5 42 2 5 PCMCIA Port A Signal Multiplexing 42 6 42 2 6 RISC Controller Configuration Register RCCR 42 6 42 2 7 UTOPIA Mode Initialization 42 6 42 3 Serial ATM Configuration 42 7 42 3 1 RISC Controller Configuration Register RCCR 42 7 42 3 2 SCC Confi...

Page 38: ...Mechanism and Detection of Expired Buffers 44 12 44 4 5 2 Example of Timer CU Implementation 44 13 44 5 AAL2 Data Structures for Receive 44 13 44 5 1 Receive Packet Descriptor RPD 44 13 44 5 2 AAL2_Rx_Queue 44 16 44 5 3 AAL2 Receive Connection Table AAL2_RCT 44 17 44 5 4 Example of AAL2 Receive 44 19 44 6 Systems Restrictions When Using the AAL2 Functionality 44 20 44 7 Global AAL2 Data Structures...

Page 39: ...45 8 45 2 10 1 Transmission Errors 45 9 45 2 10 2 Reception Errors 45 9 45 2 11 SDMA Bus Arbitration and Transfers 45 9 45 2 12 The SDMA Registers 45 10 45 2 12 1 SDMA Configuration Register SDCR 45 10 45 3 Programming Model 45 10 45 3 1 Communications Processor Timing Register CPTR 45 11 45 3 2 Parameter RAM 45 12 45 3 2 1 RAM Perfect Match Address Low Register ADDR_LOW 45 13 45 3 2 2 RAM Perfect...

Page 40: ...45 32 45 3 3 1 Hardware Initialization 45 32 45 3 3 2 User Initialization before Setting ECNTRL ETHER_EN 45 33 45 3 3 2 1 Descriptor Controller Initialization 45 34 45 3 3 2 2 User Initialization after Setting ECNTRL ETHER_EN 45 34 45 3 4 Buffer Descriptors BDs 45 34 45 3 4 1 Ethernet Receive Buffer Descriptor RxBD 45 35 45 3 4 2 Ethernet Transmit Buffer Descriptor TxBD 45 36 Part VIII Integrated ...

Page 41: ... DEU Key Registers 48 12 48 1 12 DEU FIFOs 48 12 48 2 Message Digest Execution Units MDEU 48 12 48 2 1 MDEU Register Map 48 12 48 2 2 MDEU Mode Register 48 13 48 2 2 1 Recommended settings for MDEU Mode Register 48 14 48 2 3 MDEU Key Size Register 48 15 48 2 4 MDEU Data Size Register 48 15 48 2 5 MDEU Reset Control Register 48 16 48 2 6 MDEU Status Register 48 17 48 2 7 MDEU Interrupt Status Regis...

Page 42: ...or Header 49 2 49 2 2 Descriptor Length and Pointer Fields 49 4 49 3 Descriptor Chaining 49 6 49 3 1 Null Fields 49 7 49 4 Dynamic Descriptors 49 7 Chapter 50 SEC Lite Crypto Channel 50 1 Crypto Channel Registers 50 2 50 1 1 Crypto Channel Configuration Register CCCR 50 2 50 1 2 Crypto Channel Pointer Status Registers CCPSR 50 4 50 1 3 Crypto Channel Current Descriptor Pointer Register CDPR 50 10 ...

Page 43: ...Interface Module 52 1 Communications Processor Timing Register CPTR 52 1 52 2 Master Slave Interface 52 2 52 2 1 Bus Access 52 2 52 2 2 Bus Master 52 2 52 2 3 Master Read 52 2 52 2 3 1 Target Aborts 52 3 52 2 4 Master Write 52 3 52 2 5 Misaligned Data 52 3 52 2 6 Target Access 52 4 Part IX System Debugging and Testing Support Intended Audience 1 Contents 1 Suggested Reading 1 MPC8xx Documentation ...

Page 44: ... Description 53 10 53 2 3 1 Instruction Support Detailed Description 53 10 53 2 3 2 Load Store Support Detailed Description 53 11 53 2 3 3 The Counters 53 13 53 2 3 4 Trap Enable Programming 53 14 53 2 4 Operation Details 53 14 53 2 4 1 Restrictions 53 14 53 2 4 2 Byte and Half Word Working Modes 53 14 53 2 4 2 1 Examples 53 14 53 2 4 3 Context Dependent Filter 53 16 53 2 4 4 Ignore First Match 53...

Page 45: ...ions Debug Mode 53 30 53 3 2 5 1 Serial Data Into Development Port 53 30 53 3 2 5 2 Serial Data Out of Development Port 53 31 53 3 2 5 3 Fast Download Procedure 53 32 53 4 Software Monitor Debugger Support 53 33 53 4 1 Freeze Indication 53 33 53 5 Development Support Programming Model 53 33 53 5 1 Development Support Registers 53 35 53 5 1 1 Comparator A H Value Registers CMPA CMPH 53 35 53 5 1 2 ...

Page 46: ... 1 A 3 BE Mode A 2 A 4 TLE Mode A 2 A 4 1 TLE Mode System Examples A 4 A 5 PPC LE Mode A 5 A 5 1 I O Addressing in PPC LE Mode A 7 A 6 Setting the Endian Mode Of Operation A 7 Appendix B Serial Communications Performance Appendix C Register Quick Reference Guide C 1 User Registers C 1 C 2 Supervisor Registers C 2 C 3 MPC885 Specific SPRs C 2 Appendix D Instruction Set Listings D 1 Instructions Sor...

Page 47: ...F 4 Appendix G MPC870 G 1 MPC87066 Overview G 1 G 2 Implementation Impact of Differences between MPC885 and MPC870 G 2 G 2 1 Unimplemented Pins G 2 G 2 2 Other Unimplemented Signals G 3 G 2 3 SMC General Set Up G 4 Appendix H Serial ATM Scrambling Reception and SI Programming H 1 ATM Cell Payload Scrambling H 1 H 2 Receiving Serial ATM Cells H 1 H 2 1 HEC Delineation Mechanism H 3 H 3 Serial Inter...

Page 48: ...MPC885 PowerQUICC Family Reference Manual Rev 2 xlviii Freescale Semiconductor Contents Paragraph Number Title Page Number Index 1 ...

Page 49: ...tency 6 18 7 1 MPC885 Instruction Cache Organization 7 3 7 2 MPC885 Data Cache Organization 7 5 7 3 Instruction Cache Control and Status Register IC_CST 7 6 7 4 Instruction Cache Address Register IC_ADR 7 7 7 5 Instruction Cache Data Port Register IC_DAT 7 8 7 6 Data Cache Control and Status Register DC_CST 7 11 7 7 Data Cache Address Register DC_ADR 7 13 7 8 Data Cache Data Port Register DC_DAT 7...

Page 50: ...tion Timing Example 1 9 2 9 3 Writeback Arbitration Timing Example 2 9 2 9 4 Private Writeback Bus Load Timing 9 3 9 5 External Load Timing 9 3 9 6 Full Completion Queue Timing 9 4 9 7 Branch Folding Timing 9 4 9 8 Branch Prediction Timing 9 5 9 9 Bus Latency for String Instructions 9 8 10 1 System Configuration and Protection Logic 10 3 10 2 Internal Memory Map Register IMMR 10 4 10 3 SIU Module ...

Page 51: ...12 3 12 3 MPC875 Signals and Pin Numbers Part 1 12 24 12 4 MPC875 Signals and Pin Numbers Part 2 12 25 12 5 Three State Buffers and Active Pull Up Buffers 12 41 13 1 Input Sample Window 13 2 13 2 MPC885 Bus Signals 13 3 13 3 Basic Transfer Protocol 13 6 13 4 Basic Flow Diagram of a Single Beat Read Cycle 13 7 13 5 Basic Timing Single Beat Read Cycle Zero Wait States 13 8 13 6 Basic Timing Single B...

Page 52: ...requency Dividers for GCLKx 14 10 14 6 Divided System Clocks GCLKx Timing Diagram 14 11 14 7 Memory Controller and External Bus Clocks Timing Diagram for EBDF 0 and EBDF 1 14 11 14 8 Memory Controller and External Bus Clocks Timing Diagram for CSRC 0 and DFNH 1 or CSRC 1 and DFNL 0 14 12 14 9 BRGCLK Divider 14 13 14 10 SYNCCLK Divider 14 14 14 11 MPC885 Power Rails 14 15 14 12 System Clock and Res...

Page 53: ...rnal Master GPCM Handled Memory Access Timing TRLX 0 15 31 15 31 User Programmable Machine Block Diagram 15 32 15 32 RAM Array Indexing 15 33 15 33 Memory Periodic Timer Request Block Diagram 15 34 15 34 UPM Clock Scheme One Division Factor 1 15 35 15 35 UPM Clock Scheme Two Division Factor 2 15 35 15 36 UPM Signals Timing Example One Division Factor 1 EBDF 00 15 36 15 37 UPM Signals Timing Exampl...

Page 54: ...CMCIA Interface Input Pins Register PIPR 16 9 16 4 PCMCIA Interface Status Changed Register PSCR 16 10 16 5 PCMCIA Interface Enable Register PER 16 11 16 6 PCMCIA Interface General Control Register PGCRx 16 13 16 7 PCMCIA Base Register PBR 16 14 16 8 PCMCIA Option Register 0 7 POR0 POR7 16 14 16 9 PCMCIA Single Beat Read Cycle PRS 0 PSST 1 PSL 3 PSHT 1 16 17 16 10 PCMCIA Single Beat Read Cycle PRS...

Page 55: ...SDCR 19 4 19 4 SDMA Status Register SDSR 19 5 19 5 DMA Channel Mode Register DCMR 19 8 19 6 IDMA Status Registers IDSR1 IDSR2 19 9 19 7 IDMAx Channel s BD Table 19 10 19 8 IDMA Buffer Descriptor Structure 19 11 19 9 Function Code Registers SFCR and DFCR 19 12 19 10 SDACK Timing Diagram Single Address Peripheral Write Externally Generated TA 19 17 19 11 SDACK Timing Diagram Single Address Periphera...

Page 56: ...r Configuration Registers BRGCn 20 38 21 1 SCC Block Diagram 21 2 21 2 GSMR_H General SCC Mode Register High Order 21 4 21 3 GSMR_L General SCC Mode Register Low Order 21 6 21 4 Data Synchronization Register DSR 21 10 21 5 Transmit on Demand Register TODR 21 10 21 6 SCC Buffer Descriptors BDs 21 12 21 7 SCCx Buffer Descriptor and Buffer Structure 21 12 21 8 Function Code Registers RFCR and TFCR 21...

Page 57: ...us Collision 23 19 23 13 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance 23 19 23 14 HDLC Bus Transmission Line Configuration 23 20 23 15 Delayed RTS Mode 23 20 23 16 HDLC Bus TDM Transmission Line Configuration 23 21 24 1 LocalTalk Frame Format 24 1 24 2 Connecting the MPC885 to LocalTalk 24 3 25 1 Asynchronous HDLC Frame Structure 25 2 25 2 Receive Flowchart 25 3 25 3 TXCTL_TBL RXCT...

Page 58: ...e SCCS 28 12 29 1 SMC Block Diagram 29 1 29 2 SMC Mode Registers SMCMRn 29 3 29 3 SMC Memory Structure 29 5 29 4 SMC Function Code Registers RFCR TFCR 29 7 29 5 SMC UART Frame Format 29 10 29 6 SMC UART Receive BD RxBD 29 14 29 7 SMC UART Receiving using RxBDs 29 16 29 8 SMC UART Transmit BD TxBD 29 17 29 9 SMC UART Event Register SMCE Mask Register SMCM 29 18 29 10 SMC UART Interrupts Example 29 ...

Page 59: ... 11 USB Function Code Registers RFCR and TFCR 31 15 31 12 USB Mode Register USMOD 31 16 31 13 USB Slave Address Register USADR 31 17 31 14 USB Endpoint Registers USEP0 USEP3 31 18 31 15 USB Command Register USCOM 31 19 31 16 USB Event Register USBER 31 20 31 17 USB Status Register USBS 31 21 31 18 USB Memory Structure 31 22 31 19 USB Receive Buffer Descriptor RxBD 31 23 31 20 USB Transmit Buffer D...

Page 60: ...iver Timing Mode 3 33 19 33 19 PIP Transparent Transfers 33 19 33 20 The PIP Centronics Interface Signals 33 20 33 21 PIP as a Centronics Transmitter 33 21 33 22 PIP as a Centronics Receiver 33 22 34 1 Port A Open Drain Register PAODR 34 4 34 2 Port A Data Register PADAT 34 4 34 3 Port A Data Direction Register PADIR 34 5 34 4 Port A Pin Assignment Register PAPAR 34 5 34 5 Block Diagram for PA15 T...

Page 61: ...4 37 5 ATM TxBD 37 7 37 6 ATM TxBD in Expanded Cell Mode UTOPIA Only 37 7 37 7 Connection Tables in Dual port RAM and External Memory 37 11 37 8 Receive Connection Table RCT 37 12 37 9 PTP Receive Connection Table PTP RCT 37 16 37 10 Transmit Connection Table TCT 37 20 37 11 PTP Transmit Connection Table PTP TCT 37 24 37 12 TCTE Examples for Internal and External VBR UBR Channels 37 28 37 13 Trans...

Page 62: ...hree APC Priority Levels Combining APC Scheduling Tables and APC PTP queues 40 21 41 1 ATM Interrupt Queue 41 1 41 2 UTOPIA Event Register IDSR1 and Mask Register IDMR1 41 2 41 3 Serial ATM Event Register SCCE and Mask Register SCCM 41 3 41 4 Interrupt Queue Entry 41 4 41 5 Interrupt Queue Mask IMASK 41 6 42 1 Port D Pin Assignment Register PDPAR 42 1 42 2 System Clock Control Register SCCR 42 3 4...

Page 63: ... 17 MII_DATA Register 45 23 45 18 MII_SPEED Register 45 24 45 19 R_BOUND Register 45 26 45 20 R_FSTART Register 45 27 45 21 X_WMRK Register 45 27 45 22 X_FSTART Register 45 28 45 23 FUN_CODE Register 45 29 45 24 R_CNTRL Register 45 30 45 25 R_HASH Register 45 31 45 26 X_CNTRL Register 45 32 45 27 Receive Buffer Descriptor RxBD 45 35 45 28 Transmit Buffer Descriptor TxBD 45 37 46 1 SEC Lite Connect...

Page 64: ... Header 49 2 49 3 OP_n sub fields 49 3 49 4 Descriptor Length Field 49 5 49 5 Descriptor Pointer Field 49 5 49 6 Next Descriptor Pointer Field 49 6 49 7 Chain of Descriptors 49 7 50 1 Crypto Channel Configuration Register 50 2 50 2 Crypto Channel Pointer Status Register 1 50 5 50 3 Crypto Channel Pointer Status Register 2 50 5 50 4 Crypto Channel Current Descriptor Pointer Register 50 10 50 5 Fetc...

Page 65: ...ers CMPG CMPH 53 36 53 17 Breakpoint Address Register BAR 53 36 53 18 Instruction Support Control Register ICTRL 53 37 53 19 Load Store Support Comparators Control Register LCTRL1 53 39 53 20 Load Store Support AND OR Control Register LCTRL2 53 40 53 21 Breakpoint Counter Value and Control Registers COUNTA COUNTB 53 42 53 22 Interrupt Cause Register ICR 53 43 53 23 Debug Enable Register DER 53 44 ...

Page 66: ...MPC885 PowerQUICC Family Reference Manual Rev 2 lxvi Freescale Semiconductor Figures Figure Number Title Page Number ...

Page 67: ...7 4 9 MPC885 Specific Supervisor Level SPRs 4 9 4 10 MPC885 Specific Debug Level SPRs 4 10 4 11 Addresses of SPRs Located Outside of the Core 4 11 5 1 Memory Operands 5 1 5 2 Integer Arithmetic Instructions 5 7 5 3 Integer Compare Instructions 5 9 5 4 Integer Logical Instructions 5 9 5 5 Integer Rotate Instructions 5 10 5 6 Integer Shift Instructions 5 10 5 7 Integer Load Instructions 5 11 5 8 Int...

Page 68: ...3 6 14 Register Settings After a Data TLB Miss Exception 6 13 6 15 Register Settings after an Instruction TLB Error Exception 6 14 6 16 Register Settings After a Data TLB Error Exception 6 14 6 17 Register Settings after a Debug Exception 6 15 6 18 Additional SPRs that Affect MSR Bits 6 17 6 19 Exception Latency 6 19 6 20 Before and After Exceptions 6 19 7 1 MPC885 Family 7 1 7 2 Instruction Cache...

Page 69: ...PC885 Specific MMU Exceptions 8 31 9 1 Instruction Execution Timing 9 5 9 2 Load Store Instruction Timing 9 7 10 1 Multiplexing Control 10 3 10 2 MMR Field Descriptions 10 5 10 3 SIUMCR Field Descriptions 10 6 10 4 SYPCR Field Descriptions 10 8 10 5 TESR Field Descriptions 10 9 10 6 Key Registers 10 9 10 7 Priority of SIU Interrupt Sources 10 13 10 8 IRQ0 Versus IRQx Operation 10 14 10 9 SIPEND Fi...

Page 70: ...tem Frequency Generation 14 6 14 3 Power On Reset DPLL Configuration 14 7 14 4 Functionality Summary of the Clocks 14 8 14 5 PITCLK Configuration at PORESET 14 14 14 6 TMBCLK Configuration 14 15 14 7 MPC885 Modules vs Power Rails 14 16 14 8 SCCR Field Descriptions 14 19 14 9 PLPRCR Field Descriptions 14 21 14 10 PLPRCR CSR and DER CHSTPE Bit Combinations 14 23 15 1 Memory Controller Register Usage...

Page 71: ...d Descriptions 16 15 17 1 TGCR Field Descriptions 17 8 17 2 TMR1 TMR4 Field Descriptions 17 9 17 3 TER Field Descriptions 17 11 18 1 Peripheral Prioritization 18 3 18 2 CP Microcode Revision Number 18 4 18 3 CPM Configuration Register CPMCFG Bit Settings 18 5 18 4 RCCR Field Descriptions 18 5 18 5 RMDS Field Descriptions 18 7 18 6 CPCR Field Descriptions 18 8 18 7 CP Command Opcodes 18 8 18 8 CP C...

Page 72: ...MR_L Field Descriptions 21 7 21 4 TODR Field Descriptions 21 11 21 5 SCC Parameter RAM Map for All Protocols 21 13 21 6 RFCRx TFCRx Field Descriptions 21 15 21 7 SCCx Event Mask and Status Registers 21 16 21 8 Preamble Requirements 21 23 21 9 DPLL Codings 21 24 22 1 UART Specific SCC Parameter RAM Memory Map 22 4 22 2 Transmit Commands 22 6 22 3 Receive Commands 22 6 22 4 Control Character Table R...

Page 73: ...criptions 25 10 25 10 Asynchronous HDLC RxBD Status and Control Field Descriptions 25 11 25 11 Asynchronous HDLC TxBD Status and Control Field Descriptions 25 12 26 1 SCC BISYNC Parameter RAM Memory Map 26 3 26 2 Transmit Commands 26 5 26 3 Receive Commands 26 5 26 4 Control Character Table and RCCM Field Descriptions 26 7 26 5 BSYNC Field Descriptions 26 8 26 6 BDLE Field Descriptions 26 8 26 7 R...

Page 74: ...criptions 29 7 29 4 SMC UART Specific Parameter RAM Memory Map 29 10 29 5 Transmit Commands 29 12 29 6 Receive Commands 29 12 29 7 SMC UART Errors 29 13 29 8 SMC UART RxBD Status and Control Field Descriptions 29 14 29 9 SMC UART TxBD Status and Control Field Descriptions 29 17 29 10 SMCE SMCM Field Descriptions 29 18 29 11 SMC Transparent Transmit Commands 29 25 29 12 SMC Transparent Receive Comm...

Page 75: ...1 21 31 14 USB RxBD Fields 31 23 31 15 USB Function TxBD Fields 31 25 31 16 USB Host TxBD Fields 31 27 31 17 USB Controller Transmission Errors 31 29 31 18 USB Controller Reception Errors 31 29 32 1 I2MOD Field Descriptions 32 6 32 2 I2ADD Field Descriptions 32 7 32 3 I2BRG Field Descriptions 32 7 32 4 I2CER I2CMR Field Descriptions 32 8 32 5 I2COM Field Descriptions 32 8 32 6 I2C Parameter RAM Me...

Page 76: ...34 11 Port C Pin Assignment 34 12 34 12 Port C Pin Assignment for UTOPIA 34 14 34 13 PCDAT Bit Descriptions 34 14 34 14 PCDIR Bit Descriptions 34 15 34 15 PCPAR Bit Descriptions 34 15 34 16 PCSO Bit Descriptions 34 16 34 17 PCINT Bit Descriptions 34 17 34 18 Port D Pin Assignment 34 18 34 19 PDDAT Bit Descriptions 34 19 34 20 PDDIR Bit Descriptions 34 19 34 21 PDPAR Field Descriptions 34 20 34 22 ...

Page 77: ... 14 38 14 MPHYST Field Descriptions 38 16 38 15 ASTATUS Register Field Descriptions 38 16 39 1 Types of Cell Filtering 39 6 39 2 Performance Monitoring Cell Fields 39 8 39 3 PM Table Field Descriptions 39 13 39 4 Available PTP Options 39 16 39 5 PTP BD Field Descriptions 39 17 39 6 Address Signals in a Multi PHY System 39 19 39 7 CPCR ATM Specific Field Descriptions 39 22 39 8 ATM Commands 39 23 4...

Page 78: ...E_HIGH Field Descriptions 45 15 45 11 HASH_TABLE_LOW Field Descriptions 45 16 45 12 R_DES_START Field Descriptions 45 16 45 13 X_DES_START Field Descriptions 45 17 45 14 R_BUFF_SIZE Field Descriptions 45 18 45 15 ECNTRL Field Descriptions 45 19 45 16 I_EVENT I_MASK Field Descriptions 45 20 45 17 IVEC Field Descriptions 45 21 45 18 R_DES_ACTIVE Field Descriptions 45 22 45 19 X_DES_ACTIVE Field Desc...

Page 79: ...gister Field Descriptions 48 19 48 11 MDEU Interrupt Control Register Field Descriptions 48 21 48 12 AESU Mode Register Field Descriptions 48 25 48 13 AESU Reset Control Register Field Descriptions 48 28 48 14 AESU Status Register Field Descriptions 48 30 48 15 AESU Interrupt Status Register Field Descriptions 48 31 48 16 AESU Interrupt Control Register Field Descriptions 48 33 48 17 Counter Modul...

Page 80: ... 53 12 Status Data Shifted Out of Development Port Shift Register 53 30 53 13 Debug Instructions Data Shifted Into Development Port Shift Register 53 31 53 14 MPC885 Specific Development Support and Debug SPRs 53 34 53 15 Development Support Debug Registers Protection 53 35 53 16 CMPA CMPD Field Descriptions 53 35 53 17 CMPE CMPF Field Descriptions 53 36 53 18 CMPG CMPH Field Descriptions 53 36 53...

Page 81: ...ons 6 D 20 D 13 Integer Load Instructions D 21 D 14 Integer Store Instructions D 21 D 15 Integer Load and Store with Byte Reverse Instructions D 22 D 16 Integer Load and Store Multiple Instructions D 22 D 17 Integer Load and Store String Instructions D 22 D 18 Memory Synchronization Instructions D 22 D 19 Floating Point Load Instructions 6 D 23 D 20 Floating Point Store Instructions 6 D 23 D 21 Fl...

Page 82: ...O Form D 34 D 40 A Form D 35 D 41 M Form D 36 D 42 MD Form D 36 D 43 MDS Form D 36 D 44 Instruction Set Legend D 39 H 1 Serial Interface Register Programming Example for Serial ATM H 4 H 2 ATM Cell Transmission and Reception Programming Example H 4 H 3 TDMA Port Pin Requirements H 5 H 4 Port Register Programming Example H 5 ...

Page 83: ... of this book As with any technical documentation it is the readers responsibility to be sure they are using the most recent version of the documentation Contact your sales representative for more information Before Using This Manual Before using this manual determine whether it is the latest revision and if there are errata or addenda To locate any published errata or updates for this document re...

Page 84: ...xx core These chapters provide details concerning the processor core as an implementation of the PowerPC architecture Chapter 3 The MPC8xx Core provides an overview of the MPC885 core Chapter 4 MPC8xx Core Register Set describes the hardware registers accessible to the MPC885 core These include both architecturally defined and MPC885 specific registers Chapter 5 MPC885 Instruction Set describes th...

Page 85: ...host adapter module which provides all control logic for a PCMCIA socket interface and requires only additional external analog power switching logic and buffering Part V Communications Processor Module describes the configuration clocking and operation of the various communications protocols supported by the MPC885 Chapter 17 Communications Processor Module and CPM Timers provides a brief overvie...

Page 86: ...ISDN devices Chapter 31 Universal Serial Bus USB describes the MPC885 implementation of the universal serial bus USB controller Chapter 32 I2C Controller describes the MPC885 implementation of the inter integrated circuit I2 C controller which allows data to be exchanged with other I2 C devices such as microcontrollers EEPROMs real time clock devices and A D converters Chapter 33 Parallel Interfac...

Page 87: ...lti classic SAR MPHY ATM operation including the UTOPIA modes and the signals provided for UTOPIA support Chapter 44 AAL2 Implementation describes the implementation of AAL2 Part VII Fast Ethernet Controller FEC describes the MPC885 support for 10 100 base T Ethernet It consists of the following chapter Chapter 45 Fast Ethernet Controller FEC describes the Fast Ethernet Controller which is impleme...

Page 88: ...ins a quick reference guide to the MPC885 registers Appendix D Instruction Set Listings contains tables of the PowerPC instructions supported by the MPC885 Appendix E MPC880 describes characteristics specific to the MPC880 Appendix F MPC875 describes characteristics specific to the MPC875 Appendix G MPC870 describes characteristics specific to the MPC870 Appendix H Serial ATM Scrambling Reception ...

Page 89: ...r s Pocket Reference Guide for the PowerPC Architecture MPCPRGREF D This foldout card provides an overview of PowerPC registers instructions and exceptions for 32 bit implementations Application notes These short documents address specific design issues useful to programmers and engineers working with Freescale processors Additional literature is published as new processors become available For a ...

Page 90: ...ynchronous transfer mode BD Buffer descriptor BIST Built in self test BPU Branch processing unit BRI Basic rate interface BUID Bus unit ID CAM Content addressable memory CEPT Conférence Européene des Administrations des Postes et des Télécommunications European Conference of Postal and Telecommunications Administrations CP Communications processor CPM Communications processor module CR Condition r...

Page 91: ...L Inter chip digital link IEEE Institute of Electrical and Electronics Engineers IrDA Infrared Data Association ISDN Integrated services digital network ITLB Instruction translation lookaside buffer IU Integer unit JTAG Joint test action group LIFO Last in first out LR Link register LRU Least recently used LSB Least significant byte lsb Least significant bit LSU Load store unit MAC Multiply accumu...

Page 92: ...l communications controller SCP Serial control port SDLC Synchronous Data Link Control SDMA Serial DMA SEC Lite Integrated security engine a low cost derivative of the MPC185 security engine SI Serial interface SIMM Signed immediate value SIU System interface unit SMC Serial management controller SNA Systems network architecture SPI Serial peripheral interface SPR Special purpose register SPRGn Re...

Page 93: ...ironment architecture XER Register used primarily for indicating conditions such as carries and overflows for integer operations Table iii Terminology Conventions The Architecture Specification This Manual Data storage interrupt DSI DSI exception Extended mnemonics Simplified mnemonics Instruction storage interrupt ISI ISI exception Interrupt Exception Privileged mode or privileged state Superviso...

Page 94: ...ence Manual Rev 2 xciv Freescale Semiconductor DS ds FLM FM FXM CRM RA RB RT RS rA rB rD rS respectively SI SIMM U IMM UI UIMM 0 0 shaded Table iv Instruction Field Conventions continued The Architecture Specification Equivalent to ...

Page 95: ...ncludes cross references that indicate where each register is described in detail Conventions This part uses the following notational conventions mnemonics Instruction mnemonics are shown in lowercase bold italics Italics indicate variable command parameters for example bcctrx Book titles in text are set in italics 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number rA rB In...

Page 96: ...ct machine GPR General purpose register HDLC High level data link control I2 C Inter integrated circuit IEEE Institute of Electrical and Electronics Engineers IrDA Infrared Data Association ISDN Integrated services digital network ITLB Instruction translation lookaside buffer IU Integer unit JTAG Joint Test Action Group LRU Least recently used cache replacement algorithm LSU Load store unit MMU Me...

Page 97: ... System interface unit SMC Serial management controller SPI Serial peripheral interface SPR Special purpose register SRAM Static random access memory TB Time base register TDM Time division multiplexed TLB Translation lookaside buffer TSA Time slot assigner Tx Transmit UART Universal asynchronous receiver transmitter UISA User instruction set architecture UPM User programmable machine VEA Virtual ...

Page 98: ...MPC885 PowerQUICC Family Reference Manual Rev 2 I 4 Freescale Semiconductor ...

Page 99: ... processor core The MPC885 family is a PowerPC architecture based quad integrated communications controller PowerQUICC The CPU on the MPC885 is the MPC8xx core a 32 bit microprocessor which implements the PowerPC architecture incorporating memory management units MMUs and instruction and data caches The MPC885 is the superset of this family of devices and is mainly described in this document Table...

Page 100: ...Us with 32 entry TLB fully associative instruction and data TLBs MMUs support multiple page sizes of 4 16 and 512 Kbytes as well as 8 Mbytes 16 virtual address spaces and 16 protection groups Advanced on chip emulation debug mode The MPC885 family provides enhanced ATM functionality as found on the MPC862 and MPC866 Families The MPC885 family includes the following Improved operation administratio...

Page 101: ...counting Interrupt can be masked on reference match and event capture Two Fast Ethernet controllers FEC Two 10 100 Mbps Ethernet IEEE 802 3 CDMA CS interface through MII and or RMII interfaces System integration unit SIU Bus monitor Software watchdog Periodic interrupt timer PIT Clock synthesizer Decrementer and time base Reset controller IEEE 1149 1 test access port JTAG Security engine optimized...

Page 102: ...ands for example GRACEFUL STOP TRANSMIT ENTER HUNT MODE and RESTART TRANSMIT Supports continuous mode transmission and reception on all serial channels 8 Kbytes of dual port RAM The MPC885 family has several serial DMA SDMA channels to support the CPM Three parallel I O registers with open drain capability Four baud rate generators Independent can be connected to any SCC or SMC Allow changes durin...

Page 103: ...c retransmission upon transmit error The USB host controller features are as follows Supports control bulk interrupt and isochronous data transfers CRC16 generation and checking NRZI encoding decoding with bit stuffing Supports both 12 and 1 5 Mbps data rates automatic generation of preamble token and data rate configuration Note that low speed operation requires an external hub Flexible data buff...

Page 104: ...pport only one PCMCIA socket Eight memory or I O windows supported Debug interface Eight comparators four operate on instruction address two operate on data address and two operate on data Supports conditions Each watchpoint can generate a breakpoint internally Normal high and normal low power modes to conserve power 1 8 V core and 3 3 V I O operation with 5 V TTL compatibility The MPC885 MPC880 c...

Page 105: ...hannels System Functions 16 Kbyte Instruction Cache 32 Entry ITLB Instruction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port and UTOPIA Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Program ROM SCC1 Serial Interface I2C SPI SMC2 SMC1 SCC2 MPC8xx Processor Core DMAs FIFOs...

Page 106: ...ache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Program ROM Serial Interface I2 C SPI SMC2 SMC1 MPC8xx Processor Core SCC2 Serial Interface PCMCIA ATA Interface Virtual IDMA and Serial DMAs SCC4 Security Engine AESU DEU MDEU Controller Channel ...

Page 107: ...hannels System Functions 16 Kbyte Instruction Cache 32 Entry ITLB Instruction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port and UTOPIA Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Program ROM SCC1 Serial Interface I2C SPI SMC2 SMC1 SCC2 MPC8xx Processor Core DMAs FIFOs...

Page 108: ...truction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Program ROM Serial Interface I2 C SPI SMC2 SMC1 MPC8xx Processor Core SCC3 Serial Interface PCMCIA ATA Interface Virtual IDMA and Serial DMAs SCC4 DMAs FIFOs 10 100 MIII...

Page 109: ...MU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Program ROM Serial Interface SPI SMC1 MPC8xx Processor Core SCC4 Serial Interface PCMCIA ATA Interface Virtual IDMA and Serial DMAs Security Engine AESU DEU MDEU Controller Channe...

Page 110: ...16 Kbyte Instruction Cache 32 Entry ITLB Instruction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port and UTOPIA Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Program ROM SCC1 Serial Interface I2 C SPI SMC2 SMC1 SCC2 MPC8xx Processor Core DMAs FIFOs 10 100 MII Base T Media...

Page 111: ...dependent DMA Channels System Functions 16 Kbyte Instruction Cache 32 Entry ITLB Instruction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port and UTOPIA Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Program ROM SCC1 Serial Interface I2 C SPI SMC2 SMC1 SCC2 MPC8xx Processor...

Page 112: ...16 Kbyte Instruction Cache 32 Entry ITLB Instruction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port and UTOPIA Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Program ROM SCC1 Serial Interface I2 C SPI SMC2 SMC1 SCC2 MPC8xx Processor Core DMAs FIFOs 10 100 MII Base T Media...

Page 113: ...e supports integer operations on a 32 bit internal data path and 32 bit arithmetic hardware The core interface to the internal and external buses is 32 bits wide Bus System Interface Unit SIU Embedded Parallel I O Memory Controller 4 Timers Interrupt Controllers 8 Kbyte Dual Port RAM System Functions 8 Kbyte Instruction Cache 32 Entry ITLB Instruction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU ...

Page 114: ...ts six watchpoint pins that detect software events Four of its eight internal comparators operate on the effective address on the address bus two operate on the effective address on the data address bus and two operate on the data bus The core can make comparisons using operators and to generate watchpoints Each watchpoint can then generate a breakpoint that can be configured to trigger in a progr...

Page 115: ...e is determined by a clock divider allowing the operating system to reduce the processor s operational frequency and operate in Normal Low mode 1 6 Security Engine A block diagram of the Security Engine s internal architecture is shown in Figure 1 10 The 8xx bus interface 8xx IF module is designed to transfer 32 bit words between the 8xx bus and any register inside the Security Engine core An oper...

Page 116: ... USB The universal serial bus USB is an industry standard extension to the PC architecture The USB controller on the MPC885 family supports data exchange between a wide range of simultaneously accessible peripherals Attached peripherals share USB bandwidth through a host scheduled token based protocol The USB physical interconnect is a tiered star topology and the center of each star is a hub Each...

Page 117: ... controller a time slot assigner five parallel ports a parallel interface port four independent baud rate generators and serial DMA channels to support the SCCs SMCs SPI and I2C The SDMAs provide two channels of general purpose DMA capability for each communications channel They offer high speed transfers 32 bit data movement buffer chaining and independent request and acknowledge logic The four g...

Page 118: ...MPC885 Overview MPC885 PowerQUICC Family Reference Manual Rev 2 1 20 Freescale Semiconductor ...

Page 119: ...0D Reserved 6 bytes 00E SWSR Software service register 16 bits 10 7 1 10 21 010 SIPEND SIU interrupt pending register 32 bits 10 5 3 10 13 014 SIMASK SIU interrupt mask register 32 bits 10 5 4 2 10 16 018 SIEL SIU interrupt edge level register 32 bits 10 5 4 3 10 17 01C SIVEC SIU interrupt vector register 32 bits 10 5 4 4 10 17 020 TESR Transfer error status register 32 bits 10 4 4 10 8 024 02F Re...

Page 120: ...us changed register 32 bits 16 4 2 16 10 0EC 0EF Reserved 4 bytes 0F0 PIPR PCMCIA interface input pins register 32 bits 16 4 1 16 8 0F4 0F7 Reserved 4 bytes 0F8 PER PCMCIA interface enable register 32 bits 16 4 3 16 11 0FC 0FF Reserved 4 bytes Memory Controller 100 BR0 Base register bank 0 32 bits 15 4 1 15 8 104 OR0 Option register bank 0 32 bits 15 4 2 15 11 108 BR1 Base register bank 1 32 bits ...

Page 121: ...8 17C MDR Memory data register 32 bits 15 4 6 15 17 180 1FF Reserved 128 bytes System Integration Timers 200 TBSCR Timebase status and control register 16 bits 10 9 3 10 25 202 203 Reserved 2 bytes 204 TBREFA Timebase reference register A 32 bits 10 9 2 10 24 208 TBREFB Timebase reference register B 32 bits 20C 21F Reserved 20 bytes 220 Reserved 16 bits 222 223 Reserved 2 bytes 224 Reserved 32 bit...

Page 122: ...0 Reserved 32 bits 324 Reserved 32 bits 328 Reserved 32 bits 32C Reserved 32 bits 330 33F Reserved 16 bytes 340 PISCRK Periodic interrupt status and control register key 32 bits 10 10 1 10 26 344 PITCK Periodic interrupt count register key 32 bits 10 10 2 10 27 348 37F Reserved 56 bytes Clocks and Reset Keys 380 SCCRK System clock control key 32 bits 10 4 5 10 9 384 PLPRCRK PLL and reset control r...

Page 123: ... 3 3 3 19 9 915 917 Reserved 3 bytes 918 IDSR2 IDMA2 status register 8 bits 19 3 3 2 19 9 919 91B Reserved 3 bytes 91C IDMR2 IDMA2 mask register 8 bits 19 3 3 3 19 9 91D 92F Reserved 19 bytes Communications Processor Module Interrupt Control 930 CIVR CPM interrupt vector register 16 bits 35 5 5 35 9 932 93F Reserved 14 bytes 940 CICR CPM interrupt configuration register 32 bits 35 5 1 35 6 944 CIP...

Page 124: ...imers 980 TGCR Timer global configuration register 16 bits 17 2 3 1 17 8 982 98F Reserved 14 bytes 990 TMR1 Timer 1 mode register 16 bits 17 2 4 17 9 992 TMR2 Timer 2 mode register 16 bits 17 2 4 17 9 994 TRR1 Timer 1 reference register 16 bits 17 2 4 1 17 10 996 TRR2 Timer 2 reference register 16 bits 17 2 4 1 17 10 998 TCR1 Timer 1 capture register 16 bits 17 2 4 2 17 10 99A TCR2 Timer 2 capture...

Page 125: ...CC RCTR1 RISC controller trap register 1 16 bits Used only by optional RAM microcode 9CE RCTR2 RISC controller trap register 2 16 bits Used only by optional RAM microcode 9D0 RCTR3 RISC controller trap register 3 16 bits Used only by optional RAM microcode 9D2 RCTR4 RISC controller trap register 4 16 bits Used only by optional RAM microcode 9D4 9D5 Reserved 2 bytes 9D6 RTER RISC timer event regist...

Page 126: ...ter 8 bits A18 A1F Reserved 8 bytes Serial Communications Controller 2 SCC2 A20 GSMR_L2 SCC2 general mode register 32 bits 21 2 1 21 3 A24 GSMR_H2 SCC2 general mode register 32 bits 21 2 1 21 3 A28 PSMR2 SCC2 protocol specific mode register 16 bits 21 2 2 21 10 22 16 22 13 UART 25 13 1 25 8 Asynchronous HDLC 26 11 26 10 BISYNC 27 17 27 15 Ethernet 28 8 28 7 Transparent A2A A2B Reserved 16 bits A2C...

Page 127: ... Asynchronous HDLC 26 11 26 10 BISYNC 27 17 27 15 Ethernet 28 8 28 7 Transparent A4A A4B Reserved 2 bytes A4C TODR3 SCC3 transmit on demand register 16 bits 21 2 4 21 10 A4E DSR3 SCC3 data synchronization register 16 bits 21 2 3 21 10 A50 SCCE3 SCC3 event register 16 bits 22 20 22 22 UART 23 12 23 14 HDLC 25 13 25 8 Asynchronous HDLC 26 15 26 15 BISYNC 28 12 28 11 Transparent A52 A53 Reserved 2 by...

Page 128: ...rved 1 byte A77 SCCS4 SCC4 status register 8 bits 22 20 22 22 UART 23 12 23 14 HDLC 26 15 26 15 BiSYNC 28 12 28 11 Transparent A78 A81 Reserved 10 bytes Serial Management Controller 1 SMC1 A82 SMCMR1 SMC1 mode register 16 bits 29 2 1 29 2 A84 A85 Reserved 2 bytes A86 SMCE1 SMC1 event register 8 bits 29 3 12 29 18 UART 29 4 11 29 29 Transparent 29 5 9 29 35 GCI A87 A89 Reserved 3 bytes A8A SMCM1 SM...

Page 129: ...es AB6 PTPR PIP timing parameters register 16 bits 33 4 4 33 10 Port B Registers AB8 PBDIR Port B data direction register 32 bits 34 3 1 3 34 10 ABC PBPAR Port B pin assignment register 32 bits 34 3 1 4 34 11 AC0 PBODR Port B open drain register 32 bits 34 3 1 1 34 9 AC4 PBDAT Port B data register 32 bits 34 3 1 2 34 9 Port E Registers AC8 PEDIR Port E data direction register 32 bits 34 6 1 3 34 2...

Page 130: ...Ethernet Controller 1 FEC E00 ADDR_LOW register 32 bits 45 3 2 1 45 13 E04 ADDR_HIGH 32 bits 45 3 2 2 45 14 E08 HASH_TABLE_HIGH 32 bits 45 3 2 3 45 14 E0C HASH_TABLE_LOW 32 bits 45 3 2 4 45 15 E10 R_DES_START 32 bits 45 3 2 5 45 16 E14 X_DES_START 32 bits 45 3 2 6 45 16 E18 R_BUFF_SIZE 32 bits 45 3 2 7 45 17 E1C E3F Reserved 36 bytes E40 ECNTRL 32 bits 45 3 2 8 45 18 E44 IEVENT 32 bits 45 3 2 9 45...

Page 131: ... bits 45 3 2 1 45 13 1E04 ADDR2_HIGH 32 bits 45 3 2 2 45 14 1E08 HASH_TABLE2_HIGH 32 bits 45 3 2 3 45 14 1E0C HASH_TABLE2_LOW 32 bits 45 3 2 4 45 15 1E10 R2_DES_START 32 bits 45 3 2 5 45 16 1E14 X2_DES_START 32 bits 45 3 2 6 45 16 1E18 R_BUFF2_SIZE 32 bits 45 3 2 7 45 17 1E1C 1E3F Reserved 36 bytes 1E40 ECNTRL2 32 bits 45 3 2 8 45 18 1E44 IEVENT2 32 bits 45 3 2 9 45 19 1E48 IMASK2 32 bits 45 3 2 9...

Page 132: ...ytes 18 7 1 18 12 3000 3BFF Dual port system RAM expansion 3 072 bytes 18 7 1 18 12 3C00 3FFF PRAM Dual port parameter RAM 1 024 bytes 18 7 3 18 13 Table 2 2 Security Engine Memory Map IMMR 14 15 10 SEC Lite Address SEC Lite Module Description Size1 Section Page 00000 01007 Reserved 4104 bytes 01008 Controller Interrupt Mask 64 bits 51 1 1 51 1 01010 Controller Interrupt Status 64 bits 51 1 2 51 2...

Page 133: ... 3 7 48 30 04038 AESU Interrupt control register 64 bits 48 3 8 48 32 04040 0404F Reserved 16 bytes 04050 AESU End of message register 64 bits 48 3 9 48 34 04058 040FF Reserved 168 bytes 04100 AESU IV register 64 bits 48 3 9 1 48 34 04108 043FF Reserved 760 bytes 04400 04408 AESU Key memory 12 bytes 48 3 9 4 48 36 0440C 047FF Reserved 1012 bytes 04800 04FFF AESU FIFO 2048 bytes 48 3 9 5 48 36 0500...

Page 134: ...rol register 64 bits 48 2 5 48 16 06020 06027 Reserved 8 bytes 06028 MDEU Status register 64 bits 48 2 6 48 17 06030 MDEU Interrupt status register 64 bits 48 2 7 48 18 06038 MDEU Interrupt control register 64 bits 48 2 8 48 20 06040 0604F Reserved 16 bytes 06050 MDEU EU_GO 64 bits 48 2 9 48 21 06058 060FF Reserved 168 bytes 06100 06127 MDEU Context memory 32 bytes 48 2 10 48 22 06128 063FF Reserv...

Page 135: ...nd MPC885 specific registers Chapter 5 MPC885 Instruction Set describes the instructions implemented by the MPC885 These instructions are organized by the level of architecture in which they are implemented UISA VEA and OEA Chapter 6 Exceptions describes the exception model implemented on the MPC885 Chapter 7 Instruction and Data Caches describes the organization of the on chip instruction and dat...

Page 136: ...are intended for use with the corresponding user s manuals Hardware specifications Hardware specifications provide specific data regarding bus timing signal behavior and AC DC and thermal characteristics as well as other design considerations Separate hardware specifications are provided for each part described in this book Technical summaries Each device has a technical summary that provides an o...

Page 137: ...hown in uppercase text Specific bits fields or numerical ranges appear in brackets For example MSR LE refers to the little endian mode enable bit in the machine state register x In certain contexts such as in a signal encoding or a bit field indicates a don t care n Indicates an undefined numerical value NOT logical operator AND logical operator OR logical operator Acronyms and Abbreviations Table...

Page 138: ...Engineers ITLB Instruction translation lookaside buffer IU Integer unit LIFO Last in first out LR Link register LRU Least recently used LSB Least significant byte lsb Least significant bit LSU Load store unit MMU Memory management unit MSB Most significant byte msb Most significant bit MSR Machine state register NaN Not a number No op No operation OEA Operating environment architecture PCI Periphe...

Page 139: ...A User instruction set architecture VA Virtual address VEA Virtual environment architecture XER Register used primarily for indicating conditions such as carries and overflows for integer operations Table II 2 Terminology Conventions The Architecture Specification This Manual Data storage interrupt DSI DSI exception Extended mnemonics Simplified mnemonics Instruction storage interrupt ISI ISI exce...

Page 140: ...truction field notation conventions used in this manual Table II 3 Instruction Field Conventions The Architecture Specification Equivalent To BA BB BT crbA crbB crbD respectively BF BFA crfD crfS respectively D d DS ds FLM FM FXM CRM RA RB RT RS rA rB rD rS respectively SI SIMM U IMM UI UIMM 0 0 shaded ...

Page 141: ...nt instructions load store and arithmetic Likewise it supports those registers defined by the PowerPC architecture necessary for the supported instructions The MPC885 core adheres to portions of the PowerPC architecture definition for supervisor operations For example it implements the PowerPC exception model excluding inappropriate exceptions such as those that support floating point operations T...

Page 142: ... loading and storing data between the memory system and the GPRs Uniform length instructions to allow simplified instruction pipelining and parallel processing instruction dispatch mechanisms Nondestructive use of registers for arithmetic instructions in which the second third and sometimes the fourth operand typically specify source registers for calculations whose results are usually stored in t...

Page 143: ...nment in which multiple devices can access memory defines aspects of the cache model defines cache control instructions and defines the time base facility from a user level perspective Implementations that conform to the PowerPC VEA also adhere to the UISA but may not necessarily adhere to the OEA PowerPC operating environment architecture OEA The OEA defines supervisor level called privileged sta...

Page 144: ...IQ 0 Instruction Queue CTR CR LR Branch Processing Unit Integer Unit XER GPR File 32 Entry Load Store Unit LSU Data MMU Tags U Bus Interface Instruction MMU Tags Fetcher 32 Bit 32 Bit One Instruction Retired per Clock 32 Bit One Instruction 32 Bit 32 Bit ALU Performs EA Calculation 32 Bit 32 Bit L Bus Power Dissipation Control Time Base Counter Decrementer JTAG Additional Features INSTRUCTION UNIT...

Page 145: ...s the instruction set and memory management The MPC885 implements all PowerPC asynchronous exceptions interrupts system reset machine check decrementer and external interrupts MPC885 specific exceptions are PowerPC compliant Separate 32 entry instruction and data translation lookaside buffers TLBs Core specific features Fully static design Additional registers that support the MPC885 specific feat...

Page 146: ... used as breakpoints All instructions enter the CQ along with processor state information that can be affected by the instruction s execution Executed arithmetic instructions pass their results both to rename buffers and to the architected registers typically GPRs but to ensure program order instructions remain in the CQ until they can be retired If an exception occurs before the instruction can b...

Page 147: ...h processor instructions including flow control and CR instructions Table 9 1 on page 9 5 in Chapter 9 describes instruction latencies 3 4 3 1 Branch Operations Because branch instructions can change program flow and because most branches cannot be resolved at the same time they are fetched program branching can keep a processor from operating at maximum instruction throughput If a branch is mispr...

Page 148: ...lso implements a branch reservation station and static branch prediction so branches can be resolved as early as possible The reservation station allows a branch instruction to pass from the IQ before its condition is ready With the branch out of the way fetching can continue as the branch is evaluated Static branch prediction defined by the PowerPC UISA determines which instruction stream is pref...

Page 149: ...owerPC registers The MPC885 implements the user registers defined by the UISA and VEA portions of the architecture except for those that support floating point operations PowerPC registers implemented on the MPC885 are described in Chapter 4 MPC8xx Core Register Set and Section 4 1 2 PowerPC Registers Supervisor Registers Implementation specific registers These are all special purpose registers SP...

Page 150: ...tore Unit The load store unit LSU transfers all data between the GPRs and the processor s internal bus It is implemented as an independent execution unit so that stalls in the memory pipeline affect the master instruction pipeline only if there is a data dependency The following lists the LSU s main features All instructions implemented in hardware including unaligned string and multiple accesses ...

Page 151: ... If all operands are available the LSU takes the instruction and enables the sequencer to issue a new instruction Using a dedicated interface the LSU notifies the integer unit of the need to calculate the EA All load store instructions are executed and finished in order If no prior instructions are in the address queue the load store operation is issued to the data cache when the instruction execu...

Page 152: ...s nonspeculative one clock cycle after the previous load store bus cycle ends only if all prior instructions have finished without an exception The nonspeculative identification relates to the state of the cycle s associated instruction For lmw although the accesses are pipelined into the bus they are all marked as nonspeculative because the instruction is nonspeculative If a single register load ...

Page 153: ... to the external bus interface When an stwcx instruction addresses external memory and the external bus interface determines that the reservation was lost it blocks the external bus access and notifies the LSU The MPC885 supports the memory reservation mechanism in a hierarchical bus structure For reservations on internal memory an lwarx causes on chip snoop logic to latch the address This logic n...

Page 154: ...ue on write and return the value last set for it on read Classes of instructions Required instructions except floating point load store and compute instructions are implemented in hardware Optional instructions are executed by implementation dependent code any attempt to execute one of these commands causes the core to take the software emulation exception offset 0x01000 Illegal and reserved instr...

Page 155: ... store with update instructions where rA 0 the EA is written into r0 For load with update instructions where rA rD rA is boundedly undefined Integer load store multiple instructions For these types of instructions EA must be a multiple of four If it is not the system alignment error handler is invoked For an lmw instruction if rA is in the range of registers to be loaded the instruction completes ...

Page 156: ...VEA except for 8 byte operands Because the MPC885 uses a 32 bit data bus performance is good rather than optimal See Section 3 6 3 5 Unaligned Accesses for a description of integer unaligned instruction execution and timing see Section 9 2 2 String Instruction Latency for a description of string instruction timing Memory control instructions The MPC885 interprets cache control instructions as if t...

Page 157: ... mechanism that requires an intermediate 52 bit virtual address It also does not support block address translation or the associated block address translation SPRs In its place the MPC885 s internal memory space includes memory mapped control registers and memory used by various modules on the chip This memory is part of the main memory as seen by the core but cannot be accessed by any external sy...

Page 158: ...The MPC8xx Core MPC885 PowerQUICC Family Reference Manual Rev 2 3 18 Freescale Semiconductor ...

Page 159: ...n Section 4 1 1 PowerPC Registers User Registers Supervisor registers which can be accessed by supervisor software and in some cases are the automatic result of hardware activity such as when an exception is taken and when the system is reset All supervisor registers are defined by the operating environment architecture OEA except the time base registers which can be written to only by supervisor ...

Page 160: ... the contents of XER 0 3 to a CR field An mcrxr instruction can copy a specified XER field to a specified CR field Table 4 1 User Level PowerPC Registers Description Name Reference Section Access Level Serialize Access General purpose registers GPRs The thirty two 32 bit GPRs are used for source and destination operands User Condition register CR See Section 4 1 1 1 1 Condition Register CR User On...

Page 161: ...or integer instructions CR 0 3 reflects the result as a signed quantity The CR bits are interpreted as shown in Table 4 3 If any portion of the result is undefined the value placed into CR0 0 3 is undefined Note that CR0 may not reflect the true that is infinitely precise result if overflow occurs 4 1 1 1 3 XER Figure 4 2 shows XER bit assignments Settings are based on the final result produced by...

Page 162: ...xr that cannot overflow 1 OV Overflow Set to indicate that an overflow occurred during execution of an instruction Add subtract from and negate instructions with OE 1 set OV if the carry out of the msb is not equal to the carry out of the msb 1 and clear it otherwise Multiply low and divide instructions with OE 1 set OV if the result cannot be represented in 32 bits mullw divw divwu and clear it o...

Page 163: ... other time its value is boundedly undefined This term is defined very Table 4 6 Supervisor Level PowerPC SPRs SPR Number Name Reference Section Serialize Access Decimal SPR 5 9 SPR 0 4 18 00000 10010 DSISR See the Programming Environments Manual and Section 4 1 2 1 DAR DSISR and BAR Operation Write Full sync Read Sync relative to load store operations 19 00000 10011 DAR See the Programming Enviro...

Page 164: ...evel PowerPC registers implemented by the MPC885 For more details see the Programming Environments Manual for 32 Bit Processors 4 1 2 3 1 Machine State Register MSR The 32 bit machine state register MSR is used to configure such parameters as the privilege level whether translation is enabled and the endian mode It can be read by the mfmsr instruction and modified by the mtmsr sc and rfi instructi...

Page 165: ...rt to the value latched during hard reset configuration Figure 4 3 Machine State Register MSR Table 4 8 MSR Field Descriptions Bits Name Description 0 12 Reserved 13 Reserved Must be written as a 0 14 Reserved 15 ILE Exception little endian mode When an exception occurs this bit is copied into MSR LE to select the endian mode for the context established by the exception 16 EE1 External interrupt e...

Page 166: ...e Table 6 1 0 Exceptions are vectored to the physical address 0x000n_nnnn 1 Exceptions are vectored to the physical address 0xFFFn_nnnn The reset value of IP is determined by the IIP bit bit 2 in the hard reset configuration word See Section 11 3 1 1 Hard Reset Configuration Word Subsequent soft resets cause IP to revert to the value latched during hard reset configuration 26 IR 1 Instruction addr...

Page 167: ...ion Cache Control Registers Write as a store 562 10001 10010 IC_DAT Section 7 3 1 Instruction Cache Control Registers Write as a store 568 10001 11000 DC_CST Section 7 3 2 Data Cache Control Registers Write as a store 569 10001 11001 DC_ADR Section 7 3 2 Data Cache Control Registers Write as a store 570 10001 11010 DC_DAT Section 7 3 2 Data Cache Control Registers Write as a store 784 11000 10000 ...

Page 168: ... 8 5 DMMU Tablewalk Control Register MD_TWC Write as a store 798 11000 11110 MD_RPN Section 8 8 7 DMMU Real Page Number Register MD_RPN Write as a store 799 11000 11111 M_TW M_SAVE Section 8 8 11 MMU Tablewalk Special Register M_TW Write as a store 824 11001 11000 MD_CAM Section 8 8 12 4 DMMU CAM Entry Read Register MD_CAM Write as a store 825 11001 11001 MD_RAM0 Section 8 8 12 5 DMMU RAM Entry Re...

Page 169: ...0100 11001 CMPF Write Fetch sync Read Sync relative to load store operations 154 00100 11010 CMPG Write Fetch sync Read Sync relative to load store operations 155 00100 11011 CMPH Write Fetch sync Read Sync relative to load store operations 156 00100 11100 LCTRL1 Write Fetch sync Read Sync relative to load store operations 157 00100 11101 LCTRL2 Write Fetch sync Read Sync relative to load store op...

Page 170: ...y the system reset interrupt are MSR SRR0 and SRR1 no other reset activity occurs Section 6 1 2 1 System Reset Interrupt 0x00100 describes values for these registers after system reset When a hard or soft reset occurs registers are set in the same way as follows SRR0 SRR1 Set to an undefined value MSR IP Programmable through the IIP bit in the hard reset configuration word MSR ME Cleared ICTRL Cle...

Page 171: ...le words or for the load store multiple and move assist instructions a sequence of bytes or words The address of a memory operand is the address of its first byte that is of its lowest numbered byte 5 1 2 Aligned and Misaligned Accesses The operand of a single register memory access instruction has a natural alignment boundary equal to the operand length In other words the natural address of an op...

Page 172: ...r load and store instructions only For more information see Section 5 2 4 2 Load and Store Instructions Flow control instructions These include branching instructions condition register logical instructions and other instructions that affect the instruction flow For more information see Section 5 2 4 3 Branch and Flow Control Instructions Trap instructions These instructions test for a specified s...

Page 173: ...the MPC885 The class is determined by examining the primary opcode and the extended opcode if any If the opcode or combination of opcode and extended opcode is not that of a defined instruction or of a reserved instruction the instruction is illegal In future versions of the architecture instruction codings that are now illegal may become assigned to instructions in the architecture or may be rese...

Page 174: ...amming Environments Manual and Section 5 2 1 4 Reserved Instruction Class Notice that extended opcodes for instructions that are defined only for 64 bit implementations are illegal in 32 bit implementations and vice versa The following primary opcodes have unused extended opcodes 17 19 31 59 63 primary opcodes 30 and 62 are illegal for all 32 bit implementations but as 64 bit opcodes they have som...

Page 175: ... 2 2 2 Effective Address Calculation An effective address EA is the 32 bit sum computed by the processor when executing a memory access or branch instruction or when fetching the next sequential instruction For a memory access instruction if the sum of the effective address and the operand length exceeds the maximum effective address the memory operand is considered to wrap around from the maximum...

Page 176: ... instruction is execution synchronizing It ensures that all preceding instructions have completed execution and will not cause an exception before the instruction executes but does not ensure subsequent instructions execute in the newly established environment For example if the mtmsr sets the MSR PR bit unless an isync immediately follows the mtmsr instruction a privileged instruction could be ex...

Page 177: ...ming Environments Manual Note that some of the instructions have the following optional features CR Update The dot suffix on the mnemonic enables the update of the CR Overflow option The o suffix indicates that the XER overflow bit is enabled 5 2 4 PowerPC UISA Instructions The PowerPC UISA includes the base user level instruction set excluding a few user level cache control synchronization and ti...

Page 178: ...ate Carrying addic rD rA SIMM Add Immediate Carrying and Record addic rD rA SIMM Subtract from Immediate Carrying subfic rD rA SIMM Add Carrying addc addc addco addco rD rA rB Subtract from Carrying subfc subfc subfco subfco rD rA rB Add Extended adde adde addeo addeo rD rA rB Subtract from Extended subfe subfe subfeo subfeo rD rA rB Add to Minus One Extended addme addme addmeo addmeo rD rA Subtra...

Page 179: ...ical instructions do not affect the XER SO XER OV and XER CA bits For simplified mnemonics examples for the integer logical operations see Appendix F Simplified Mnemonics in the Programming Environments Manual Table 5 3 Integer Compare Instructions Name Mnemonic Syntax1 1 Implementation Note In these instructions the L bit is applicable for 64 bit implementations For the MPC885 if L 1 the instruct...

Page 180: ...teger rotate instructions are listed in Table 5 5 The integer shift instructions perform left and right shifts Immediate form logical unsigned shift operations are obtained by specifying masks and shift values for certain rotate instructions Simplified mnemonics are provided to make coding of such shifts simpler and easier to understand The integer shift instructions are listed in Table 5 6 Equiva...

Page 181: ...ations that are not naturally aligned may suffer performance degradation Refer to Section 6 1 2 6 1 Integer Alignment Exceptions for additional information about load and store address alignment exceptions 5 2 4 2 2 Register Indirect Integer Load Instructions For integer load instructions the byte half word or word addressed by the EA is loaded into rD Many integer load instructions have an update...

Page 182: ...everse instructions When used in a system operating with the default big endian byte order these instructions have the effect of loading and storing data in little endian order Likewise when used in a system operating with little endian byte order these instructions have the effect of loading and storing data in big endian order For more information about Load Word and Zero lwz rD d rA Load Word a...

Page 183: ...low movement of data from memory to registers or from registers to memory without concern for alignment These instructions can be used for a short move between arbitrary memory locations or to initiate a long move between misaligned memory fields When the MPC885 is operating with little endian byte order execution of a load or store string instruction causes the system alignment error handler to b...

Page 184: ... one of these instructions it scans the execution pipelines to determine whether an instruction in progress may affect the particular CR bit If no interlock is found the branch can be resolved immediately by checking the bit in the CR and taking the action defined for the branch instruction If an interlock is detected the branch is considered unresolved and the direction of the branch is predicted...

Page 185: ...tions are invalid in the MPC885 5 2 4 4 Trap Instructions The trap instructions shown in Table 5 14 are provided to test for a specified set of conditions If any of the conditions tested by a trap instruction are met the system trap handler is invoked If the tested conditions are not met instruction execution continues normally Table 5 12 Branch Instructions Name Mnemonic Syntax Branch b ba bl bla...

Page 186: ...nstructions and about related aspects of memory synchronization Table 5 16 lists the UISA memory synchronization instructions for the MPC885 The sync instruction delays execution of subsequent instructions until previous instructions have completed to the point that they can no longer cause an exception and until all previous memory accesses are performed globally the sync operation is not broadca...

Page 187: ...ocation is not modified and a bit is cleared in the CR If the store was successful the sequence of instructions from the read of the semaphore to the store that updated the semaphore appear to have been executed atomically that is no other processor or mechanism modified the semaphore location between the read and the update thus providing the equivalent of a real atomic operation However in reali...

Page 188: ...ndition register instructions specified by the UISA the VEA defines the Move from Time Base mftb instruction for reading the contents of the time base register The mftb is a user level instruction and is shown in Table 5 17 Simplified mnemonics are provided for the mftb instruction so it can be coded with the TBR name as part of the mnemonic rather than requiring it to be coded as an operand The m...

Page 189: ... Furthermore load store instructions that update the MMU page tables in external memory should both be preceded and followed by an isync to ensure that instructions before and after such instructions are fetched and completed in the appropriate context 5 2 5 3 Memory Control Instructions VEA Memory control instructions include the following types Cache management instructions Translation lookaside...

Page 190: ...at permits a user program to call on the system to perform a service and causes the processor to take an exception The Return from Interrupt rfi instruction is a supervisor level instruction that is useful for returning from an exception handler 5 2 6 2 Processor Control Instructions OEA Processor control instructions read from and write to the condition register CR machine state register MSR and ...

Page 191: ...s a 10 bit binary number in the instruction The number coded is split into two 5 bit halves that are reversed in the instruction encoding with the high order 5 bits appearing in bits 16 20 of the instruction encoding and the low order 5 bits in bits 11 15 If the SPR field contains a value not shown in Section 4 1 MPC885 Register Implementation either the program exception handler is invoked or res...

Page 192: ...MPC885 Instruction Set MPC885 PowerQUICC Family Reference Manual Rev 2 5 22 Freescale Semiconductor ...

Page 193: ... a precise exception model This means that when an exception is taken the following conditions are met Subsequent instructions in the program flow are discarded Previous instructions finish and write back their results The address of the faulting instruction is saved in SRR0 and the machine state of the interrupted process is saved in SRR1 When the exception is taken the instruction causing the ex...

Page 194: ...0 Alignment Alignment exceptions result from the following conditions The operand of a load store multiple is not word aligned The operand of a lwarx or stwcx is not word aligned The operand of a load store instruction is not naturally aligned when MSR LE 1 Trying to execute a multiple string instruction when MSR LE 1 See Section 6 1 2 3 DSI Exception 0x00300 0x00700 Program The MPC885 cannot gene...

Page 195: ... exceptions in the order of detection within the instruction processing Implementation Specific Exceptions 0x01000 Software emulation See Section 6 1 3 1 Software Emulation Exception 0x01000 0x01100 Instruction TLB miss See Section 6 1 3 2 Instruction TLB Miss Exception 0x01100 0x01200 Data TLB miss See Section 6 1 3 3 Data TLB Miss Exception 0x01200 0x01300 Instruction TLB error See Section 6 1 3...

Page 196: ...uction Trap Trap instruction 8 DTLB miss 2 Data TLB miss 9 DTLB error 2 Data TLB protection translation error 10 Machine check Load or store access error 11 Debug L breakpoint 2 Match detection 1 The trace mechanism is implemented by letting one instruction go as if no trace is enabled and trapping the second instruction This of course refers to this second instruction 2 MPC885 specific exception ...

Page 197: ... at offset 0x00200 and the registers are set as shown in Table 6 5 Table 6 4 Register Settings After a System Reset Interrupt Exception Register Setting SRR0 Set to the EA of the next instruction of the interrupted process SRR1 Saves the machine status before exceptions and to restore status when an rfi instruction is executed 1 4 0 10 15 0 Others Loaded from MSR 16 31 SRR1 30 is cleared only by l...

Page 198: ...ruction at the end of the queue can retire The instruction must be completed without exception The instruction must either be a mtspr mtmsr rfi a memory reference or a memory or cache control instruction Instructions not fitting these criteria are discarded along with any execution results After the exception handler completes execution resumes with the first instruction that was discarded If all ...

Page 199: ...n may yield boundedly undefined results instead of causing an alignment exception For all other cases listed above an implementation may execute the instruction correctly instead of causing an alignment exception The register settings for alignment exceptions are shown in Table 6 7 Table 6 6 Register Settings after an External Interrupt Register Setting Description SRR0 Set to the effective addres...

Page 200: ...operating in user mode MSR PR is set It is also generated for mtspr or mfspr instructions that have an invalid SPR MSR POW 0 ILE EE 0 PR 0 FP 0 ME SE 0 BE 0 IP IR 0 DR 0 RI 0 LE Set to value of ILE DSISR 0 14 Cleared 15 16 For instructions that use register indirect with index addressing set to bits 29 30 of the instruction encoding For instructions that use register indirect with immediate index ...

Page 201: ...ng an exception request when it passes through zero A decrementer exception request remains pending until the decrementer exception is taken and then it is cancelled The decrementer implementation meets the following requirements The counters for the decrementer and the time base counter are driven by the same fundamental time base Loading a GPR from the decrementer does not affect the decrementer...

Page 202: ...d into SRR0 MSR bits are saved in SRR1 as shown in Table 6 10 and a system call exception is generated The system call exception causes the next instruction to be fetched from offset 0x00C00 from the physical base address indicated by the new setting of MSR IP As with most other exceptions this exception is context synchronizing Refer to Section 5 2 2 3 1 Context Synchronization regarding actions ...

Page 203: ... 11 Floating Point Assist Exception The floating point assist exception is not generated by the MPC885 Attempting to execute a floating point causes an instruction implementation specific software emulation exception Table 6 10 Register Settings After a System Call Exception Register Setting Description SRR0 Set to the effective address of the instruction following the System Call instruction SRR1...

Page 204: ...ore unimplemented register and SPR 0 0 or MSR PR 0 no program exception condition In addition Table 6 12 shows the following set of registers Execution resumes at offset 0x01000 from the base address indicated by MSR IP 6 1 3 2 Instruction TLB Miss Exception 0x01100 This type of exception occurs if MSR IR 1 and an attempt is made to fetch an instruction from a page whose effective page number cann...

Page 205: ...ent or page valid bit of this page is cleared in the translation table Note that although the MPC885 does not implement segment registers as they are defined by the OEA the concept of segment is retained as the memory space accessible to the level one table descriptors The fetch access violates memory protection The fetch access is to guarded memory Table 6 13 Register Settings After an Instructio...

Page 206: ...Register Settings after an Instruction TLB Error Exception Register Setting SRR0 Set to the EA of the instruction that caused the exception SRR1 Note that only one of bits 1 3 and 4 will be set 1 1 if the translation of an attempted access is not in the translation tables Otherwise 0 2 0 3 1 if the fetch access was to guarded memory when MSR IR 1 Otherwise 0 4 1 if the access is not permitted by t...

Page 207: ... Set to the EA of the data access that caused the exception Table 6 17 Register Settings after a Debug Exception Register Setting SRR0 For I breakpoints set to the EA of the instruction that caused the exception For L breakpoint set to the EA of the instruction after the one that caused the exception For development port maskable request or a peripheral breakpoint set to the EA of the instruction ...

Page 208: ...he architectural state the CQ must record the value of the destination before the instruction is executed The destination of a store instruction however is in memory and it is not practical from a performance standpoint to always read memory before writing it Therefore stores issue immediately to store buffers but do not update memory until all previous instructions have finished executing without...

Page 209: ...y the exception handler after saving the machine state in SRR0 and SRR1 and DAR and DSISR if needed and cleared by the exception handler before retrieving the machine state In critical code sections where MSR EE is cleared but SRR0 and SRR1 are not busy MSR RI should remain set In such cases if an exception occurs the process is restartable Table 6 18 lists SPRs that facilitate manipulation of MSR...

Page 210: ...10 11 1 2 3 4 5 6 7 8 0 Fetch in IQ In dispatch entry IQ0 Execute 5 9 Complete In CQ 6 5 4 3 IH2 IH1 IH4 IH3 IH2 IH1 IH4 IH3 IH2 IH1 7 6 5 4 2 1 3 3 2 Instruction Queue Completion Queue In retirement entry CQ0 2 1 6 IH1 IH2 IH3 IH4 12 IH4 IH3 IH2 IH1 16 17 13 14 15 18 IH4 IH3 IH2 IH1 IH4 IH3 IH2 IH1 IH5 IH4 IH3 IH2 IH6 IH5 IH4 IH3 IH1 IH2 IH1 IH7 IH6 IH5 IH4 IH8 IH7 IH6 IH5 IH3 IH2 IH4 IH3 A B C D...

Page 211: ...ption handler For full completion queue restore time it is no less than two clocks E The MSR and instruction pointer of the executing process have been saved and control has been transferred to the exception handler routine Exception handler instructions that have been fetched can be dispatched 6 1 7 Partially Completed Instructions Partially completed instructions can be reexecuted after the exce...

Page 212: ...Debug I breakpoint 1 Any Before Faulting instruction Debug L breakpoint 1 Load store After Faulting instruction 4 Software emulation 1 NA Before Faulting instruction Floating point unavailable Floating point Before Faulting instruction 1 Implementation specific exceptions not defined by the PowerPC architecture Table 6 20 Before and After Exceptions continued Exception Type Instruction Type Before...

Page 213: ...ate 8 Kbyte instruction and 8 Kbyte data caches Harvard architecture The MPC885 instruction cache is two way set associative and the data cache is two way set associative The caches implement a least recently used LRU replacement algorithm within each set The cache directories are physically addressed The physical real address tag is stored in the cache directory Both the instruction and data cach...

Page 214: ... bus masters The SIU receives requests for bus operations from the instruction and data caches and executes the operations according to the external bus protocol The data cache provides buffers for load and store bus operations The data cache supplies data to the GPRs by means of a 32 bit interface to the load store unit The LSU is directly coupled to the data cache to allow efficient movement of ...

Page 215: ...er physical address bits PA 0 19 Address translation occurs in parallel with set selection from A 20 27 The instruction cache implements a single state bit for each cache block that indicates whether the cache block is valid or invalid The MPC885 does not support snooping of the instruction cache All memory is COMP Way0 28 31 27 20 19 0 Word Select Bidirectional Multiplexer 2 1 Hit0 HIT Data Effec...

Page 216: ...ate All Command The instruction cache also implements a lock bit for each cache block that allows instructions to be loaded into the instruction cache and locked providing fast and deterministic execution time for critical code segments The MPC885 supports commands for locking and unlocking individual cache blocks and for unlocking all the cache blocks at once 7 2 Data Cache Organization The MPC88...

Page 217: ...he set for the MPC885 Bits A 28 29 select a word within a block The tags consist of the high order physical address bits PA 0 19 Address translation occurs in parallel with set selection from A 20 27 COMP Way0 28 31 27 20 19 0 Bidirectional Multiplexer 2 1 Hit0 HIT Data Effective Address Set0 Set1 Set255 Set254 COMP Tag0 w0 w1 w2 w3 Valid Bit Lock Bit Tag1 w0 w1 w2 w3 Tag255 w0 w1 w2 w3 Tag254 w0 ...

Page 218: ...tions describes the cache control instructions 7 3 1 Instruction Cache Control Registers The MPC885 implements three special purpose registers SPRs to control the instruction cache the instruction cache control and status register IC_CST the instruction cache address register IC_ADR and the instruction cache data port register IC_DAT The instruction cache can be disabled invalidated or locked by i...

Page 219: ...011 Load and lock cache block 100 Unlock cache block 101 Unlock all 110 Invalidate all 111 Reserved Note that reading these bits always returns 0b000 7 9 Reserved 10 CCER1 Instruction cache error type 1 bus error during an IC_CST load load cache block command 0 No error detected 1 Error detected Note that this is a read only sticky bit set only by the MPC885 when an error is detected Reading this ...

Page 220: ...ead the IC_DAT register Table 7 3 Instruction Cache Address Register IC_ADR Bits Name Description 0 31 ADR Instruction cache command address When programming the IC_CST CMD load and lock cache block and unlock cache block commands IC_ADR contains the physical address in external memory of the desired cache block element When reading the data tags and status contained within the instruction cache I...

Page 221: ...cache the instruction cache disable command IC_CST CMD 0b010 is used to disable the instruction cache Neither of these commands has any error cases The current state of the instruction cache is available by reading the instruction cache enable status bit IC_CST IEN When disabled the MPC885 ignores the instruction cache valid bit and operates as if all accesses have caching inhibited access attribu...

Page 222: ...oad and lock cache block commands before checking the termination status These bits are set by the MPC885 and are cleared by software Note that the MPC885 considers all zero wait state devices on the internal bus as caching inhibited For this reason software should not perform load and lock cache block operations from these devices on the internal bus 7 3 1 2 3 Instruction Cache Unlock Cache Block...

Page 223: ...che data port register DC_DAT The data cache can be disabled invalidated locked or flushed by issuing the appropriate commands to the data cache control registers DC_CST DC_ADR and DC_DAT Also the data cache control registers can be used to read the contents and tags of specific data cache blocks DC_CST DFWT can be used to force the data cache into write through mode DC_CST LES controls true littl...

Page 224: ...on the physical address before accessing the internal U bus Also for accesses originating from the MPC8xx core the SIU unmunges the address and swaps the bytes of data within each word at the external bus internal U bus boundary See Appendix A Byte Ordering for more information about MPC885 byte ordering Note that this is a read only bit Any attempt to write to it is ignored This bit is programmed...

Page 225: ...e MPC885 when an error is detected Reading this bit clears it 12 31 Reserved 0 31 Field ADR Reset R W R W SPR 569 Figure 7 7 Data Cache Address Register DC_ADR Table 7 8 Data Cache Address Register DC_ADR Bits Name Description 0 31 ADR Data cache command address When programming the DC_CST load and lock cache block unlock cache block and flush cache block commands DC_ADR contains the physical addr...

Page 226: ...al A write to DC_DAT results in an undefined data cache state For tag array DC_ADR 18 0 read commands the tag and state information is placed in the target general purpose register Figure 7 11 provides the format of the DC_DAT register for a tag read The last copyback address or data buffer can be read by using the copyback buffer read command DC_ADR 18 1 The copyback buffer select field DC_ADR 20...

Page 227: ...s as if all accesses have caching inhibited access attributes that is all accesses are propagated to the bus as single beat transactions Disabling the data cache does not affect the data address translation logic MSR DR controls data address translation Note that the data cache is disabled at hard reset Also the data cache is automatically disabled when a type 1 data cache error see Table 7 7 for ...

Page 228: ...k 1 Write the address of the cache block to be unlocked to the DC_ADR register 2 Write the unlock cache block command DC_CST CMD 0b1000 to the DC_CST register If the block is found in the cache hit it is unlocked and thereafter operates as a regular valid cache block If the block is not found in the cache miss no operation is performed There are no error cases for the unlock block command The data...

Page 229: ...nd there is no concern for architectural compliance using the DC_CST flush cache block command is more efficient 7 4 Cache Control Instructions The PowerPC architecture defines instructions for controlling both the instruction and data caches The cache control instructions icbi dcbt dcbtst dcbz dcbst dcbf and dcbi are intended for the management of the local caches In the following descriptions th...

Page 230: ...lid If the block containing the byte addressed by the EA is not in the data cache and the corresponding page is caching allowed the block is established in the data cache without fetching the block from main memory and all bytes of the block are cleared and the tag is marked as modified valid The dcbz instruction executes regardless of whether the cache block is locked but if the cache is disabled...

Page 231: ... treated as a store with respect to address translation and memory protection If the address hits in the cache the cache block is placed in the invalid state regardless of whether the data is modified If the address misses in the cache no action is taken Because this instruction may effectively destroy modified data it is privileged that is dcbi is available only to programs at the supervisor priv...

Page 232: ...without activating the instruction cache array The MPC885 instruction cache includes the following operational features Instruction fetch latency is reduced by sending the requested instruction address to the instruction cache and internal bus simultaneously A cache hit aborts the internal bus transaction before the MPC885 can initiate an external fetch The instruction cache supports stream hits a...

Page 233: ...tten into the burst buffer and delivered to the instruction sequencer either directly from the internal bus or from the burst buffer a stream hit A cache block in the array is then selected to receive the cache block being gathered in the burst buffer The selection algorithm gives first priority to invalid blocks If all blocks in the set are marked invalid the block in way 0 is selected If none of...

Page 234: ...o considered a programming error to perform load and lock cache block operations from zero wait state devices that are located on the internal bus The MPC885 considers these devices as caching inhibited memory regions If a load and lock cache block operation is performed from such a device the instruction is not guaranteed to be fetched from the instruction cache in most cases the instruction is f...

Page 235: ... to have memory coherency not required attributes Therefore software must maintain data cache coherency The MPC885 does not provide support for snooping external bus activity All coherency between the internal caches and external agents memory or I O devices must be controlled by software In addition there is no mechanism provided for DMA or other internal masters to access the data cache directly...

Page 236: ...ading subsequent words in the cache block the cache block is marked invalid After the cache block with the requested data has been loaded from memory the modified valid cache block in the copyback buffer is sent to the SIU to be written to memory If a bus error is encountered during the copyback a machine check exception is generated the copyback error is an imprecise exception The address and dat...

Page 237: ...id it is temporarily stored in the copyback buffer to be written to memory later Locked cache blocks are never replaced After a cache block has been selected the word aligned physical address of the store data is sent to the SIU with a 4 word burst transfer read request The SIU arbitrates for the bus and initiates a burst read The transfer begins with the aligned word containing the requested data...

Page 238: ...ter 8 Instruction Set in the Programming Environments Manual The lwarx instruction performs a load word from memory operation and creates a reservation for the 16 byte section of memory that contains the accessed word The reservation granularity is 16 bytes The lwarx instruction makes a nonspecific reservation with respect to the executing processor and a specific reservation with respect to other...

Page 239: ...nvestigate the exact state of the cache before the event that caused the reset To ensure proper operation after reset initialize the instruction cache by performing the following 1 Write the unlock all command IC_CST CMD 0b101 to the IC_CST register 2 Write the invalidate all command IC_CST CMD 0b110 to the IC_CST register 3 Write the cache enable command IC_CST CMD 0b001 to the IC_CST register Si...

Page 240: ...he cache To load the debug routine into the instruction cache before entering debug mode perform the following procedure 1 Save all four ways of the sets that are needed for the debug routine by reading the tag the LRU valid and lock bit states 2 Unlock the locked ways in the selected sets 3 Use the load and lock cache block command to load the debug routine into the instruction cache and lock the...

Page 241: ... 2 Freescale Semiconductor 7 29 cache and memory but the LRU bits in the data cache array are not updated For the dcbst dcbf dcbi instructions the data cache and memory are updated according to the PowerPC architecture but the LRU bits in the data cache array are not updated ...

Page 242: ...Instruction and Data Caches MPC885 PowerQUICC Family Reference Manual Rev 2 7 30 Freescale Semiconductor ...

Page 243: ...ble overrides to page protection settings 8 1 Features The following is a list of the MMU s important features Multiple page sizes 4 16 512 Kbyte or 8 Mbyte pages optional 1 Kbyte subpage protection granularity for 4 Kbyte pages with the following page attributes Changed bit support through the DTLB error exception on a write attempt to a unmodified page data MMU only Write through attribute for d...

Page 244: ...bled Additional registers and exceptions for handling table walks in software Note that although the MPC885 does not define segment registers as they are defined by the OEA the concept of segment is retained as the memory space accessible to the level one table descriptors 8 3 Address Translation The core generates 32 bit effective addresses EA for memory accesses Setting MSR IR and MSR DR enables...

Page 245: ...tion Enabled Translations are generated on a per page basis and are stored in tables in memory Along with the translation each table entry holds attributes for that page for example whether a location is cacheable Recently used translations are kept in translation lookaside buffers TLBs in hardware In the MPC885 software handles the table lookup and TLB reload with little hardware assistance This ...

Page 246: ...s the DMMU does not implement a fast TLB mechanism The DTLB is accessed for each transfer simultaneously with the data cache tag read hence there is no time penalty Data Instruction Fetch Same Page Fast TLB Hit TLB Hit TLB reload read page description from external memory to TLB Use current page description Yes No Yes No 32 bit EA is generated Compare address with TLB entries Is page valid Yes No ...

Page 247: ...d bits is a programming error Subpage validity flags can be manipulated to implement 1 4 Kbyte pages or any other combination of 1 Kbyte subpages However all subpages of an effective page frame must map to the same physical page During translation the EA the privilege level MSR PR and CASID are provided to the TLB as shown in Figure 8 3 In the TLB the EA and CASID are compared with each entry s EP...

Page 248: ...x_AP contains 16 fields The field content is used according to the group protection mode To be consistent with the PowerPC OEA the APG value should match the four msbs of the effective page number To override protection using APG use it on blocks of addresses which are defined by the 4 msbs of the effective page number If APG is not to be used for a particular block set the GP for that block to cl...

Page 249: ...ts 20 27 must all be programmed to the same protection attributes which are applied to the full page This mode is just as efficient in memory size as mode 1 but has the memory protection resolution of mode 3 Mode 3 Protection resolution to 1 Kbyte minimum subpage size with no restriction on subpage mapping In this mode program MD_CTR TWAM 0 Mx_CTR PPM 0 Mx_CTR PPCS 0 For pages larger than 4 Kbyte ...

Page 250: ...generate an exception for an R reference bit update In fact there is no entry for an R bit in the TLB The change bit C is bit 23 in the level two descriptor described in Table 8 4 Software updates C changed bits but hardware treats the C bit negated as a write protect attribute Therefore attempting to write to a page marked unmodified invalidates that entry and causes an implementation specific DT...

Page 251: ...l Two Table MD_CTR TWAM 0 MD_CTR TWAM 1 MD_CTR TWAM 0 MD_CTR TWAM 1 1 Kbyte 1 1 4 Kbytes 1 1 4 1 16 Kbytes 1 1 16 4 512 Kbytes 1 1 1 1 8 Mbytes 8 2 1 1 Level 1 Table Base Level 1 Index 00 Level 1 Index 0 19 20 31 9 10 Level 2 Index Page Offset 0 19 Level 1 Table Pointer M_TWB Level 1 Descriptor 0 Level 1 Descriptor 1 Level 1 Descriptor N Level 1 Descriptor 1023 Level 2 Table Base Level 2 Index 20 ...

Page 252: ... descriptor the page size determines the number of replaced bits as shown in Table 8 2 The remaining physical address bits come directly from the effective address When MD_CTR TWAM 0 the tablewalk begins at the level one base address placed in M_TWB The level one table is indexed by EA 0 11 to get the level one page descriptor As shown in Table 8 1 8 Mbyte pages must have eight identical entries i...

Page 253: ...s 8 7 1 Level One Descriptor Table 8 3 describes the level one descriptor format supported by the hardware to minimize the software tablewalk routine Table 8 2 Number of Replaced EA Bits per Page Size Page Size Number of Replaced EA Bits 1 Kbyte 20 4 Kbyte 20 16 Kbyte 18 512 Kbyte 13 8 Mbyte 9 Table 8 3 Level One Segment Descriptor Format Bits Name Description 0 19 L2BA Level 2 table base address ...

Page 254: ... access 1x Reserved Basic encoding 00 R W No access 01 R W R O 10 R W R W 11 R O R O 22 PP1 1 For pages larger than 4 Kbytes in mode 2 PP in bits 22 23 24 25 26 27 must equal the PP in bits 20 21 2nd subpage 0 Bits 20 21 contain Basic encoding 1 Bits 20 21 contain extended encoding 23 C Change bit for entry Set to 1 by default if change tracking functionality is not desired 0 Unchanged region writ...

Page 255: ...R 0 No similar restriction exists for tlbie and tlbia Table 8 6 lists the MPC885 specific MMU registers and indicates the sections that describe them These SPRs should be accessed when both instruction and data address translation is disabled Table 8 5 Page Size Selection Level 1 PS Level 2 SPS Page Size 00 0 4 Kbyte 00 1 16 Kbyte 01 0 Reserved 01 1 512 Kbyte 10 x Reserved 11 0 11 1 8 Mbyte Table ...

Page 256: ...r 794 Scratch Register M_TW MMU tablewalk special register 799 8 8 11 Debug Registers MI_CAM IMMU CAM entry read register 816 8 8 12 1 MI_RAM0 IMMU RAM entry read register 0 817 8 8 12 2 MI_RAM1 IMMU RAM entry read register 1 818 8 8 12 3 MD_CAM DMMU CAM entry read register 824 8 8 12 4 MD_RAM0 DMMU RAM entry read register 0 825 8 8 12 5 MD_RAM1 DMMU RAM entry read register 1 826 8 8 13 0 1 2 3 4 ...

Page 257: ...ibit attribute when the IMMU is disabled MSR IR 0 0 Caching is allowed 1 Caching is inhibited 3 Reserved Ignored on write returns 0 on read 4 RSV4I Reserve four ITLB entries See Section 8 10 2 Locking TLB Entries 0 ITLB_INDX decremented modulo 32 1 ITLB_INDX decremented modulo 28 5 Reserved Ignored on write returns 0 on read 6 PPCS Privilege user state compare mode 0 Ignore user supervisor state d...

Page 258: ... WT default when the DMMU is disabled MSR DR 0 4 RSV4D Reserve four DTLB entries See Section 8 10 2 Locking TLB Entries 0 DTLB_INDX decremented modulo 32 1 DTLB_INDX decremented modulo 28 5 TWAM Tablewalk assist mode 0 1 Kbyte subpage hardware assist 1 4 Kbyte page hardware assist default 6 PPCS Privilege user state compare mode 0 Ignore user supervisor state during address compare 1 Account for u...

Page 259: ...ad 22 EV TLB entry valid bit 0 TLB entry is invalid 1 TLB entry is valid EV is set to 1 on each ITLB DTLB miss 23 27 Reserved Ignored on write returns 0 on read 28 31 ASID Address space ID of the ITLB DTLB entry to be compared with M_CASID CASID Loaded with M_CASID on a TLB miss 0 15 Field Reset 0000_0000_0000_0000 R W R W 16 22 23 26 27 28 29 30 31 Field APG G PS V Reset 0 0 R W R W R W R W R W R...

Page 260: ...o the TLB 28 29 PS Page size level one 00 Small 4 or 16 Kbyte See MI_RPN SPS Default for ITLB miss 01 512 Kbyte 10 Reserved 11 8 Mbyte 30 Reserved Ignored on write returns 0 on read 31 V Entry valid bit 0 Entry is not valid 1 Entry is valid Default value on ITLB miss 0 15 Field L2TB Reset R W R W 16 19 20 22 23 26 27 28 29 30 31 Field L2TB APG G PS WT V Reset R W R W SPR 797 Figure 8 10 DMMU Table...

Page 261: ... MD_EPN 10 19 when MD_CTR TWAM 1 Returns MD_EPN 12 21 when MD_CTR TWAM 0 23 26 APG Access protection group Up to 16 protection groups are supported Set to 0000 on a DTLB miss 27 G Guarded memory attribute of the entry 0 Nonguarded memory Cleared on DTLB miss 1 Guarded memory 28 29 PS Level one page size Cleared on a DTLB miss 00 Small 4 Kbyte or 16 Kbyte See MD_RPN 01 512 Kbyte 10 Reserved 11 8 Mb...

Page 262: ...utable No access 1x Reserved Reserved Basic Encoding Supervisor User 00 Executable No access 01 Executable Executable 1x Executable Executable 22 PP1 1 For pages larger than 4 Kbytes in mode 2 PP in bits 22 23 24 25 26 27 must equal the PP in bits 20 21 0 Bits 20 21 contain basic encoding 1 Bits 20 21 contain extended encoding 23 Reserved 24 25 MD_CTR PPCS 0 For 1 Kbyte pages in mode 3 set to the ...

Page 263: ...access 01 R W R O 10 R W R W 11 R O R O 22 PP1 0 Bits 20 21 contain basic encoding 1 Bits 20 21 contain extended encoding 23 Change bit for DTLB entry Set to 1 by default if change tracking functionality is not desired 0 Unchanged region Write access causes an IMMU exception Software should take an appropriate action before setting this bit 1 Changed region Write access is allowed to this page 24 ...

Page 264: ... for the entry 0 Caching is allowed 1 Caching is inhibited 31 V Entry valid indication 1 For pages larger than 4 Kbytes in mode 2 PP in bits 22 23 24 25 26 27 must equal the PP in bits 20 21 0 19 20 29 30 31 Field L1TB L1INDX Reset 00 R W R W SPR 796 Figure 8 13 MMU Tablewalk Base Register M_TWB Table 8 14 M_TWB Field Descriptions Bits Name Description 0 19 L1TB Tablewalk level one base value 20 2...

Page 265: ... returns 0 on read 28 31 CASID Current address space ID Compared with ASID field of a TLB entry to qualify a match 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8 GP9 GP10 GP11 GP12 GP13 GP14 GP15 Reset R W R W SPR 786 MI_AP 794 MD_AP Figure 8 15 MMU Access Protection Registers MI_AP MD_AP Table 8 16 MI_AP MD_AP Field ...

Page 266: ... entry read register MI_CAM When the content addressable memory of the MI_CAM register is read it contains the effective address and page sizes of an entry indexed by MI_CTR ITLB_INDX MI_CAM is updated only by writing to it Table 8 17 describes the MI_CAM fields 0 15 Field EPN Reset R W R 16 19 20 22 23 27 28 31 Field EPN PS ASID SH SPV Reset R W R W SPR 816 Figure 8 17 IMMU CAM Entry Read Registe...

Page 267: ... 01 is valid 30 0 Subpage 2 Address 20 21 10 is not valid 1 Subpage 2 Address 20 21 10 is valid 31 0 Subpage 3 Address 20 21 11 is not valid 1 Subpage 3 Address 20 21 11 is valid 0 15 Field RPN Reset R W R 16 19 20 22 23 24 27 28 31 Field RPN PS_B CI APG SFP Reset R W R SPR 817 Figure 8 18 IMMU RAM Entry Read Register 0 MI_RAM0 Table 8 18 MI_RAM0 Field Descriptions Bits Name Description 0 19 RPN R...

Page 268: ...tted 1 Subpage 2 Address 20 21 10 Supervisor fetch is permitted 31 0 Subpage 3 Address 20 21 11 Supervisor fetch is not permitted 1 Subpage 3 Address 20 21 11 Supervisor fetch is permitted 0 15 Field Reset 0 R W R 16 25 26 29 30 31 Field UFP PV G Reset 0 R W R SPR 818 Figure 8 19 IMMU RAM Entry Read Register 1 MI_RAM1 Table 8 19 MI_RAM1 Field Descriptions Bits Name Description 0 25 Reserved 26 UFP...

Page 269: ...uarded memory 1 Guarded memory 0 15 Field EPN Reset R W R W 16 19 20 23 24 26 27 28 31 Field EPN SPVF PS SH ASID Reset R W R W SPR 824 Figure 8 20 DMMU CAM Entry Read Register MD_CAM Table 8 20 MD_CAM Field Descriptions Bits Name Description 0 19 EPN Effective page number 20 SPVF Subpage validity flags 0 Subpage 0 address 20 21 00 is not valid 1 Subpage 0 address 20 21 00 is valid 21 0 Subpage 1 a...

Page 270: ...e DTLB entry matches the value in M_CASID 1 ASID comparison is disabled for the entry 28 31 ASID Address space ID of the DTLB entry to be compared with M_CASID CASID 0 15 Field RPN Reset R W R 16 19 20 22 23 26 27 28 29 30 31 Field RPN PS APGI G WT CI Reset R W R W SPR 825 Figure 8 21 DMMU RAM Entry Read Register 0 MD_RAM0 Table 8 21 MD_RAM0 Field Descriptions Bits Name Description 0 19 RPN Real p...

Page 271: ...ute for the entry 0 Caching is allowed 1 Caching is inhibited 30 31 Reserved 0 15 Field Reset 0 R W R 16 17 18 19 22 23 24 25 26 27 28 29 30 31 Field C EVF SA SAT URP0 UWP0 URP1 UWP1 URP2 UWP2 URP3 UWP3 Reset 0 R W R SPR 826 Figure 8 22 DMMU RAM Entry Read Register 1 MD_RAM1 Table 8 22 MD_RAM1 Field Descriptions Bits Name Description 0 16 Reserved 17 C Change bit for DTLB entry 0 Unchanged region ...

Page 272: ... 20 21 00 User read access is permitted 25 UWP0 User write permission page zero 0 Subpage 0 address 20 21 00 User write access is not permitted 1 Subpage 0 address 20 21 00 User write access is permitted 26 URP1 0 Subpage 1 address 20 21 01 User read access is not permitted 1 Subpage 1 address 20 21 01 User read access is permitted 27 UWP1 0 Subpage 1 address 20 21 01 User write access is not perm...

Page 273: ... addition to the architecture defined SPRG0 SPRG3 so miss code need not corrupt existing GPRs Table 8 23 MPC885 Specific MMU Exceptions Exception Cause ITLB miss MSR IR 1 and an attempt is made to fetch an instruction from a page whose EPN cannot be translated by the ITLB Tablewalk software is responsible for loading information for the missed page from the translation table See Section 8 10 1 1 T...

Page 274: ... and level 1 attributes mfspr R1 MD_TWC Load R1 with level 2 pointer while taking page size into account lwz R1 R1 Load level 2 page entry mtspr MD_RPN R1 Write TLB entry mfspr R1 M_TW Restore R1 rfi Figure 8 23 DTLB Reload Code Example itlb_swtw mtspr M_TW R1 Save R1 mfspr R1 SRR0 Load R1 with instruction miss EA the same data may be taken from MI_EPN mtspr MD_EPN R1 Save instruction miss EA in M...

Page 275: ... RSV4I MD_CTR RSV4D 3 Invalidate the EA of the reserved page by using tlbia or tlbie 4 Set MI_CTR ITLB_INDX MD_CTR DTLB_INDX to the appropriate value between 27 and 31 5 Load Mx_EPN with the effective page number the ASID of the reserved page and set EV 6 Run software tablewalk code to load the appropriate entry into the translation lookaside buffer See Section 8 10 1 1 Translation Reload Examples...

Page 276: ...SVD is set the reserved entries are not invalidated Software can explicitly invalidate one or more of these entries by setting MD_CTR DTLB_INDX or MI_CTR ITLB_INDX negating MD_EPN EV or MI_EPN EV and writing to the appropriate MD_RPN or MI_RPN The TLBs are not invalidated automatically on reset but are disabled However they must be invalidated under program control during initialization ...

Page 277: ...he miss Full completion queue CQ Branch instruction handling Branch prediction All examples assume an instruction cache hit 9 1 1 Data Cache Load with a Data Dependency Figure 9 1 shows a data cache load with zero wait states The sub instruction depends on the value loaded to r12 which causes a bubble in the instruction stream The example in Section 9 1 3 Private Writeback Bus Load has no such dep...

Page 278: ...endent on sub rather than on mulli Although the writeback of the mulli is delayed two clocks there is no bubble in the execution stream mulli r12 r4 3 sub r3 r15 3 addic r4 r3 1 Figure 9 3 Writeback Arbitration Timing Example 2 9 1 3 Private Writeback Bus Load In Figure 9 4 lwz and xor write back in the same clock since they use the writeback bus in two different ticks a tick 1 4 of a processor cl...

Page 279: ...letion Queue Figure 9 6 shows stalls due to a full CQ Here the CQ is full from executing sub addic and and It takes one more bubble from the load writeback to allow further issue while the CQ retires sub addic and and lwz r12 64 SP sub r5 r5 3 addic r4 r14 1 and r3 r4 r5 ori xor load lwz sub and xor cror ori sub and cror ori load sub lwz lwz lwz lwz sub lwz cror and and xor xor ori GCLK1 E Data Fe...

Page 280: ...d Issuing bl causes a bubble because it does no work lwz r12 64 SP sub r3 r12 3 addic r4 r14 1 bl func func mulli r5 r3 3 addi r4 3 r0 Figure 9 7 Branch Folding Timing xor xor lwz lwz sub and xor addic ori sub and addic xor lwz sub lwz lwz lwz lwz lwz sub lwz addic addic and and Bubble GCLK1 E Data Fetch Decode Read Execute Writeback L Address Drive L Data Cache Address Load Writeback E Address Bu...

Page 281: ...r5 1 blt cr0 while Figure 9 8 Branch Prediction Timing 9 2 Instruction Timing List Table 9 1 summarizes instruction execution timings in terms of latency and blockage of the appropriate execution unit A serializing instruction blocks all execution units Table 9 1 Instruction Execution Timing Instructions Latency Blockage Unit Serializing Branch b ba bl bla bc bca bcl bcla bclr bclrl bcctr bcctl Ta...

Page 282: ...llw mulhw mulhwu 2 1 27 IU No Integer compare cmpi cmp cmpli cmpl 1 IU No Integer logical andi andis ori oris xori xoris and or xor nand nor eqv andc orc extsb extsh cntlzw 1 IU No Integer rotate and shift rlwinm rlwnm rlwimi slw srw srawi sraw 1 IU No Integer load lbz lbzu lbzx lbzux lhz lhzu lhzx lhzux lha lhau lhax lhaux lwz lwzu lwzx lwzux lhbrx lwbrx 28 1 LSU No Integer store stb stbu stbx st...

Page 283: ...vision latency 7 Blockage of the multiply instruction is dependent on the next instruction If the next instruction is a divide the blockage is 2 clocks otherwise the blockage is 1 clock 8 Assumes nonspeculative aligned access on chip memory and available bus See Section 3 6 3 4 Nonspeculative Load Instructions Section 3 6 3 5 Unaligned Accesses and Section 9 2 1 Load Store Instruction Timing Table...

Page 284: ...and mfspr accesses to off core SPRs by using a special cycle on the internal bus See Section 4 1 3 1 Accessing SPRs If the access ends in a bus error a software emulation exception is taken All write operations to off core SPRs mtspr are previously synchronized In other words the instruction is not taken until all prior instructions terminate Figure 9 9 Bus Latency for String Instructions 0x00 00 ...

Page 285: ...ion such as technical specifications reference materials and detailed applications notes can be accessed through the world wide web at http www freescale com Conventions This chapter uses the following notational conventions Bold entries in figures and tables showing registers and parameter RAM should be initialized by the user mnemonics Instruction mnemonics are shown in lowercase bold italics It...

Page 286: ...uilt in self test CRC Cyclic redundancy check CTR Count register DABR Data address breakpoint register DAR Data address register DEC Decrementer register DMA Direct memory access DRAM Dynamic random access memory DTLB Data translation lookaside buffer EA Effective address GPR General purpose register IEEE Institute of Electrical and Electronics Engineers ITLB Instruction translation lookaside buff...

Page 287: ...Family Reference Manual Rev 2 Freescale Semiconductor III 3 SWT Software watchdog timer TB Time base register TLB Translation lookaside buffer Tx Transmit Table III 1 Acronyms and Abbreviated Terms continued Term Meaning ...

Page 288: ...MPC885 PowerQUICC Family Reference Manual Rev 2 III 4 Freescale Semiconductor ...

Page 289: ...ces to request and obtain system bus mastership Chapter 12 External Signals describes bus operation The memory controller module provides a glueless interface to many types of memory devices and peripherals it supports a maximum of eight memory banks each with its own device and timing attributes Memory control services are provided to both internal and external masters The MPC885 supports circuit...

Page 290: ... reset interrupt if the time out is reached This timer can be disabled or its time out period can be changed in SYPCR Once SYPCR is written it cannot be written again until a system reset Periodic interrupt timer PIT Generates periodic interrupts for use with a real time operating system RTOS or the application software The PIT is clocked by the PITCLK clock and can be disabled if it is not needed...

Page 291: ...ntrolled by the PCMCIA interface BDIP GPL_B5 RSV IRQ2 KR RETRY IRQ4 SPKROUT IRQ 3 6 FRZ IRQ6 Programmed in SIUMCR CS6 CE1_B CS7 CE2_B Address matching and bank valid bits When a transfer matches either memory controller bank 6 or any PCMCIA bank mapped to slot B CS6 CE1_B is asserted When a transfer matches either memory controller bank 7 or any PCMCIA bank mapped to slot B CS7 CE2_B is asserted W...

Page 292: ...hine GPCM UPMA or UPMB assigned to control the required slave GPL_A 2 3 GPL_B 2 3 CS 2 3 GPL_A 2 3 GPL_B 2 3 Dynamically active depending on the machine UPMA or UPMB assigned to control the required slave GPL_A 2 3 CS 2 3 Programmed in the SIUMCR ALE_B DSCK AT1 IP_B 0 1 IWP 0 1 VFLS 0 1 IP_B2 IOIS16_B AT2 IP_B3 IWP2 VF2 IP_B4 LWP0 VF0 IP_B5 LWP1 VF1 IP_B6 DSDI AT0 IP_B7 PTR AT3 TDI DSDI TCK DSCK T...

Page 293: ...y space In the MPC885 all 16 bits can be programmed Chapter 2 Memory Map describes the internal memory map Section 11 3 1 1 Hard Reset Configuration Word describes available and default initial values 16 23 PARTNUM Part number read only Mask programmed with a code corresponding to the part number of the MPC885 Intended to help factory test and user code that is sensitive to part refinements PARTNU...

Page 294: ...nfiguration The default is set by the hard reset configuration word See Section 11 3 1 1 Hard Reset Configuration Word for the description of these bits 11 12 DBPC Debug port pins configuration Determines the active pins for the development port The default is set by the hard reset configuration word See Section 11 3 1 1 Hard Reset Configuration Word for the description of these bits 13 Reserved s...

Page 295: ...iven on its dedicated pin WE1 BS_B1 IOWR is driven on its dedicated pin WE2 BS_B2 PCOE is driven on its dedicated pin WE3 BS_B3 PCWE is driven on its dedicated pin 1 Assertion of either BS_A0 WE0 BS_B0 or IORD is driven on BS_A0 and WE0 BS_B0 IORD Assertion of either BS_A1 WE1 BS_B1 or IOWR is driven on BS_A1 and WE1 BS_B1 IOWR Assertion of either BS_A2 WE2 BS_B2 or PCOE is driven on BS_A2 and WE2...

Page 296: ...lock resolution for the bus monitor maximum timeout is 2 040 clocks 24 BME Bus monitor enable Controls bus monitor operation during internal to external bus cycles 0 Disable the bus monitor 1 Enable the bus monitor Note If the bus monitor is disabled transfer error conditions do not cause TEA to be asserted 25 27 Reserved should be cleared 28 SWF Software watchdog freeze 0 The software watchdog ti...

Page 297: ...ription 0 17 Reserved should be cleared 18 IEXT Instruction external transfer error acknowledge Set if the cycle is terminated by an externally generated TEA when an instruction fetch is initiated 19 ITMT Instruction transfer monitor timeout Set if the cycle is terminated by a bus monitor timeout when an instruction fetch is initiated 20 25 Reserved should be cleared 26 DEXT Data external transfer...

Page 298: ... exception and will not change the value in the register One exception to this is the timebase register TBU and TBL locked with TBK A write to the timebase register when it is locked results in a software emulation exception Reads are allowed at all times to any of the SIU registers regardless of whether they are locked or unlocked 0x308 TBREFBK Timebase reference register B key 32 bits 0x30C TBK ...

Page 299: ...nal bus arbitration logic external master support and pin multiplexing See Section 10 4 2 SIU Module Configuration Register SIUMCR 10 5 1 Interrupt Structure The SIU receives interrupts from internal sources like the PIT communications processor module CPM and the external IRQ pins Figure 10 7 shows the MPC885 interrupt structure Open Locked Power on reset Write 0x55CC_AA33 to the key register Wri...

Page 300: ...Chapter 35 CPM Interrupt Controller Section 10 5 3 1 Nonmaskable Interrupts IRQ0 and SWT describes how IRQ0 operates differently from other IRQ signals and how the operation is configurable through SIU registers 10 5 2 Priority of Interrupt Sources There are seven external IRQ pins IRQ0 is essentially nonmaskable although in a limited sense it can be masked as shown in Table 10 8 and IRQ5 is not a...

Page 301: ...SIVEC INTC 0 Highest IRQ0 0000_0000 1 Internal Level 0 0000_0100 2 IRQ1 0000_1000 3 Internal Level 1 0000_1100 4 IRQ2 0001_0000 5 Internal Level 2 0001_0100 6 IRQ3 0001_1000 7 Internal Level 3 0001_1100 8 IRQ4 0010_0000 9 Internal Level 4 0010_0100 10 0010_1000 11 Internal Level 5 0010_1100 12 IRQ6 0011_0000 13 Internal Level 6 0011_0100 14 IRQ7 0011_1000 15 Lowest Internal Level 7 0011_1100 16 31...

Page 302: ...ion about recoverability of NMI see Section 6 1 5 Recoverability After an Exception 10 5 4 Programming the SIU Interrupt Controller The SIU s interrupt controller includes the SIU interrupt pending register SIPEND SIU interrupt mask register SIMASK SIU interrupt edge level register SIEL and SIU interrupt vector register SIVEC registers These are described in the following sections Table 10 8 IRQ0 ...

Page 303: ...e an LVL bit If an IRQ pin is defined as an edge interrupt SIEL EDn 1 the corresponding bit being set indicates that a falling edge was detected on the line and are reset by writing ones to them Note that IRQ0 can be masked in only a very limited sense If SIEL ED0 1 edge sensitive and SIPEND IRQ0 is not cleared in the interrupt service routine further assertions of IRQ0 are masked 0 1 2 3 4 5 6 7 ...

Page 304: ...being serviced 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field IRM0 LVM0 IRM1 LVM1 IRM2 LVM2 IRM3 LVM3 IRM4 LVM4 LVM5 IRM6 LVM6 IRM7 LVM7 Reset 0000_0000_0000_0000 R W R W Addr IMMR 0xFFFF0000 0x014 16 31 Field Reset xxxx_xxxx_xxxx_xxxx R W R W Addr IMMR 0xFFFF0000 0x016 Figure 10 11 SIU Interrupt Mask Register SIMASK Table 10 10 SIMASK Field Descriptions Bits Name Description 0 IRM0 Interrupt request...

Page 305: ...his register is affected by HRESET and SRESET 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field ED0 ED1 ED2 ED3 ED4 ED6 ED7 Reset 0000_0000_0000_0000 R W R W Addr IMMR 0xFFFF0000 0x018 16 31 Field Reset xxxx_xxxx_xxxx_xxxx R W R W Addr IMMR 0xFFFF0000 0x01A Figure 10 12 SIU Interrupt Edge Level Register SIEL Table 10 11 SIEL Field Descriptions Bits Name Description 0 2 4 6 8 12 14 EDn Edge detect 0 7 0 ...

Page 306: ...hich allows indexing into the table When read as a half word each entry can contain a full routine of up to 256 instructions see Figure 10 14 and Table 10 7 0 7 8 15 Field INTC Reset xx11_11xx_xxxx_xxxx R W R Addr IMMR 0xFFFF0000 0x01C 16 31 Field Reset xxxx_xxxx_xxxx_xxxx R W R Addr IMMR 0xFFFF0000 0x01E Figure 10 13 SIU Interrupt Vector Register SIVEC Table 10 12 SIVEC Field Descriptions Bits Na...

Page 307: ...ithin a reasonable time The MPC885 s bus monitor does not monitor accesses initiated by external masters At the start of the transfer start signal TS the monitor begins counting and stops when transfer acknowledge TA retry RETRY or transfer error TEA is asserted For burst cycles this action is also performed between subsequent TA assertions for each data beat If the monitor times out the bus monit...

Page 308: ...h the writes must occur in the correct order before a timeout occurs any number of instructions may be executed between the writes This allows interrupts and exceptions to occur between the two writes when necessary See Figure 10 15 Figure 10 15 Software Watchdog Timer Service State Diagram The decrementer begins counting when it is loaded with a value from the SWTC field This value is then loaded...

Page 309: ...this register The SWSR can be written at any time but returns all zeros when read This register is affected by HRESET and SRESET Table 10 13 describes SWSR fields 0 15 Field SEQ Reset 0000_0000_0000_0000 R W W Addr IMMR 0xFFFF0000 0x00E Figure 10 17 Software Service Register SWSR Table 10 13 SWSR Field Descriptions Bits Name Description 0 15 SEQ Sequence This field is the pattern that is used to c...

Page 310: ...equest was made only one interrupt is reported Explicitly changing DEC 0 from 0 to 1 in software signals an interrupt request A decrementer exception causes a pending interrupt request in the core which is cleared automatically when the decrementer interrupt is taken Table 10 14 shows some decrementer periods available assuming a 4 MHz oscillator 10 8 1 Decrementer Register DEC The decrementer reg...

Page 311: ...9 1 Timebase Register TBU and TBL The timebase register TB holds a 64 bit integer that is incremented periodically It is implemented in two parts time base upper and time base lower TBU and TBL There is no automatic initialization of TB therefore system software must perform this initialization The contents of TB can be written by mtspr and read by mftb or mftbu instruction Figure 10 19 shows TBU ...

Page 312: ... by SRESET Table 10 18 describes TBREFA TBREFB fields 0 31 Field TBL Reset R W R W SPR 268 Read 284 Write Figure 10 20 Timebase Lower Register TBL Table 10 17 TBL Field Descriptions Bits Name Description 0 31 TBL Timebase lower The value in this field is used as the lower part of the timebase register 0 15 Field TBREFA TBREFB Reset R W R W Addr TBREFA IMMR 0xFFFF0000 0x204 TBREFB IMMR 0xFFFF0000 0...

Page 313: ...ed the divider is reset and the counter starts counting If the PS bit is set an interrupt is generated at the interrupt controller that remains pending until PS is cleared If PS is set again before being cleared the interrupt remains pending until PS is cleared Any write to PITC stops the current countdown 0 7 8 9 10 11 12 13 14 15 Field TBIRQ REFA REFB REFAE REFBE TBF TBE Reset 0000_0000_0000_000...

Page 314: ...ter It must be unlocked in PISCRK before it can be written This register is affected by HRESET but is not affected by SRESET Table 10 20 describes PISCR fields 0 7 8 9 12 13 14 15 Field PIRQ PS PIE PITF PTE Reset 0000_0000_0000_0000 R W R W Addr IMMR 0xFFFF0000 0x240 Figure 10 24 Periodic Interrupt Status and Control Register PISCR Table 10 20 PISCR Field Descriptions Bits Name Description 0 7 PIR...

Page 315: ...Enables the PS bit to generate an interrupt 14 PITF PIT freeze enable 0 The PIT is unaffected by the FRZ signal 1 The FRZ signal stops the PIT 15 PTE Periodic timer enable 0 The PIT is disabled 1 The PIT is enabled 0 15 Field PITC Reset R W R W Addr IMMR 0xFFFF0000 0x244 Bit 16 31 Field Reset 0000_0000_0000_0000 R W R W Addr IMMR 0xFFFF0000 0x246 Figure 10 25 PIT Count Register PITC Table 10 21 PI...

Page 316: ...re monitor debugger as described in Section 53 4 1 Freeze Indication When the FRZ signal is asserted the clocks to the software watchdog PIT timebase counter and decrementer can be disabled This is controlled by the associated bits in the control register of each timer If they are programmed to stop counting when FRZ is asserted the counters maintain their values until FRZ is negated The bus monit...

Page 317: ...of the MPC885 11 1 Types of Reset The MPC885 has several sources of input to the reset logic Power on reset External hard reset Internal hard reset Software watchdog reset Checkstop reset Debug port hard reset JTAG reset Table 11 1 MPC885 Reset Responses Reset Source Reset Effect Reset Logic and PLL States Reset System Configuration1 Reset 1 Includes SIU pin configuration the parallel I O configur...

Page 318: ...riving both HRESET and SRESET for 512 clock cycles After 512 cycles elapse the MPC885 s configuration is sampled from the data signals and the core stops internally asserting both HRESET and SRESET To ensure prompt negation external pull up resistors should be provided to drive HRESET and SRESET high After HRESET and SRESET are internally negated a 16 cycle period passes before the presence of an ...

Page 319: ...ft reset request from a development tool an internal hard or soft reset sequence is generated The development tool must reconfigure the debug port following a reset event See Section 53 3 2 1 2 Development Serial Data In DSDI 11 1 5 JTAG Reset When the JTAG logic asserts the JTAG reset signal an internal soft reset sequence is generated 11 1 6 Power On and Hard Reset Sequence Figure 11 1 shows the...

Page 320: ...ation is sampled from the DSDI and DSCK signals Once the core negates SRESET 16 clock cycles must elapse before the external soft reset signal is sampled 11 1 9 Soft Reset Sequence Figure 11 2 shows the reset sequence following an internal or external soft reset event Figure 11 2 Soft Reset Sequence 11 2 Reset Status Register RSR The 32 bit reset status register RSR is memory mapped into the MPC88...

Page 321: ...set event occurred 1 An external soft reset event occurred 2 Reserved 3 SWRS Software watchdog reset status Cleared by a power on reset When a software watchdog expire event occurs SWRS is set and remains set until software clears it 0 No software watchdog reset event occurred 1 A software watchdog reset event occurred 4 CSRS Check stop reset status Cleared by a power on reset When the core enters...

Page 322: ...ng time the configuration is sampled from the data bus If the RSTCONF signal is negated the internal default value is selected While HRESET and RSTCONF are asserted the MPC885 weakly pulls the data bus low and the desired configuration is selected by driving the appropriate bits high as shown in Figure 11 4 Figure 11 4 shows a typical data bus configuration input circuit Figure 11 4 Data Bus Confi...

Page 323: ...he maximum rise time of HRESET should be less than six clock cycles Refer to Section 11 3 2 Soft Reset for more information Figure 11 5 shows a reset operation with a short PORESET signal assertion Note that the configuration of the MPC885 is determined from the signal levels driven on the D 0 31 signals following the assertion of RSTCONF and the negation of HRESET Figure 11 5 Reset Configuration ...

Page 324: ...to the internal pull down resistor on the data bus Figure 11 8 Hard Reset Configuration Word Table 11 3 Hard Reset Configuration Word Field Descriptions Bits Name Description 0 EARB External arbitration If this bit is set external arbitration is assumed if cleared internal arbitration is performed See Section 10 4 2 SIU Module Configuration Register SIUMCR 1 IIP Initial interrupt prefix Defines th...

Page 325: ...ize 11 Reserved 6 Reserved for future use and should be allowed to float 7 8 ISB Initial internal space base select Defines the initial value of the IMMR bits 0 15 and determines the base address of the internal memory space 00 0x00000000 01 0x00F00000 10 0xFF000000 11 0xFFF00000 9 10 DBGC Debug pin configuration Selects the signal function of the following pins Pin DBGC 00 DBGC 01 DBGC 10 DBGC 11...

Page 326: ...K AT1 Defined by DBGC Note that if DBPC 11 DBPC overrides DBGC Reserved DSCK IP_B6 DSDI AT0 DSDI OP3 MODCK2 DSDO DSDO IP_B7 PTR AT3 PTR TCK DSCK DSCK TCK TCK TDI DSDI DSDI TDI TDI TDO DSDO DSDO TDO TDO 13 14 EBDF External bus division factor Defines the frequency division factor between GCLK1 GCLK2 and GCLK1_50 GCLK2_50 CLKOUT is similar to GCLK2_50 GCLK2_50 and GCLK1_50 are used by the system int...

Page 327: ...rnal devices including the phase locked loop circuitry and frequency dividers that generate programmable clock timing for baud rate generators and timers Chapter 15 Memory Controller describes the memory controller which controlling a maximum of eight memory banks shared between a general purpose chip select machine GPCM and a pair of user programmable machines UPMs Chapter 16 PCMCIA Interface des...

Page 328: ...example MSR LE refers to the little endian mode enable bit in the machine state register x In certain contexts such as in a signal encoding or a bit field indicates a do not care n Indicates an undefined numerical value NOT logical operator AND logical operator OR logical operator Acronyms and Abbreviations Table IV 1 contains acronyms and abbreviations used in this document Note that the meanings...

Page 329: ...etwork JTAG Joint Test Action Group LIFO Last in first out LRU Least recently used LSB Least significant byte lsb Least significant bit LSU Load store unit MAC Multiply accumulate MMU Memory management unit MSB Most significant byte msb Most significant bit MSR Machine state register NMSI Nonmultiplexed serial interface OSI Open systems interconnection PCI Peripheral component interconnect PCMCIA ...

Page 330: ...PR Special purpose register SRAM Static random access memory TDM Time division multiplexed TLB Translation lookaside buffer TSA Time slot assigner Tx Transmit UART Universal asynchronous receiver transmitter UISA User instruction set architecture UPM User programmable machine USART Universal synchronous asynchronous receiver transmitter Table IV 1 Acronyms and Abbreviated Terms continued Term Mean...

Page 331: ...s descriptions of the MPC885 input and output signals showing multiplexing pin assignments and reset values 12 1 MPC885 MPC880 Signals The following sections describe the signals pin numbers and signal descriptions 12 1 1 MPC885 MPC880 Signals and Pin Numbers Figure 12 1 and Figure 12 2 show the MPC885 signals and pin numbers ...

Page 332: ...L1RSYNCA PD14 UTPB 2 L1TSYNCB PD13 UTPB 3 L1RSYNCB PD12 RXENB RxD3 PD11 TXENB TxD3 PD10 UTPCLK TxD4 PD9 MII MDC RMII MDC RxD4 PD8 UTPB 4 RTS3 PD7 UTPB 5 RTS4 PD6 UTPB 6 CLK8 L1TCKB PD5 UTPB 7 CLK4 PD4 SOC CLK7 TIN4 PD3 MPC885 125 1 N16 1 P17 1 W11 1 P16 1 W9 1 W17 1 T15 1 W15 1 V14 1 U13 1 W13 1 U4 1 W2 1 T4 1 U1 1 U3 1 V3 1 P18 1 T19 1 V19 1 U19 1 R17 1 V17 1 U16 1 W16 1 V15 1 U14 1 T13 1 V13 1 T...

Page 333: ... 0 31 BR BG BB FRZ IRQ6 IRQ 0 1 IRQ7 CS 0 5 B14 C14 A15 D14 C16 A16 CS6 CE1_B CS7 CE2_B WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A 0 3 GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A 2 3 GPL_B 2 3 CS 2 3 UPWAITA GPL_A4 UPWAITB GPL_B4 GPL_A5 PORESET RSTCONF HRESET SRESET XTAL CLKOUT EXTCLK TEXP ALE_A CE1_A CE2_A WAIT_A SOC_Split IP_A 0 1 UTPB_Split 0 1 IP_A2 IOIS16_A UTPB_Split2 ALE_B DS...

Page 334: ...when an external master starts a bus transaction RD WR Hi Z D13 Bidirectional three state Read Write Driven by a bus master to indicate the direction of the data transfer A logic one indicates a read from a slave device and a logic zero indicates a write to a slave device The MPC885 drives this signal when it is a bus master This signal is input when an external master initiates a transaction on t...

Page 335: ...I requires the use of an external pull up resistor RSV IRQ2 See Table 12 3 B10 Bidirectional three state Reservation The MPC885 outputs this three state signal with the address bus to indicate that the core initiated a transfer as a result of a stwcx or lwarx Interrupt Request 2 One of eight external inputs that can request by means of the internal interrupt controller a service routine from the c...

Page 336: ...ore IRQ0 Hi Z N4 Input Interrupt Request 0 One of eight external inputs that can request by means of the internal interrupt controller a service routine from the core IRQ1 Hi Z P3 Input Interrupt Request 1 One of eight external inputs that can request by means of the internal interrupt controller a service routine from the core IRQ7 Hi Z P4 Input Interrupt Request 7 One of eight external inputs th...

Page 337: ...WE2 BS_B2 PCOE High C17 Output Write Enable 2 Output asserted when the MPC885 starts a write access to an external slave controlled by the GPCM WE2 is asserted if D 16 23 contains valid data to be stored by the slave device Byte Select 2 on UPMB Output asserted under control of UPMB as programmed by the user In a read or write transfer BS_B2 is asserted only if D 16 23 contains valid data PCMCIA O...

Page 338: ... CS3 is independently defined for each signal in the SIU module configuration register SIUMCR UPWAITA GPL_A4 Hi Z B13 Bidirectional User Programmable Machine Wait A Input that is sampled as defined by the user when an access to an external slave is controlled by UPMA General Purpose Line 4 on UPMA Output reflecting the value specified in UPMA when an external transfer to a slave is controlled by U...

Page 339: ...nsfers when accesses to PCMCIA slot A are handled under the control of the PCMCIA interface CE2_A High C15 Output Card Enable 2 Slot A This output signal enables odd byte transfers when accesses to PCMCIA slot A are handled under the control of the PCMCIA interface WAIT_A SOC_Split Hi Z A2 Input Wait Slot A This input signal if asserted low causes a delay in the completion of a transaction on the ...

Page 340: ...s reflected in the PIPR and PSCR of the PCMCIA interface UTPB_Split 5 This input signal is used as Rx data in split bus mode only IP_A 6 UTPB_Split 6 Hi Z E2 Bidirectional Input Port A 6 This input signal is monitored by the MPC885 and its value is reflected in the PIPR and PSCR of the PCMCIA interface UTPB_Split 6 This input signal is used as Rx data in split bus mode only IP_A 7 UTPB_Split 7 Hi ...

Page 341: ...85 monitors this input its value and changes are reported in the PIPR and PSCR of the PCMCIA interface Instruction Watchpoint 2 This output reports the detection of an instruction watchpoint in the program flow executed by the core Visible Instruction Queue Flushes Status The MPC885 outputs VF2 with VF0 VF1 when instruction flow tracking is required VFn reports the number of instructions flushed f...

Page 342: ...t used for transactions initiated by external masters OP 0 UtpClk_Split Low B6 Output Output Port 0 This output signal is generated by the MPC885 as a result of a write to the PGCRA register in the PCMCIA interface UtpClk_Split This input output signal is used as the UTOPIA Rx clock in split bus mode only The direction of this I O pin in split UTOPIA mode is defined by UTOPIA mode register UTMODE ...

Page 343: ...nchronous external master initiates a transaction A synchronous external master initiates a single beat transaction The memory controller uses these signals to increment the address lines that connect to memory devices when a synchronous external or internal master starts a burst transfer AS Hi Z D7 Input Address Strobe Input driven by an external asynchronous master to indicate a valid address on...

Page 344: ...l interface TDMa TXD3 Transmit data output for SCC3 PA 7 CLK1 TIN1 L1RCLKA BRGO1 Hi Z V14 Bidirectional General Purpose I O Port A Bit 7 Bit 7 of the general purpose I O port A CLK1 One of eight clock inputs that can be used to clock SCCs and SMCs TIN1 Timer 1 external clock L1RCLKA Receive clock for the serial interface TDMa BRGO1 Output clock of BRG1 PA 6 CLK2 TOUT1 Hi Z U13 Bidirectional Genera...

Page 345: ... output PB 31 SPISEL MII1 TXCLK RMII1 REFCLK Hi Z V3 Bidirectional optional open drain General Purpose I O Port B Bit 31 Bit 31 of the general purpose I O port B SPISEL SPI slave select input MII1 TXCLK Media independent interface 1 transmit clock RMII1 REFCLK Reduced media independent interface 1 reference clock PB 30 SPICLK Hi Z P18 Bidirectional optional open drain General Purpose I O Port B Bi...

Page 346: ...thernet UTOPIA multi PHY transmit address line 2 only if in ESAR mode UTOPIA multi PHY receive address line 2 PB 22 SMSYN2 SDACK2 TXADDR3 RXADDR3 Hi Z V15 Bidirectional optional open drain General Purpose I O Port B Bit 22 Bit 22 of the general purpose I O port B SMSYN2 SMC2 external sync input SDACK2 SDMA acknowledge 2 output that is used as a peripheral interface signal for IDMA emulation UTOPIA...

Page 347: ...idirectional optional open drain General Purpose I O Port B Bit 16 Bit 16 of the general purpose I O port B L1RQa D channel request signal for serial interface TDMa L1ST4 One of four output strobes that can be generated by the serial interface RTS43 Request to send modem line for SCC4 PHREQ 0 Most significant bit of PHY request bus used in classic SAR MPHY mode only UTOPIA multi PHY receive addres...

Page 348: ...e I O port C USBRXN USB receive gated version of D TGATE1 Timer 1 timer 2 gate signal PC 9 CTS2 Hi Z T14 Bidirectional General Purpose I O Port C Bit 9 Bit 9 of the general purpose I O port C CTS2 Clear to send modem line for SCC2 PC 8 CD2 TGATE2 Hi Z W14 Bidirectional General Purpose I O Port C Bit 8 Bit 8 of the general purpose I O port C CD2 Carrier detect modem line for SCC2 TGATE2 Timer 3 tim...

Page 349: ... I O port D L1RSYNCB Input receive data sync signal to the TDM channel B UTPB 3 UTOPIA bus bit 3 input output signal PD 11 RXD3 RXENB Hi Z R2 Bidirectional General Purpose I O Port D Bit 11 Bit 11 of the general purpose I O port D RXD3 Receive data for serial channel 3 RXENB Receive enable output signal PD 10 TXD3 TXENB Hi Z T2 Bidirectional General Purpose I O Port D Bit 10 Bit 10 of the general ...

Page 350: ...it of UTPB CLK4 One of eight clock inputs that can be used to clock SCCs and SMCs PD 3 SOC CLK7 TIN4 Hi Z T9 Bidirectional General Purpose I O Port D Bit 3 Bit 3 of the general purpose I O port D SOC Start of cell input output signal CLK7 One of eight clock inputs that can be used to clock SCCs and SMCs TIN4 Timer 4 external clock input PE31 CLK8 L1TCLKB MII1 RXCLK Hi Z U9 Bidirectional optional o...

Page 351: ...SMSYN2 TXD4 MII2 RXCLK L1ST1 Hi Z V2 Bidirectional optional open drain General Purpose I O Port E Bit 23 SMSYN2 SMC2 external sync input TXD4 Transmit data for serial channel 4 MII2 RXCLK Media independent interface 2 receive clock L1ST1 One of four output strobes that can be generated by the serial interface PE22 TOUT2 MII2 RXD1 RMII2 RXD1 SDACK1 Hi Z V1 Bidirectional optional open drain General ...

Page 352: ...I2 TXCLK Media independent interface 1 transmit clock RMII2 REFCLK Reduced media independent interface 1 reference clock PE15 TGATE1 MII2 TXD1 RMII2 TXD1 Hi Z W6 Bidirectional General Purpose I O Port E Bit 15 TGATE1 Timer 1 timer 2 gate signal MII2 TXD1 Media independent interface 2 transmit data 1 RMII2 TXD1 Reduced media independent interface 2 transmit data 1 PE14 RXD3 MII2 TXD0 RMII2 TXD0 Hi ...

Page 353: ...erface 1 collision Power supply See Figure 12 1 Power VDDL Power supply of the internal logic VDDH Power supply of the I O buffers and certain parts of the clock control VDDSYN Power supply of the PLL circuitry GND Ground for circuits except for the PLL circuitry VSSSYN VSSSYN1 Ground for the PLL circuitry 1 Pulled low if RSTCONF pulled down 2 High until DPLL locked then oscillates 3 See Section 1...

Page 354: ... MDC RxD4 PD8 MPC875 58 1 P14 1 U16 1 R9 1 R12 1 R11 1 P11 1 P7 1 R5 1 N6 1 T4 1 P6 1 T5 1 T17 1 R17 1 R14 1 N13 1 N12 1 U13 1 T12 1 U12 1 T11 1 R15 1 U9 1 T15 1 P12 1 U11 1 T10 1 P10 1 T3 1 T14 1 T13 1 R13 1 U14 1 P13 1 C7 1 P9 1 R8 1 U7 1 R7 1 T6 1 T2 1 U8 1 U4 1 T9 1 U3 1 R6 1 M5 1 T7 1 U6 1 T8 L1TCLKB CLK8 MII RXCLK PE31 L1RXDB MII1 RXD2 PE30 MII2 CRS PE29 TOUT3 MII2 COL PE28 L1RQB MII2 RXER R...

Page 355: ...2 PCOE WE3 BS_B3 PCWE BS_A 0 3 GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A 2 3 GPL_B 2 3 CS 2 3 UPWAITA GPL_A4 UPWAITB GPL_B4 GPL_A5 PORESET RSTCONF HRESET SRESET XTAL CLKOUT EXTCLK TEXP ALE_A CE1_A CE2_A WAIT_A IP_A 0 1 IP_A2 IOIS16_A ALE_B DSCK IP_B 0 1 WP 0 1 VFLS 0 1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR30 REG BADDR 28 29 MPC875 E4 IP_A3 D2 IP_A4 E3 IP_A5 F4 IP_A6 C2 IP_A7 B6 OP0 C6 OP1 U10 1 MII1_CRS...

Page 356: ...is input when an external master starts a bus transaction RD WR Hi Z D13 Bidirectional three state Read Write Driven by a bus master to indicate the direction of the data transfer A logic one indicates a read from a slave device and a logic zero indicates a write to a slave device The MPC875 drives this signal when it is bus master Input when an external master initiates a transaction on the bus B...

Page 357: ...BI requires the use of an external pull up resistor RSV IRQ2 See Table 12 3 C9 Bidirectional three state Reservation The MPC875 outputs this three state signal with the address bus to indicate that the core initiated a transfer as a result of a stwcx or lwarx Interrupt Out 2 One of eight external inputs that can request by means of the internal interrupt controller a service routine from the core ...

Page 358: ...he core IRQ0 Hi Z M6 Input Interrupt Out 0 One of eight external inputs that can request by means of the internal interrupt controller a service routine from the core IRQ1 Hi Z P5 Input Interrupt Out 1 One of eight external inputs that can request by means of the internal interrupt controller a service routine from the core IRQ7 Hi Z N5 Input Interrupt Out 7 One of eight external inputs that can r...

Page 359: ...space WE2 BS_B2 PCOE High D16 Output Write Enable 2 Output asserted when the MPC875 starts a write access to an external slave controlled by the GPCM WE2 is asserted if D 16 23 contains valid data to be stored by the slave device Byte Select 2 on UPMB Output asserted under control of UPMB as programmed by the user In a read or write transfer BS_B2 is asserted only D 16 23 contains valid data PCMCI...

Page 360: ... CS2 and CS3 is independently defined for each signal in the SIU module configuration register SIUMCR UPWAITA GPL_A4 Hi Z D11 Bidirectional User Programmable Machine Wait A This input is sampled as defined by the user when an access to an external slave is controlled by UPMA General Purpose Line 4 on UPMA This output reflects the value specified in UPMA when an external transfer to a slave is cont...

Page 361: ...o PCMCIA slot A are handled under the control of the PCMCIA interface CE2_A High D14 Output Card Enable 2 Slot A This output signal enables odd byte transfers when accesses to PCMCIA slot A are handled under the control of the PCMCIA interface WAIT_A Hi Z D4 Input Wait Slot A This input signal if asserted low causes a delay in the completion of a transaction on the PCMCIA controlled Slot A IP_A0 H...

Page 362: ...1 These outputs report the detection of an instruction watchpoint in the program flow executed by the core Visible History Buffer Flushes Status The MPC875 outputs VFLS 0 1 when program instruction flow tracking is required They report the number of instructions flushed from the history buffer in the core OP0 Low B6 Output Output Port 0 This output signal is generated by the MPC875 as a result of ...

Page 363: ...ynchronous external master initiates a transaction A synchronous external master initiates a single beat transaction The memory controller uses these signals to increment the address lines that connect to memory devices when a synchronous external or internal master starts a burst transfer AS Hi Z C7 Input Address Strobe Input driven by an external asynchronous master to indicate a valid address o...

Page 364: ...ent interface 1 transmit data 1 RMII1 TXD1 Reduced media independent interface 1 transmit data 1 PA 3 MII1 RXER RMII1 RXER BRGO3 Hi Z R5 Bidirectional General Purpose I O Port A Bit 3 Bit 3 of the general purpose I O port A MII1 RXER Media independent interface 1 receive error RMII1 RXER Reduced media independent interface 1 receive error BRGO3 Output clock of BRG3 PA 2 MII1 RXDV RMII1 CRS_D V TXD...

Page 365: ...eneral Purpose I O Port B Bit 27 Bit 27 of the general purpose I O port B I2CSDA I2 C serial data pin Bidirectional should be configured as an open drain output BRGO1 BRG1 output clock PB 26 I2CSCL BRGO2 Hi Z N12 Bidirectional optional open drain General Purpose I O Port B Bit 26 Bit 26 of the general purpose I O port B I2CSCL I2C serial clock pin Bidirectional should be configured as an open drai...

Page 366: ...mer 2 gate signal PC 7 CTS4 L1TSYNCB USBTXP Hi Z T10 Bidirectional General Purpose I O Port C Bit 7 Bit 7 of the general purpose I O port C CTS4 Clear to send modem line for SCC4 L1TSYNCB Transmit sync input for serial interface TDMb USBTXP USB transmit PC 6 CD4 L1RSYNCB USBTXN Hi Z P10 Bidirectional General Purpose I O Port C Bit 6 Bit 6 of the general purpose I O port C CD4 Carrier detect modem ...

Page 367: ...es that can be generated by the serial interface PE24 SMRXD1 BRGO1 MII2 RXD2 Hi Z U8 Bidirectional optional open drain General Purpose I O Port E Bit 24 SMRXD1 SMC1 receive data input BRGO1 Output clock of BRG1 MII2 RXD2 Media independent interface 2 receive data 2 PE23 TXD4 MII2 RXCLK L1ST1 Hi Z U4 Bidirectional optional open drain General Purpose I O Port E Bit 23 TXD4 Transmit data for serial c...

Page 368: ...rface 1 transmit clock RMII2 REFCLK Reduced media independent interface 1 reference clock PE15 TGATE1 MII2 TXD1 RMII2 TXD1 Hi Z T7 Bidirectional General Purpose I O Port E Bit 15 TGATE1 Timer 1 timer 2 gate signal MII2 TXD1 Media independent interface 2 transmit data 1 RMII2 TXD1 Reduced media independent interface 2 transmit data 1 PE14 MII2 TXD0 RMII2 TXD0 Hi Z P8 Bidirectional General Purpose I...

Page 369: ...HRESET or PORESET is asserted these pins immediately begin functioning as the signals selected in the SIUMCR The behavior of these signals is shown in Table 12 3 MII1_COL Hi Z R10 Input MII1_COL Media independent interface 1 collision Power supply See Figure 12 3 Power VDDL Power supply for the internal logic VDDH Power supply for the I O buffers and certain parts of the clock control VDDSYN Power...

Page 370: ...gnals in periods when no drivers are active and to keep the buffer Table 12 3 Configuration Dependent Signal Behavior During Reset Signal Function Determined at Reset by Pin Signal Behavior SRESET HRESET or PORESET Previous programming of SIUMCR SIUMCR default values only BDIP GPL_B5 BDIP high impedance GPL_B5 high1 1 After a hard reset this signal function is actually inactive until the user sele...

Page 371: ...he access on the external bus throughout the entire bus cycle TA When the MPC885 memory controller responds to the access on the external bus For chip selects controlled by the GPCM set for external TA the TA buffer is not enabled as an output For chip selects controlled by the GPCM set to terminate in n wait states TA is enabled as an output on cycle n 1 and driven high then is driven low on cycl...

Page 372: ...ctions The following sections provide recommended pin connections 12 6 1 Reset Configuration Some external pin configurations are determined at reset by the hard reset configuration word Thus some decisions regarding system configuration for example location of BDM pins should be made before required application of pull up and pull down resistors can be determined RSTCONF should be grounded if the...

Page 373: ...uration See also Section 11 4 TRST Considerations TCK DSCK or ALE_B DSCK AT1 depending on the configuration of the DSCK function should be connected to ground through a pull down resistor to disable debug mode as a default When required an external debug mode controller can actively drive this signal high to put the processor into debug mode The two signals TCK DSCK and TDI DSDI have special requi...

Page 374: ...nce Memory controller signals are driven to their inactive state Refresh stops For the behavior of specific signals during a hard reset see Section 12 1 2 MPC885 MPC880 System Bus Signals SRESET The current bus cycle aborts Bus signals revert to their inactive state For example BR or BG negate and address and data signals become high impedance Memory controller aborts the current access and signal...

Page 375: ... of bus clock 13 2 Bus Transfer Overview The bus transfers information between the MPC885 and external memory or a peripheral device External devices can accept or provide 8 16 and 32 bits in parallel and must follow the handshake protocol described in this section The maximum number of bits accepted or provided during a bus transfer is defined as port width The MPC885 s address bus specifies the ...

Page 376: ...r in addition to meeting input setup and hold times Figure 13 1 Input Sample Window TSIZ0 and TSIZ1 indicate the number of bytes remaining to be transferred during an operand cycle consisting of one or more bus cycles and are driven with the address type signals at the beginning of a bus cycle These signals are valid at the rising edge of the clock in which the transfer start signal TS is asserted...

Page 377: ... MPC885 when an external device initiates a transaction and the memory controller was configured to handle external master accesses RD WR Read Write 1 O Driven by the MPC885 along with the address when it owns the external bus Driven high indicates that a read access is in progress Driven low indicates that a write access is in progress I Sampled by the MPC885 when an external device initiates a t...

Page 378: ...g with the address when it owns the external bus Indicates additional information about the address on the current transaction BDIP Burst Data in Progress 1 O Driven by the MPC885 when it owns the external bus as part of the burst protocol Asserted indicates that the second beat in front of the current one is requested by the master Negated before the burst transfer ends to abort the burst data ph...

Page 379: ...n chip memory controller or PCMCIA interface TEA Transfer Error Acknowledge 1 I Driven by the slave device to which the current transaction is addressed Indicates that an error condition occurred during the bus cycle O Driven by the MPC885 when the internal bus monitor detects a bus error BI Burst Inhibit 1 I Driven by the slave device to which the current transaction was addressed Indicates that ...

Page 380: ...device requests bus access Address phase The address and the transfer attributes are generated Data phase Any data to be transferred is transferred The data phase may transfer a single beat of data 4 bytes or less for nonburst operations a 4 beat data burst 4 4 bytes an 8 beat data burst 8 2 bytes or a 16 beat data burst 16 1 bytes Termination The transfer completes successfully or it was aborted ...

Page 381: ...e basic read cycle begins with a bus arbitration followed by the address transfer then the data transfer The following flow and timing diagrams show the handshakes applicable to the fixed transaction protocol Figure 13 4 maps the flow of a single beat read cycle Figure 13 4 Basic Flow Diagram of a Single Beat Read Cycle MASTER Receives Bus Grant BG from arbiter Asserts Bus Busy BB if no other mast...

Page 382: ...ductor Figure 13 5 shows the basic timing for a single beat read cycles with no wait states Figure 13 5 Basic Timing Single Beat Read Cycle Zero Wait States CLKOUT BR BG BB R W TSIZ 0 1 AT 0 3 BURST TS Data TA Assert BB drive address and assert TS Receive BG and BB negated Data is Valid A 0 31 ...

Page 383: ...Figure 13 6 demonstrates the basic timing of a single beat read cycle with one wait state Figure 13 6 Basic Timing Single Beat Read Cycle One Wait State CLKOUT BR BG BB R W TSIZ 0 1 AT 0 3 BURST TS Data TA Assert BB drive address and assert TS Receive BG and BB negated Data is Valid Wait State A 0 31 ...

Page 384: ...following flow and timing diagrams show the handshakes as applicable to the fixed transaction protocol Figure 13 7 maps the flow of a single beat write cycle Figure 13 7 Basic Flow of a Single Beat Write Cycle MASTER Bus Request BR Receives Bus Grant BG from arbiter Asserts Bus Busy BB if no other master is driving Asserts Transfer Start TS Drives address and attributes Asserts Transfer Acknowledg...

Page 385: ... timing chart in Figure 13 8 shows the basic timing of a single beat write cycle with no wait states Figure 13 8 Basic Timing Single Beat Write Cycle Zero Wait States CLKOUT BR BG BB R W TSIZ 0 1 AT 0 3 BURST TS Data TA Assert BB drive address and assert TS Receive BG and BB negated Data is sampled A 0 31 ...

Page 386: ... case of single beat transfers assumes that external memory has a 32 bit port size As demonstrated in Figure 13 10 the MPC885 provides an effective mechanism for interfacing with 16 and 8 bit port size memories by allowing transfers to these devices when they are controlled by the internal memory controller CLKOUT BR BG BB R W TSIZ 0 1 AT 0 3 BURST TS Data TA Assert BB drive address and assert TS ...

Page 387: ...QUICC Family Reference Manual Rev 2 Freescale Semiconductor 13 13 Figure 13 10 Basic Timing Single Beat 32 Bit Data Write Cycle 16 Bit Port Size CLKOUT BR BG BB R W TSIZ 0 1 BURST TS Data TA STS PS 10 ABCDEFGH EFGHEFGH 00 10 A A 2 A 0 31 ...

Page 388: ...rst transfers to these devices when they are controlled by the internal memory controller In this case the MPC885 attempts to initiate a burst transfer as in the normal case If in a cycle before the TA is asserted for the first beat the memory controller responds that the port size is 16 8 bits and that the burst is accepted the MPC885 completes a 8 16 beat burst Each data beat effectively transfe...

Page 389: ...he burst includes 4 beats When the port size is 16 bits and controlled by the internal memory controller the burst includes 8 beats When the port size is 8 bits and controlled by the internal memory controller the burst includes 16 beats The MPC885 bus supports critical data first access for fixed size burst The order of wraparound wraps back to the critical data For example assuming data 2 is cri...

Page 390: ...ss and attributes Asserts Transfer Acknowledge TA Receives data SLAVE Asserts Burst Data in Progress BDIP Drives BURST asserted Receives address Returns data Asserts Transfer Acknowledge TA Returns data BDIP asserted Receives data Asserts Transfer Acknowledge TA Returns data BDIP asserted Receives Data Asserts Transfer Acknowledge TA Returns data BDIP asserted Negates Burst Data in Progress BDIP Y...

Page 391: ...ual Rev 2 Freescale Semiconductor 13 17 Figure 13 12 Burst Read Cycle 32 Bit Port Size Zero Wait State Expects Another Data Last Beat CLKOUT BR BG BB R W TSIZ 0 1 BURST TS Data TA Data is BDIP PS 00 Valid Data is Valid Data is Valid Data is Valid 00 A 0 31 AT 0 3 ...

Page 392: ...ev 2 13 18 Freescale Semiconductor Figure 13 13 Burst Read Cycle 32 Bit Port Size One Wait State Expects Another Data Last Beat CLKOUT BR BG BB R W TSIZ 0 1 BURST TS Data TA Data is BDIP PS 00 Valid Data is Valid Data is Valid Data is Valid 00 Wait State A 0 31 AT 0 3 ...

Page 393: ...reescale Semiconductor 13 19 Figure 13 14 Burst Read Cycle 32 Bit Port Size Wait States between Beats Expects Another Data Last Beat CLKOUT BR BG BB R W TSIZ 0 1 BURST TS Data TA Data is BDIP PS 00 Valid Data is Valid Data is Valid Data is Valid 00 Wait State A 0 31 AT 0 3 ...

Page 394: ...scale Semiconductor Figure 13 15 Burst Read Cycle 16 Bit Port Size One Wait State between Beats The following flow Figure 13 16 and timing diagram Figure 13 17 show the handshakes for a burst write transaction CLKOUT BR BG BB R W TSIZ 0 1 BURST TS Data TA PS BDIP 00 10 A 0 31 AT 0 3 ...

Page 395: ...ves address and attributes Asserts Transfer Acknowledge TA Drives data SLAVE Asserts burst data in progress BDIP Drives BURST asserted Receives address Negates Burst Data in Progress BDIP Stops driving data Don t sample next data Don t sample next data Yes No Drives data BDIP asserted Asserts Transfer Acknowledge TA Drives data Don t sample next data Yes No BDIP asserted Asserts Transfer Acknowled...

Page 396: ...ve device that does not support bursting The slave acknowledges the first transfer and also asserts the burst inhibit signal BI The MPC885 responds by terminating the burst and accessing the rest of the 16 byte block using three single beat read cycles Will drive another data Last beat CLKOUT BR BG BB R W TSIZ 0 1 BURST TS Data TA Data is BDIP sampled Data is sampled Data is sampled Data is sample...

Page 397: ...lignment and Data Packing on Transfers The MPC885 external bus supports only natural address alignment Byte access can have any address alignment Half word access must have A 31 0b0 Word access must have A 30 31 0b00 For burst accesses A 30 31 0b00 CLKOUT BR BG BB A 28 29 A 30 31 R W TSIZ 0 1 TS BDIP Data BURST TA BI n n 1 Mod 4 n 2 Mod 4 n 3 Mod 4 00 A 0 27 ...

Page 398: ... maximum amount of data on all bus cycles for a word operation it always assumes that the port is 32 bits wide when beginning the cycle Figure 13 19 Figure 13 20 Table 13 2 and Table 13 3 use the following conventions OP0 is the MSB of a word operand OP3 is the LSB The two bytes of a half word operand are OP0 most significant and OP1 or OP2 most significant and OP3 depending on the address of the ...

Page 399: ...uest BR bus grant BG and bus busy BB signals A device needing the bus asserts BR and waits for the arbiter to assert BG The new master must look at BB to ensure that no other master is driving the bus before it can assert BB to assume bus mastership Note that the internal Table 13 2 Data Bus Requirements for Read Cycles Transfer Size TSIZ 0 1 Address 32 Bit Port1 1 Denotes a byte not required duri...

Page 400: ...The potential bus master asserts BR to request bus mastership BR should be negated as soon as the bus is granted the bus is not busy and the new master can drive the bus If requests are pending the master can assert BR as long as needed When configured for external arbitration the MPC885 drives BR when it requires bus mastership When the internal on chip arbiter is used BR is an input to the inter...

Page 401: ...bus New masters should not begin a transfer until BB is deasserted The bus master should not relinquish or negate BB until it completes its transfer To avoid contention on BB masters should three state BB when it gets a logical 1 value This situation implies an external pull up resistor is needed to ensure that a master that acquires the bus can recognize the negation of BB regardless of how many ...

Page 402: ...dule Configuration Register SIUMCR describes prioritization of external devices relative to the internal MPC885 bus masters If the external device requests the bus and the MPC885 does not require it or the external device has higher priority than the current internal bus master the MPC885 grants the bus to the external device Figure 13 24 shows the internal finite state machine that implements the...

Page 403: ...granted mastership TS is asserted only for the first cycle of the transaction and is negated in the successive clock cycles until the end of the transaction To avoid contention the master should three state this signal when it relinquishes the bus This situation indicates that an external pull up resistor should be connected to TS to avoid having a slave recognize this signal as asserted when no m...

Page 404: ...read cycle or vice versa It may remain low for consecutive write cycles 13 4 7 3 2 Burst Indicator BURST BURST is driven by the bus master at the beginning of the bus cycle along with the address to indicate that the transfer is a burst transfer 13 4 7 3 3 Transfer Size TSIZ TSIZ 0 1 indicates the size of the requested data transfer The TSIZ signals may be used with BURST and A 30 31 to determine ...

Page 405: ... and RSV Table 13 5 Address Types Definition STS TS Core CPM AT0 User Supervisor AT1 Instruction Data AT2 Reservation Program Trace AT3 Program Trace PTR Reservation RSV Address Space Definitions 1 x x x x x 1 1 No transfer or not the first transaction of a transfer 0 x x x x x x x Start of a transaction x 0 0 0 0 0 0 1 Core initiated normal instruction program trace supervisor mode 1 1 1 Core ini...

Page 406: ...e indications can also be monitored on two separate signals PTR and RSV if desired PTR is low when the following is true AT0 0 Core access AT2 0 Instruction AT3 0 Program Trace x 1 0 0 0 0 0 1 Core initiated show cycle address instruction program trace supervisor mode 1 1 1 Core initiated show cycle address instruction supervisor mode 1 0 1 0 Core initiated reservation show cycle data supervisor m...

Page 407: ...TEA Terminates the bus cycle under a bus error condition for which the current cycle is aborted TEA overrides other cycle termination signals such as TA Note that for burst transactions TEA should be asserted externally only on the first or last beats Assertion of TEA on an intermediate beat may result in erratic operation including lockup of the MPC885 requiring hard reset 13 4 8 4 Termination Si...

Page 408: ... 13 26 Termination Signals Protocol Timing Diagram Slave 1 Slave 2 External Bus Termination Signals TA TEA BI MPC885 CLKOUT R W TSIZ 0 1 TS Data TA BI TEA Slave 1 negates acknowledge signals and Slave 2 allowed to drive acknowledge signals Slave 1 allowed to drive acknowledge signals Slave 2 negates acknowledge signals and turns off turns off Slave 1 Slave 2 A 0 31 ...

Page 409: ...he reservation flag Store by the same processor does not clear the reservation flag Some other processor or other mechanism store to the same address as an existing reservation clears the reservation flag If memory reservation is lost it is guaranteed that stwcx will not modify the memory 13 4 9 1 Cancel Reservation CR CR is a point to point signal To use it reservation logic must remember specifi...

Page 410: ... masters has a reservation for a particular address If another bus master writes to the address with an instruction other than stwcx the reservation logic remembers that the reservation for that address was lost When the master with the reservation subsequently attempts an stwcx instruction to that address the reservation logic responds to that external bus cycle with KR Note that for burst transa...

Page 411: ...ed to the core 13 4 10 Bus Exception Control Cycles The MPC885 bus architecture requires assertion of the TA from an external device to signal that the bus cycle is complete TA is not asserted in the following cases the external device does not respond various other application dependent errors occur External circuitry or the internal MPC885 bus monitor can provide TEA when no device responds by a...

Page 412: ...the case of a write cycle Figure 13 29 shows that when the internal arbiter is enabled the MPC885 negates BB and asserts BG in the clock cycle after RETRY is detected to allow any external master to gain bus ownership Normal arbitration resumes in the next clock cycle If the external master does not use the bus the MPC885 initiates a new transfer with the same address and attributes as before Figu...

Page 413: ... the MPC885 is working with an external arbiter In this case in the clock cycle after RETRY is detected asserted BR and BB are negated together Normal arbitration resumes one clock cycle later Figure 13 30 Retry Transfer Timing External Arbiter CLKOUT BR Output BG BB R W TSIZ 0 1 BURST TS Data TA RETRY Allow external master to gain the bus A A A 0 31 ...

Page 414: ...n Burst Cycle If a burst access is acknowledged on its first beat with a normal TA but with BI asserted the following single beat transfers initiated by the MPC885 to complete the 16 byte transfers process the RETRY signal assertion as a TEA If the MPC885 initiates non burst access to a small port size device the transfer size of the access is bigger than the slave port size and the first transfer...

Page 415: ...summarizes how the MPC885 recognizes the termination signals provided by the slave device that is addressed by the initiated transfer Table 13 6 Termination Signals Protocol TEA TA RETRY KR Action 0 x x Transfer error termination 1 0 x Normal transfer termination 1 1 0 Retry transfer termination kill reservation ...

Page 416: ...External Bus Interface MPC885 PowerQUICC Family Reference Manual Rev 2 13 42 Freescale Semiconductor ...

Page 417: ...e a high frequency system clock from a low frequency external source Also to enable flexible power control the MPC885 provides frequency dividers options Figure 14 1 illustrates internal clock source and distribution that includes the digital phase locked loop DPLL and interface clock dividers drivers and crystal oscillator 14 1 Features The main features of the MPC885 clocks are as follows Contai...

Page 418: ...river Time Base and Driver CLKOUT Driver SCCR PTDIV MODCK 1 2 VDDSYN EXTCLK gclk gclk2 gclk1c gclk2c gclk1_50 gclk2_50 brgclk syncclk CLKOUT tmbclk pitclk SCCR PTSEL XTAL EXTAL jdbck osclk gclk2 SCCR TBS tbclk Note that only CLKOUT is an actual external output all other outputs are internal signals Decrementer utpclk DPLL Interface divide by 1 2 4 Logic dpgdck PLPRCR S PLPRCR PDF MFI MFN MFD divou...

Page 419: ...s for special system timer circuitry which includes the periodic interrupt timer PIT timebase TB and decrementer DEC in the SIU These separate clock sources for the PIT TB and DEC are provided to enable these modules to continue to count at a fixed user defined rate regardless of system frequency The clock sources for OSCLK PITCLK and TMBCLK are selected at reset The sources for PITCLK and TMBCLK ...

Page 420: ...0 MHz input frequency while the fourth mode can accept from 45 to 66 MHz After reset the PLPRCR can be programmed to achieve a different general system clock as long as the following requirements are met OSCM is 10 MHz only MODCK 00 or 01 EXTCLK is 10 MHz MODCK 11 EXTCLK is 45 MHz to 66 MHz MODCK 10 The Input Frequency Requirements at reset are shown in Table 14 1 14 2 2 Digital Phase Lock Loop an...

Page 421: ...described in Section 14 2 1 External Reference Clocks Inside the DPLL the OSCLK is divided by the predivision factor PDF 1 to generate DPDREF clock Frequency range of DPDREF is 10 to 32 Mhz This DPDREF clock is used further inside the DPLL for generating the output clock of the DPLL i e DPGDCK see Figure 14 1 Frequency range of DPGDCK is 160 to 320 Mhz These frequency ranges must be maintained by ...

Page 422: ... the sampled MODCK 1 2 pin and attempts to achieve lock therefore the MODCK 1 2 signals should be maintained steadily throughout PORESET assertion The mode selection field and various factors are set as shown in Table 14 3 After PORESET is negated the MODCK 1 2 values are internally latched and the signals applied to MODCK 1 2 can be changed Table 14 2 Typical System Frequency Generation Input Fre...

Page 423: ...capacitance variation due for example to layout and board composition Careful consideration must be given to component placement and layout keeping components as near as possible to the chip and keeping all trace lengths to a minimum It should be noted that the sensitivity of crystal circuits to external component values is so great that even probing the circuit changes its behavior to the point t...

Page 424: ...memory controller and provide the CLKOUT output for the external bus UTPCLK Clocks the Utopia Module BRGCLK Clocks the four baud rate generators and the memory controller refresh timer This allows the serial ports to operate at a fixed frequency and the memory refresh to continue at a uniform rate even when the rest of the MPC885 is operating at a reduced frequency SYNCCLK Used by the serial synch...

Page 425: ...ides the GCLK2_50 signal externally on the CLKOUT pin The DPLL and Interface output JDBCK is sent to frequency dividers that generate the GCLKx GCLKxC GCLKx_50 SYNCCLK and BRGCLK which are sent to the rest of the modules of the MPC885 The signal divout1 is an intermediate signal and is equivalent to JDBCK divide by 2 The division factor for each divider is programmed in the SCCR The organization o...

Page 426: ...s programmed in SCCR DFNH and SCCR DFNL as shown in Figure 14 5 Figure 14 5 Frequency Dividers for GCLKx The high frequency is generated by using the DFNH field in the SCCR and it is used in normal high mode The low frequency is generated using the DFNL field in the SCCR and it is used in normal low mode The DFNH and DFNL dividers are cleared by HRESET and therefore GCLKx defaults to divout1 where...

Page 427: ...s frequency dividers The external bus clocks GCLK1_50 and GCLK2_50 are derived from GCLK1 and GCLK2 as determined by the SCCR EBDF SCCR EBDF is cleared by HRESET and thus GCLK1_50 and GCLK2_50 default to GCLK1 and GCLK2 The timing relationship between GCLKx and GCLKx_50 is shown in Figure 14 7 Figure 14 7 Memory Controller and External Bus Clocks Timing Diagram for EBDF 0 and EBDF 1 GCLK1 Divided ...

Page 428: ...UT For an example of this see Figure 14 8 Figure 14 8 Memory Controller and External Bus Clocks Timing Diagram for CSRC 0 and DFNH 1 or CSRC 1 and DFNL 0 The frequency of GCLK1_50 and GCLK2_50 are affected both by the SCCR DFNH and SCCR DFNL dividers and by the SCCR EBDF divider Thus the frequency for GCLKx_50 and CLKOUT is CLKOUT is the only externally visible clock and is equivalent to the inter...

Page 429: ...en the total multiplication factor between EXTCLK and CLKOUT is maintained as an integer number 14 3 1 4 Baud Rate Generator Clock BRGCLK The baud rate generator clock BRGCLK is used by the four baud rate generators of the communication processor module and by the memory controller refresh counter The baud rate generator clock is controlled independently in order to allow the baud rate generators ...

Page 430: ... be at least 2 5 times the maximum serial clock rate of the TSA 14 3 2 PIT Clock PITCLK The PIT clock is generated either from EXTCLK or the crystal oscillator circuit OSCM This input source can be divided by either 4 or 512 The PITCLK source and divide factor are selected by SCCR PTSEL and SCCR PTDIV The MODCK 1 2 state at PORESET negation determines the input clock source and prescalar value for...

Page 431: ... for TMBCLK 14 4 Power Distribution The various modules of the MPC885 are connected to four distinct power rails These power rails have different requirements as explained in the following sections The organization of the power rails is shown in Figure 14 11 Figure 14 11 MPC885 Power Rails Table 14 6 TMBCLK Configuration SCCR TBS MODCK 1 2 at PORESET MF Clock Source TMBCLK Prescaler 1 XX X GCLK2 1...

Page 432: ...Power VDDH The I O buffers are fed by a 3 3 V power supply 14 4 2 Internal Logic Power VDDL The internal logic are to be fed by the 1 8 V source 14 4 3 Clock Synthesizer Power VDDSYN VSSSYN VSSSYN1 To improve stability the power supply pins for the DPLL are uniquely identified in order to allow special filtration to be provided for them A well regulated voltage should be applied to VDDSYN via a lo...

Page 433: ...are initiation CPM activity internal interrupt sources external interrupt sources and resets 14 5 1 Normal High Mode Normal high mode is the default mode of the MPC885 In this mode the GCLKx frequency is determined by SCCR DFNH and all modules of the MPC885 are enabled For more information about SCCR DFNH refer to Section 14 3 1 1 Internal General System Clocks GCLK1C GCLK2C GCLK1 GCLK2 Normal hig...

Page 434: ...and reset control register SCCR shown in Figure 14 12 which is memory mapped into the MPC885 SIU s register map 0 1 2 3 5 6 7 8 9 10 11 12 13 14 15 Field COM TBS PTDIV PTSEL CRQEN EBDF HRESET 0 0 0 0 0 POR 0 0 0 0 0 0 0 0 R W R W Addr IMMR 0xFFFF0000 280 16 17 18 19 20 21 23 24 26 27 29 30 31 Field DFSYNC DFBRG DFNL DFNH DFUTP DFAUTP HRESET 0 POR 0 R W R W Addr IMMR 0xFFFF0000 282 Note HRESET is h...

Page 435: ...he periodic interrupt timer is divided by 4 or 512 At power on reset this bit is cleared if the MODCK1 and MODCK2 signals are low 0 The clock is divided by 4 1 The clock is divided by 512 8 PTSEL Periodic interrupt timer select Selects the crystal oscillator or main clock oscillator as the input source to PITCLK At power on reset it reflects the value of MODCK1 0 OSCM crystal oscillator is selecte...

Page 436: ...system clocks to be used in low power mode In low power mode the MPC885 automatically switches to the DFNL frequency To select the DFNL frequency load this field with the divide value and set the CSRC bit A loss of lock condition will not occur when changing the value of this field This field is cleared by a power on or hard reset 000 Divide by 2 001 Divide by 4 010 Divide by 8 011 Divide by 16 10...

Page 437: ...the MFN is 0 to 31 The numerator of the fractional part of the multiplication factor MFN must be less than the denominator of the fractional part of the multiplication factor MFD 1 1 If the numerator is larger than the denominator the output clock frequency will differ from the desired frequency If the numerator is zero the circuit for fractional division is disabled to save power Refer to Section...

Page 438: ...e cleared 24 CSR Checkstop reset enable Enables an automatic reset when the processor enters checkstop mode If the processor enters debug mode at reset reset is not generated automatically refer to Table 14 10 See Section 53 5 2 2 Debug Enable Register DER 25 Reserved should be cleared 26 FIOPD Force I O pull down Indicates when the address and data external pins are driven by an internal pull dow...

Page 439: ...conductor 14 23 Table 14 10 describes PLPRCR CSR and DER CHSTPE bit combinations Table 14 10 PLPRCR CSR and DER CHSTPE Bit Combinations PLPRCR CSR DER CHSTPE Checkstop Mode Result 0 0 No 0 0 Yes 0 1 No 0 1 Yes Enter debug mode 1 0 No 1 0 Yes Automatic reset 1 1 No 1 1 Yes Enter debug mode ...

Page 440: ...Clocks and Power Control MPC885 PowerQUICC Family Reference Manual Rev 2 14 24 Freescale Semiconductor ...

Page 441: ...fore it is typically used to interface with higher performance run time memory such as DRAM and bursting SRAM The UPM supports address multiplexing of the external bus periodic timers and generation of programmable control signals for row address and column address strobes to allow for a glueless interface to DRAM devices The periodic timers allow refresh cycles to be initiated while the address M...

Page 442: ...un when an external asynchronous master requests a single beat read or write access UPM periodic timer runs a user specified control signal pattern to support refresh User specified control signal patterns can be initiated by software Each UPM can be defined to support DRAM devices with depths of 64 128 256 and 512 Kbytes and 1 2 4 8 16 32 64 128 and 256 Mbytes Each UPM provides programmable timin...

Page 443: ...sable Timer Memory Command Register MCR Memory Status Register MSTAT Memory Address Register MAR Option Register OR UPM Arbiter Memory Data Register MDR Base Register BR Base Register BR UPMA or UPMB GPCM Wait State Counter Memory Periodic Timer Prescale Register MPTPR CS 0 7 BS_x 0 3 GPLx 0 5 TA DLT3 Internal UPWAITx NA and AMX Fields WE 0 3 OE in RAM Word CS 0 7 WP RD WR SCY 0 3 Expired Load Att...

Page 444: ...vides a glueless interface to EPROM SRAM flash EPROM and other peripherals GPCM signals are available on CS 0 7 CS0 lets the CPU access the boot EPROM from reset Each chip select allows up to 30 wait states Some features are common to all eight memory banks The block size of each memory bank can vary between 32 Kbytes and 256 Mbytes for a full 4 Gbytes of the address space Each memory bank can be ...

Page 445: ...hine The UPM toggles the memory controller external signals as programmed in RAM when an internal or external master initiates an external single beat or burst read write access The UPM also controls address multiplexing address increment and transfer acknowledge assertion for each memory access The UPM specifies a set of signal patterns for a user specified number of clock cycles The UPM RAM patt...

Page 446: ...5 1 Memory Controller Register Usage Register Used by the GPCM Used by a UPM Base register bank 0 7 register BRx Option register bank 0 7 register ORx Memory status register MSTAT Memory command register MCR Machine A mode register MAMR Machine B mode register MBMR Memory data register MDR Memory address register MAR Memory periodic timer prescaler register MPTPR Address Comparator Bank Select UPM...

Page 447: ...ip selects ORx should be programmed before BRx except when programming the boot chip select CS0 after hardware reset in which case BR0 should be programmed before OR0 15 3 3 Memory Bank Write Protection Attempting to write to an address range marked restricted in BRx WP causes a write protect violation for which MSTAT WPER is set 15 3 4 Address Type Protection BRx AT and ORx ATM can be used to imp...

Page 448: ...RAM array for the MDR The memory address register MAR specifies the address to be driven on the external bus when a UPM pattern is software initiated by issuing a RUN command in the MCR The memory periodic timer prescaler register MPTPR defines the divisor of the external bus clock used as the memory periodic timer input 15 3 8 GPCM Specific Registers There are no GPCM specific registers All GPCM ...

Page 449: ...0000 0x102 BR0 0x10A BR1 0x112 BR2 0x11A BR3 0x122 BR4 0x12A BR5 0x132 BR6 0x13A BR7 Figure 15 5 Base Registers BRx 0 15 Field BA Reset xxxx_xxxx_xxxx_xxxx1 R W R W Addr IMMR 0xFFFF0000 0x100 16 17 19 20 21 22 23 24 25 26 30 31 Field BA AT PS WP MS V Reset x xxx 2 0 0 00 00_000 3 R W R W Addr IMMR 0xFFFF0000 0x102 1 Because at reset the base address value of BR0 is unknown to ensure proper operati...

Page 450: ...ection 11 3 1 1 Hard Reset Configuration Word 00 32 bit port size 01 8 bit port size 10 16 bit port size 11 Reserved 22 Reserved should be cleared 23 WP Write protect Can be used to restrict write accesses within the address range of a BR 0 Both read and write accesses are allowed 1 Only read accesses are allowed The memory controller does not assert CSx and TA on write cycles to this memory bank ...

Page 451: ...d AM Reset xxxx_xxxx_xxxx_xxxx R W R W Addr IMMR 0xFFFF0000 0x104 OR0 0x10C OR1 0x114 OR2 0x11C OR3 0x124 OR4 0x12C OR5 0x134 OR6 0x13C OR7 16 17 18 19 20 21 22 23 24 27 28 29 30 31 Field AM ATM CSNT SAM ACS G5LA G5LS BIH SCY SETA TRLX EHTR Reset xxxx_xxxx_xxxx_xxx0 R W R W Addr IMMR 0xFFFF0000 0x106 Figure 15 7 Option Registers ORx 0 15 Field AM Reset 0000_0000_0000_0000 R W R Addr IMMR 0xFFFF000...

Page 452: ...r multiplexed according to the setting of MAMR AMA UPMA or MBMR AMB UPMB 21 22 ACS ACS address to chip select setup Lets the GPCM control CSx assertion relative to address lines valid 00 CS is output at the same time as the address lines 01 Reserved 10 CS is output a quarter of a clock after the address lines 11 CS is output half a clock after the address lines G5LA G5LS G5LA and G5LS general purp...

Page 453: ... effect of TRLX in Table 15 11 TRLX also doubles the wait states programmed in SCY 30 EHTR Extended hold time on read GPCM only 0 Timing is defined by the memory controller 1 After a read from the current bank an additional clock cycle is inserted before the memory controller responds to a write or read to another bank 31 Reserved should be cleared 0 1 2 3 4 5 6 7 8 9 15 Field WPER Reset 0000_0000...

Page 454: ...hich determines value for UPMx to refresh memory NCS is an integer between 1 and 8 that represents the number of enabled chip selects that are serviced by this UPM SCCR DFBRG is defined in Section 14 6 1 System Clock and Reset Control Register SCCR For example for DRAM to maintain data integrity an access or refresh must occur every 15 6 µs Given a 25 MHz system clock with the required service rat...

Page 455: ...xplicitly in the UPM RAM words 00 1 cycle disable period 01 2 cycle disable period 10 3 cycle disable period 11 4 cycle disable period 15 Reserved should be cleared 16 18 G0CLx 0 2 General line 0 control x Selects the address line output to the internal GPL0 signal in the special case where the functionality is enabled in the G0L and G0H bits of the UPM RAM word 000 A12 001 A11 010 A10 011 A9 100 ...

Page 456: ...the pattern in the RAM array beginning with the RAM word indexed by MCR MAD on the memory bank specified in MCR MB The AMX bits of the UPM RAM word in this software initiated pattern must all be set to 0b11 Thus the address for this pattern is the value written to MAR The data bus is not driven 11 Reserved 2 7 Reserved should be cleared 8 UM User machine Selects the UPM for this command 0 UPMA 1 U...

Page 457: ...The memory address register contains an address to be driven on the external bus in the case of a RUN command issued to the MCR 0 15 Field MD Reset xxxx_xxxx_xxxx_xxxx R W R W Addr IMMR 0xFFFF0000 0x17C 16 31 Field MD Reset xxxx_xxxx_xxxx_xxxx R W R W Addr IMMR 0xFFFF0000 0x17E Figure 15 12 Memory Data Register MDR Table 15 8 MDR Field Descriptions Bits Name Description 0 31 MD Memory data Contain...

Page 458: ...nfiguration register groups BRx ORx and MSTAT The GPCM provides a CS signal for memory bank activation WE signals for write cycles for each byte written to memory and OE signals for read cycles Figure 15 15 shows a simple connection between an SRAM device and the MPC885 Table 15 9 MAR Field Description Bits Name Description 0 31 MA Contains a 32 bit address to be output on the address bus if AMX 0...

Page 459: ...PCM Strobe Signal Behavior Configuration Signal Behavior ORx TRLX Access SCCR EBDF ORx CSNT ORx ACS Address to CS Asserted Address to OE Asserted Address to WE Asserted Data to WE Asserted CS Negated to Address Data Invalid WE Negated to Address Data Invalid Total Cycles 0 Read x x 00 0 3 4 Clk x x 1 4 Clk x 2 SCY1 10 1 4 Clk 11 1 2 Clk Write 0 00 0 x 1 4 Clk 10 1 4 Clk 3 4 Clk 1 4 Clk 11 1 2 Clk ...

Page 460: ...the memory device and R W is connected to the respective R W in the peripheral device 1 Read x x 00 0 3 4 Clk x x 1 4 Clk x 2 2 SCY 10 1 1 4 Clk 1 3 4 Clk 3 2 SCY 11 1 1 2 Clk Write 0 00 0 x 3 4 Clk 1 4 Clk 1 4 Clk 2 2 SCY 10 1 1 4 Clk 1 3 4 Clk 3 4 Clk 3 2 SCY 11 1 1 2 Clk 00 1 00 0 3 4 Clk 1 4 Clk 1 1 2 Clk 10 1 1 4 Clk 1 3 4 Clk 3 4 Clk 1 1 2 Clk 4 2 SCY 11 1 1 2 Clk 01 00 0 3 4 Clk 1 4 Clk 1 4...

Page 461: ...ment Figure 15 17 GPCM Peripheral Device Basic Timing ACS 1x and TRLX 0 15 5 1 2 Chip Select and Write Enable Deassertion Timing Figure 15 18 shows a basic connection between the MPC885 and a static memory device Here CS is connected directly to CE of the memory device The WE signals are connected to the respective W signal in the memory device where each WE corresponds to a different data byte Ad...

Page 462: ...trols the timing for the appropriate strobe negation in write cycles When this attribute is asserted the strobe is negated one quarter of a clock before the normal case For example when ACS 00 and CSNT 1 WE is negated one quarter of a clock earlier as shown in Figure 15 19 When ACS 00 and CSNT 1 WE and CS are negated one quarter of a clock earlier as shown in Figure 15 20 Figure 15 19 GPCM Memory ...

Page 463: ... provided for memory systems that require more relaxed timing between signals When TRLX 1 and ACS 00 an additional cycle between the address and strobes is inserted by the MPC885 memory controller See Figure 15 21 and Figure 15 22 Figure 15 21 GPCM Relaxed Timing Read ACS 1x SCY 1 CSNT 0 TRLX 1 Clock Address TS TA CS WE Data CSNT 1 ACS 11 ACS 10 Clock Address TS TA CS R W WE OE Data ACS 10 ACS 11 ...

Page 464: ...one clock earlier than in the normal case If ACS 0 CS is also negated one clock earlier as shown in Figure 15 23 and Figure 15 24 When a bank is selected to operate with external transfer acknowledge SETA and TRLX 1 the memory controller does not support external devices that provide TA to complete the transfer with zero wait states The minimum access duration in this case is 3 clock cycles Clock ...

Page 465: ...l Rev 2 Freescale Semiconductor 15 25 Figure 15 23 GPCM Relaxed Timing Write ACS 1x SCY 0 CSNT 1 TRLX 1 Figure 15 24 GPCM Relaxed Timing Write ACS 00 SCY 0 CSNT 1 TRLX 1 Clock Address TS TA CS R W WE OE Data ACS 10 ACS 11 Clock Address TS TA CS R W WE OE Data ...

Page 466: ... master or a maximum 17 clock access by programming ORx SCY The internal TA generation mode is enabled if ORx SETA is cleared If TA is asserted externally at least two clock cycles before the wait state counter has expired the current memory cycle is terminated When TRLX is set the number of wait states inserted by the memory controller is defined by 2 x SCY or a maximum of 30 wait states 15 5 1 6...

Page 467: ...Controller MPC885 PowerQUICC Family Reference Manual Rev 2 Freescale Semiconductor 15 27 Figure 15 26 GPCM Read Followed by Write EHTR 1 Clock Address TS TA CSx CSy R W OE Data Hold Time Long hold time allowed ...

Page 468: ... MPC885 PowerQUICC Family Reference Manual Rev 2 15 28 Freescale Semiconductor Figure 15 27 GPCM Read Followed by Read from Different Banks EHTR 1 Clock Address TS TA CSx CSy R W OE Data Hold Time Long hold time allowed ...

Page 469: ...register is accessed The boot chip select provides a programmable port size during system reset by using the BPS field of the hard reset configuration word described in Section 11 3 1 1 Setting these appropriately allows a boot ROM to be located anywhere in the address space The boot chip select does not provide write protection and responds to all address types CS0 operates this way until the fir...

Page 470: ...ices Figure 15 30 shows the timing for TRLX 0 when an external asynchronous master accesses SRAM TA WE and OE remain asserted until the external master negates AS at which point they deassert asynchronously Table 15 12 Boot Bank Field Values After Reset Register Field Name Value BR0 PS From hard reset configuration word 0 WP 0 MS 00 V From hard reset configuration word OR0 AM All zeros ATM 000 CSN...

Page 471: ...Sx for slaves that provide their TA signal external to the MPC885 ORx SETA 1 However the GPCM keeps its chip select asserted only until the first TA is sampled The GPCM cannot be used to burst to an external device the requires that the chip select signal remain asserted throughout a burst transaction However if the device requires only that the chip select be asserted up to the first data beat of...

Page 472: ...ing events initiate a UPM cycle Any internal or external master requests an external memory access to an address space mapped to a chip select serviced by the UPM A UPM periodic timer expires and requests a transaction such as a DRAM refresh A transfer error or reset generates an exception request The MCR receives a RUN command from the CPU Figure 15 31 User Programmable Machine Block Diagram The ...

Page 473: ...tiate patterns starting at any of the 64 UPM RAM words Figure 15 32 RAM Array Indexing 15 6 1 1 Internal External Memory Access Requests When an internal master requests a new access to external memory the address and type of transfer are compared to each valid bank defined in BRx The value in BRx MS selects the UPM to handle the memory access The user must ensure that the UPM is appropriately ini...

Page 474: ...For these special cycles the user creates a special RAM pattern that can be stored in any unused areas in the UPM RAM and the MCR RUN command is used to run the cycle The UPM runs the pattern beginning at the specified RAM location until it encounters a RAM word with its LAST bit set 15 6 1 4 Exception Requests When the MPC885 under UPM control initiates an access to a memory device the external d...

Page 475: ... GCLK1_50 does not have a 50 duty cycle Figure 15 35 UPM Clock Scheme Two Division Factor 2 The state of the external signals may change if specified in the RAM array at any edge of GCLK1_50 and GCLK2_50 plus a propagation delay specified in the MPC885 Hardware Specifications Note however that only the CS signal corresponding to the currently accessed bank will be manipulated by the UPM pattern wh...

Page 476: ...y the timing of chip selects byte selects and GPL signals based on the edges of GCLK1_50 or GCLK2_50 The clock phases shown refer to the timing windows when the signals controlled by these bits in the RAM word are driven Figure 15 36 UPM Signals Timing Example One Division Factor 1 EBDF 00 CLKOUT GCLK1_50 GCLK2_50 GPL2 Clock Phase 1 2 3 4 1 2 3 4 CS GPL1 CST3 G1T4 CST2 G1T3 G1T4 G1T4 G1T3 G1T4 G2T...

Page 477: ... is for the bank that matches the current address The selected BS is for the byte lanes read or written by the access Figure 15 38 RAM Array and Signal Generation CLKOUT GCLK1_50 GCLK2_50 GPL2 Clock Phase 1 2 3 4 1 2 3 CS GPL1 CST3 G1T4 CST1 CST4 CST2 CST2 CST4 CST3 CST1 G1T3 G1T4 G1T4 G1T3 G1T4 G2T3 G2T4 G2T4 G2T3 System Clock RAM Word RAM Word 4 RAM Array Signals Timing Generator CS Signal Selec...

Page 478: ...t cycle RBS 0x08 Write single beat cycle WSS 0x18 Write burst cycle WBS 0x20 Periodic timer request PTS 0x30 Exception EXS 0x3C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field CST4 CST1 CST2 CST3 BST4 BST1 BST2 BST3 G0L G0H G1T4 G1T3 G2T4 G2T3 Reset R W R W Addr MCR MAD indirect addressing of 1 of 64 entries 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field G3T4 G3T3 G4T4 DLT3 G4T3 WAEN G5T4 G5T3 ...

Page 479: ... select timing 3 Defines the state of BS during clock phase 4 0 Asserted at the falling edge of GCLK1_50 1 Negated at the falling edge of GCLK1_50 The final value of the BS lines depends on the values of BRx PS the TSIZ lines and A 30 31 for the access See Section 15 6 4 3 Byte Select Signals BSTx 8 9 G0L General purpose line 0 lower Defines the state of GPL0 during phases 1 3 10 Asserted at the f...

Page 480: ...ed external signals are frozen when UPWAITx is asserted UPWAITx is sampled on the falling edge of GCLK2_50 See Figure 15 45 for more information 20 G5T4 General purpose line 5 timing 4 Defines the state of GPL5 during phase 1 3 0 The value of GPL5 at the falling edge of GCLK2_50 will be 0 1 The value of GPL5 at the falling edge of GCLK2_50 will be 1 21 G5T3 General purpose line 5 timing 3 Defines ...

Page 481: ...S the increment value of A 28 31 and or BADDR 28 30 at the falling edge of GCLK1_50 is as follows If the accessed bank has a 32 bit port size the value is incremented by 4 If the accessed bank has a 16 bit port size the value is incremented by 2 If the accessed bank has an 8 bit port size the value is incremented by 1 Note The value of NA is relevant only when the UPM serves a burst read or burst ...

Page 482: ...tate of each BS 0 3 signal depends on the value of each BSTx bit and the values of BRx PS TSIZn and A 30 31 in the current cycle The BS signals are also controlled by the port size of the accessed bank the transfer size of the transaction and the address accessed Figure 15 41 shows how UPMs control BS signals Figure 15 41 BSx Signal Selection UPMA UPMB GPCM MUX MS 0 1 in BRx CS0 CS1 CS2 CS3 CS4 CS...

Page 483: ...cal value of the signal to be changed at the falling edge of GCLK1_50 or GCLK2_50 GPL0 has two 2 bit fields that perform this function plus an additional function explained below GPL5 and GPL0 offer the following enhancements beyond the other GPLx signals GPL5 can be controlled during phase 4 of the first clock cycle according to the value of G5LS as shown in Figure 15 42 This allows it to assert ...

Page 484: ... by the RUN command exception or memory periodic timer requests Table 15 16 GPL_x5 Signal Behavior Controlling Machine ORx RAM Word GPL_x5 Behavior at the Controlling Clock Edge Memory Access Slave Access Clock Cycle G5LA G5LS G5T4 G5T3 GPCM x N A N A x x GPL_A5 and GPL_B5 do not change their value UPMA First x 0 x x GPL_A5 is driven low at the falling edge of GCLK1_50 1 GPL_A5 is driven high at t...

Page 485: ...GCLK1_50 1 0 x x GPL_A5 is driven low at the falling edge of GCLK1_50 1 GPL_A5 is driven high at the falling edge of GCLK1_50 Second third 0 x 0 x GPL_B5 is driven low at the falling edge of GCLK2_50 in the current UPM cycle 1 x GPL_B5 is driven high at the falling edge of GCLK2_50 in the current UPM cycle x 0 GPL_B5 is driven low at the falling edge of GCLK1_50 in the current UPM cycle x 1 GPL_B5...

Page 486: ...the upper address signals can be driven on the lower address lines MxMR AMA and MxMR AMB control which upper address signals are on which lower address signals Note that this feature of internally multiplexing address signals should only be used in a system where the MPC885 is the only external bus master If other devices can be bus masters address multiplexing must be done in external logic One o...

Page 487: ... on External Pin when Address Multiplexing is Enabled A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 001 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 010 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 011 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 100 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 101 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 ...

Page 488: ...n for DRAM Interface Data Bus Width Memory Size DRAM Address Pin Number MPC885 Address Pin Connection AMx Row Column 8 bits 64 Kbyte 8 8 A24 A31 000 128 Kbyte 9 A23 A31 256 Kbyte 10 A22 A31 512 Kbyte 11 A21 A31 1 Mbyte 12 A20 A31 2 Mbyte 13 A19 A31 4 Mbyte 14 A18 A31 256 Kbyte 9 9 A23 A31 001 512 Kbyte 10 A22 A31 1 Mbyte 11 A21 A31 2 Mbyte 12 A20 A31 4 Mbyte 13 A19 A31 8 Mbyte 14 A18 A31 16 Mbyte ...

Page 489: ... A31 4 Mbyte 11 11 A21 A31 011 8 Mbyte 12 A20 A31 16 Mbyte 13 A19 A31 32 Mbyte 14 A18 A31 64 Mbyte 15 A17 A31 16 Mbyte 12 12 A20 A31 100 32 Mbyte 13 A19 A31 64 Mbyte 14 A18 A31 128 Mbyte 15 A17 A31 256 Mbyte 16 A16 A31 64 Mbyte 13 13 A19 A31 101 128 Mbyte 14 A18 A31 256 Mbyte 15 A17 A31 Table 15 19 AMA AMB Definition for DRAM Interface continued Data Bus Width Memory Size DRAM Address Pin Number M...

Page 490: ...A30 16 Mbyte 14 A17 A30 2 Mbyte 10 10 A21 A30 010 4 Mbyte 11 A20 A30 8 Mbyte 12 A19 A30 16 Mbyte 13 A18 A30 32 Mbyte 14 A17 A30 64 Mbyte 15 A16 A30 8 Mbyte 11 11 A20 A30 011 16 Mbyte 12 A19 A30 32 Mbyte 13 A18 A30 64 Mbyte 14 A17 A30 32 Mbyte 12 12 A19 A30 100 64 Mbyte 13 A18 A30 128 Mbyte 14 A17 A30 256 Mbyte 15 A16 A30 128 Mbyte 13 13 A18 A30 101 256 Mbyte 13 A17 A30 Table 15 19 AMA AMB Definiti...

Page 491: ...ata is latched on the falling edge of GCLK2_50 instead of the rising edge which is normal This feature lets the user speed up the memory interface by latching data 1 2 clock early which can be useful during burst reads This feature should be used only in systems without external synchronous bus devices 32 bits 256 Kbyte 8 8 A22 A29 000 512 Kbyte 9 A21 A29 1 Mbyte 10 A20 A29 2 Mbyte 11 A19 A29 4 Mb...

Page 492: ...orced outside of itself while another pattern requires only n 1 15 6 4 10 The Last Word LAST When the LAST bit is read in a RAM word the current UPM pattern terminates and the highest priority pending UPM request if any is serviced immediately in the external memory transactions If the disable timer is activated and the next access is top the same bank the execution of the next UPM pattern is held...

Page 493: ...fter the falling edge of GCLK2_50 as programmed in the RAM word in which WAEN is set This is demonstrated in the example in Figure 15 46 in which the CSx and GPL1 states C12 and F and the WAEN value CC are frozen until AS is recognized as deasserted The TA signal driven by the UPM also remains in its programmed state until AS is negated This allows TA to be used as an asynchronous handshake signal...

Page 494: ...TA specifies whether TA is generated internally or externally The following sections describe how the two mechanisms work 15 7 1 Hierarchical Bus Interface Example Assume that the CPU initiates a local bus read cycle that addresses main memory connected to the system bus The hierarchical bus interface accepts local bus requests and generates a read cycle on the system bus The programmer cannot pre...

Page 495: ...ection 10 4 2 There are two types of external bus masters Synchronous bus masters synchronize with CLKOUT and may or may not use the MPC885 memory controller to access a slave Asynchronous bus masters use an address strobe signal AS that handshakes with the MPC885 memory controller to access a slave device or bypass the memory controller to perform the slave access 15 8 1 Synchronous External Mast...

Page 496: ...s The following sections provide information about the UPM features that support external masters 15 8 4 1 Address Incrementing for External Synchronous Bursting Masters BADDR 28 30 should be used to generate addresses to memory devices for burst accesses They duplicate the value of A 28 30 when an internal master initiates an external bus transaction When an external master initiates an external ...

Page 497: ...ction with the GPCM Note that synchronous and external masters behave differently Synchronous external masters behave like internal masters except for an extra clock cycle at the beginning of the access required for address decode Asynchronous external masters behave as described in Section 15 5 3 External Asynchronous Master Support Figure 15 47 Synchronous External Master Access CLKOUT A 28 31 R...

Page 498: ...MPC885 using this configuration BADDR 28 30 connects to the multiplexer controlled by GPL_A5 Figure 15 50 shows the timing behavior of GPL_A5 BADDR and other control signals when an external master initiates a burst read access The state of GPL_A5 in the first clock cycle of the memory device access is determined by the value of the corresponding ORx G5LS In this example the accessed critical word...

Page 499: ...y Reference Manual Rev 2 Freescale Semiconductor 15 59 Figure 15 49 Synchronous External Master Interconnect Example External DRAM Multiplexer Master A 0 31 BADDR 28 30 D 0 31 R W TS BURST TA TSIZ 0 1 BI BR BG BB CS1 BS 0 3 GPL_A5 Bank MPC885 ...

Page 500: ...0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 g010 g5t4 g5t3 Bit 8 Bit 20 Bit 21 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 22 Bit 23 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 loop exen Bit 24 Bit25 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 amx0 amx1 na uta todt last Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 X X X 1 1 1 RBS...

Page 501: ...AM bank accesses Figure shows the timing behavior of GPL_A5 and other control signals when an external master to a DRAM bank initiates a single beat read The state of GPL_A5 in the first clock cycle of the memory device access is determined by the value of the corresponding ORx G5LS Figure 15 51 Asynchronous External Master Interconnect Example External DRAM Multiplexer Master D 0 31 R W AS TA TSI...

Page 502: ...1 bst2 bst3 Bit 4 Bit 5 Bit 6 Bit 7 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 g4t4 g4t3 WAEN Bit 18 Bit 19 0 1 1 1 0 g5t4 g5t3 Bit 20 Bit 21 0 0 1 1 1 1 1 1 1 1 Bit 22 Bit 23 loop exen Bit 24 Bit25 0 0 0 0 0 0 0 0 0 0 amx0 amx1 na uta todt last Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 RSS RSS 1 WAIT WAIT RSS 2 CLKOUT GCLK2_50 GCLK1_50 AS R...

Page 503: ...nd are controlled by the UPM RAM word The refresh rate is calculated based on a 25 MHz baud rate generator clock and the DRAM that requires a 512 cycle refresh every 8 ms Figure 15 53 Page Mode DRAM Interface Connection Follow these steps to configure a system for page mode DRAM 1 Determine the system architecture which includes the MPC885 and the memory system as shown in the example in Figure 15...

Page 504: ...he address mapping of the DRAM device chosen Use ORx MS to select the machine to control the cycles Notice that ORx SAM determines address multiplexing for the first clock cycle and subsequent cycles are controlled by the UPM RAM words Also notice that the AMX field in the UPM RAM word controls address multiplexing for the next clock cycle rather than the current one Program MAMR to select the num...

Page 505: ...t 6 Bit 7 1 1 1 1 1 0 0 0 0 0 1 1 g0I0 g0I1 g0h0 g0h1 Bit 8 Bit 9 Bit 10 Bit 11 g1t4 g1t3 Bit 12 Bit 13 g2t4 g2t3 Bit 14 Bit 15 g3t4 g3t3 Bit 16 Bit 17 g4t4 g4t3 Bit 18 Bit 19 g5t4 g5t3 Bit 20 Bit 21 Bit 22 Bit 23 loop exen Bit 24 Bit25 0 0 0 0 0 0 amx0 amx1 na uta todt last Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 0 0 0 1 0 0 0 0 0 0 0 0 x x x 1 1 1 RSS RSS 1 RSS 2 CLKOUT GCLK2_50 GCLK1_50 TS R ...

Page 506: ...it 6 Bit 7 1 1 1 1 1 0 0 0 0 0 1 1 g0I0 g0I1 g0h0 g0h1 Bit 8 Bit 9 Bit 10 Bit 11 g1t4 g1t3 Bit 12 Bit 13 g2t4 g2t3 Bit 14 Bit 15 g3t4 g3t3 Bit 16 Bit 17 g4t4 g4t3 Bit 18 Bit 19 g5t4 g5t3 Bit 20 Bit 21 Bit 22 Bit 23 loop exen Bit 24 Bit25 0 0 0 0 0 0 amx0 amx1 na uta todt last Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 0 0 0 1 0 0 0 0 0 0 0 0 x x x 1 1 1 WSS WSS 1 WSS 2 CLKOUT GCLK2_50 GCLK1_50 TS R...

Page 507: ... 1 g0I0 g0I1 g0h0 g0h1 Bit 8 Bit 9 Bit 10 Bit 11 g1t4 g1t3 Bit 12 Bit 13 g2t4 g2t3 Bit 14 Bit 15 g3t4 g3t3 Bit 16 Bit 17 g4t4 g4t3 Bit 18 Bit 19 g5t4 g5t3 Bit 20 Bit 21 Bit 22 Bit 23 loop exen Bit 24 Bit25 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 amx0 amx1 na uta todt last Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0...

Page 508: ... 0 0 0 0 1 1 g0I0 g0I1 g0h0 g0h1 Bit 8 Bit 9 Bit 10 Bit 11 g1t4 g1t3 Bit 12 Bit 13 g2t4 g2t3 Bit 14 Bit 15 g3t4 g3t3 Bit 16 Bit 17 g4t4 g4t3 Bit 18 Bit 19 g5t4 g5t3 Bit 20 Bit 21 Bit 22 Bit 23 loop Bit 24 0 1 1 0 0 exen Bit25 0 0 1 0 0 amx0 amx1 na uta todt last Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 x x x 1 1 1 RBS RBS 1 RBS 2 RBS 3 RBS 4 CLKOUT ...

Page 509: ... 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 0 0 0 0 0 0 0 0 exen Bit 25 0 0 1 0 1 0 1 0 0 amx0 Bit 26 0 0 0 0 0 0 0 0 x amx1 Bit 27 0 0 0 0 0 0 0 0 x na Bit 28 0 0 1 0 1 0 1 0 x uta Bit 29 1 0 1 0 1 0 1 0 1 todt Bit 30 0 0 0 0 0 0 0 0 1 last Bit 3...

Page 510: ... 7 1 0 1 0 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 1 1 0 0 exen Bit 25 0 0 1 0 0 amx0 Bit 26 0 0 0 0 x amx1 Bit 27 0 0 0 0 x na Bit 28 0 0 1 0 x uta Bit 29 1 0 1 0 1 todt Bit 30 0 0 0 0 1 last Bit 31 0 0 0 0 1 WBS WBS 1 WBS 2 WBS 3 WBS 4 CLKOUT...

Page 511: ... bst1 Bit 5 0 0 0 bst2 Bit 6 0 0 1 bst3 Bit 7 0 0 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 0 0 exen Bit 25 0 0 0 amx0 Bit 26 0 0 x amx1 Bit 27 0 0 x na Bit 28 0 0 x uta Bit 29 1 1 1 todt Bit 30 0 0 1 last Bit 31 0 0 1 PTS PTS 1 PTS 2 CLKOUT GCLK...

Page 512: ...re 15 56 of can be reduced from 9 to 6 cycles for 32 bit port size Cycles can be reduced by using faster DRAM or a slower system clock that meets the DRAM access time For a 16 bit port size memory the reduction is from 17 to 10 cycles and when an 8 bit port size memory is connected the reduction is from 33 to 18 cycles cst4 Bit 0 1 cst1 Bit 1 1 cst2 Bit 2 1 cst3 Bit 3 1 bst4 Bit 4 1 bst1 Bit 5 1 b...

Page 513: ...it 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 1 1 1 1 1 1 g4t3 Bit 19 0 0 0 0 0 0 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 0 0 0 0 0 exen Bit 25 0 0 0 0 0 0 amx0 Bit 26 0 0 0 0 1 x amx1 Bit 27 0 0 0 0 0 x na Bit 28 0 1 1 1 0 x uta Bit 29 1 0 1 0 0 1 todt Bit 30 0 0 0 0 0 1 last Bit 31 0 0 0 0 0 1 RBS RBS 1 RBS...

Page 514: ...udes the MPC885 and the memory system as shown in the example in Figure 15 64 2 Use the blank work sheet in Figure 15 70 for timing diagrams The timing diagrams in Figure 15 64 through Figure 15 69 can be used as a reference 3 Translate the timing diagrams into RAM words for each memory access type The bottom half of the figures show the RAM array contents that handle each of the possible cycles e...

Page 515: ...mber of columns and refresh timer parameters Table 15 21 UPMB Register Settings Register Field Value Comments BR2 MS 10 Selects UPMB PS 00 Selects 32 bit bus width WP 0 Allows read and write accesses MPTPR PTP 0000_0010 Prescaler divided by 32 MBMR PTB 0000_1100 15 6 µs at a 25 MHz clock PTBE 1 Enables periodic timer B AMB 001 Selects nine column address pins DSB 01 Selects two disable timer clock...

Page 516: ...1 0 0 0 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 0 0 0 0 0 g1t3 Bit 13 0 0 0 0 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 0 0 0 0 exen Bit 25 0 0 0 0 0 amx0 Bit 26 0 0 0 0 x amx1 Bit 27 0 0 0 0 x na Bit 28 0 0 0 0 x uta Bit 29 1 1 1 0 1 todt Bit 30 0 0 0 0 1 last Bit 31 0 0 0 0 1 RSS RSS 1 RSS 2 R...

Page 517: ... Bit 7 1 0 0 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 1 1 1 1 g1t3 Bit 13 1 1 1 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 0 0 0 exen Bit 25 0 0 0 0 amx0 Bit 26 0 0 0 x amx1 Bit 27 0 0 0 x na Bit 28 0 0 0 x uta Bit 29 1 1 0 1 todt Bit 30 0 0 0 1 last Bit 31 0 0 0 1 WSS WSS 1 WSS 2 WSS 3 CLKOUT GCL...

Page 518: ... Bit 11 g1t4 Bit 12 0 0 0 0 0 0 0 0 0 0 0 g1t3 Bit 13 0 0 0 0 0 0 0 0 0 0 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 0 0 0 0 0 0 0 0 0 0 exen Bit 25 0 0 0 1 0 1 0 1 0 0 0 amx0 Bit 26 0 0 0 0 0 0 0 0 0 0 x amx1 Bit 27 0 0 0 0 0 0 0 0 0 0 x na Bit 28 0 0 1 0 0 1 0 1 0 0 x uta Bit 29 1 1 1 0 1 0 1 0 1 0 1 todt Bit 30 0...

Page 519: ...0 g0h1 Bit 11 g1t4 Bit 12 1 1 1 1 1 1 1 1 1 1 g1t3 Bit 13 1 1 1 1 1 1 1 1 1 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 0 0 0 0 0 0 0 0 0 exen Bit 25 0 0 0 1 0 1 0 1 0 0 amx0 Bit 26 0 0 0 0 0 0 0 0 0 x amx1 Bit 27 0 0 0 0 0 0 0 0 0 x na Bit 28 0 0 0 1 0 1 0 1 0 x uta Bit 29 1 0 1 1 0 1 0 1 0 1 todt Bit 30 0 0 0 0 0 0...

Page 520: ...1 1 1 bst3 Bit 7 0 1 1 1 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 1 1 1 1 1 g1t3 Bit 13 1 1 1 1 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 0 0 0 0 exen Bit 25 0 0 0 0 0 amx0 Bit 26 0 0 0 0 x amx1 Bit 27 0 0 0 0 x na Bit 28 0 0 0 0 x uta Bit 29 1 1 1 1 1 todt Bit 30 0 0 0 0 1 last Bit 31 0 0 0 0 1 ...

Page 521: ... bst1 Bit 5 1 bst2 Bit 6 1 bst3 Bit 7 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 1 g1t3 Bit 13 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 0 exen Bit 25 0 amx0 Bit 26 x amx1 Bit 27 x na Bit 28 x uta Bit 29 1 todt Bit 30 1 last Bit 31 1 EXS CLKOUT GCLK2_50 GCLK1_50 TA CS2 RAS BS_B 0 3 CAS 0 3 GPL_B1 OE ...

Page 522: ...t 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Bit 22 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 na Bit 28 uta Bit 29 todt Bit 30 last Bit 31 xxS xxS 1 xxS 2 xxS 3 xxS 4 xxS 5 xxS 6 xxS 7 xxS 8 xxS 9 xxS 10 CLKOUT GCLK2_50 GCLK1_50 R W D 0 31 TA CSx RAS BS_x 0 3 CA...

Page 523: ...ation In this system configuration the sockets and system bus must be electrically isolated using external buffers and bus transceivers These buffers also provide voltage conversion required from the 3 3 to 5 V cards These components should be powered by the card power supply Because the MPC885 can accept 5 V inputs while generating 3 3 V outputs conversion is not required for inputs The PCMCIA ho...

Page 524: ...1 1 1 2 26 1 2 6 2 1 1 A B Socket PCMCIA Host Adapter Module CE1_A CE2_A WE PGM_A OE_A IORD_A IOWR_A Address_A 0 25 REG_A VCC_A Chip VDD IRQ CSi D 8 15 D 0 7 RD WR CE1_A B CE2_A B WE PGM OE RESET_A B POE_A B A 6 31 REG ALE_A B WAIT_A B IOIS16_A B RDY BSY_x BVD1_x BVD2_x SPKROUT Transceiver Buffer with OE Buffer with OE Transparent Latch with OE CD1_x CD2_x VS1_x VS2_x Power On Indication MAX 780A ...

Page 525: ... even only 0 0 0 8 bit odd 1 0 1 8 bit even 0 1 0 No access X 1 1 D 0 15 Data bus Bidirectional D 0 15 constitute the bidirectional data bus The msb is D0 and the lsb is D15 WAIT_x Extend bus cycle Input Asserted by the PC card to delay completion of the pending memory or I O cycle RD WR External transceiver direction Output Asserted during MPC885 read cycles and negated during write cycles Used i...

Page 526: ...re connected to IP_x 0 1 WP Write protect Input When the card and socket are programmed for memory interface operation this signal is used as WP It reflects the state of the write protect switch on the PC card The PC card must assert WP when the card switch is enabled It must be negated when the switch is disabled For a PC card that is writable without a switch WP must be connected to ground If th...

Page 527: ...ration this signal is used as IREQ_x and must be asserted by a PC card to indicate that a device on the PC card requires service by host software Must be held negated when no interrupt is requested These signals are connected to IP_x7 Table 16 3 PCMCIA Output Port Signals Signal Description RESET_x Card reset Output Provided to clear the card s configuration option register thus placing the card i...

Page 528: ...ck the real access time is access time one clock 600 ns 200 ns 150 ns 100 ns STP2 2 Worst case setup time STP The worst case setup time is address to strobe LNG 3 3 Length LNG is the minimum strobe time HLD4 4 Worst case hold time HLD The worst case hold time is data disable from OE STP LNG HLD STP LNG HLD STP LNG HLD Clock Cycle 100 300 150 30 120 90 20 80 75 15 60 50 20 ns 50 MHz 6 24 8 2 8 5 2 ...

Page 529: ...The user can reset the PCMCIA cards or disable the output of the external latches by writing to PGCRx CxRESET and PGCRx CxOE respectively 16 3 6 DMA The MPC885 DMA module with the CPM microcode provides two independent DMA IDMA channels See Section 19 3 IDMA Emulation The PCMCIA module can be programmed to generate control for an I O device implemented as a PCMCIA card to respond to DMA transfer A...

Page 530: ...uts from the PCMCIA card to the host BVD CD RDY VS is reported to the PIPR shown in Figure 16 3 PIPR is a read only register write operations are ignored Table 16 7 PCMCIA Registers Name Description PIPR PCMCIA interface input pins register PSCR PCMCIA interface status changed register PER PCMCIA interface enable register PGCRA PCMCIA interface general control register a PGCRB PCMCIA interface gen...

Page 531: ...eld Descriptions Bits Name Description 0 CAVS1 Voltage sense 1 for card A 1 CAVS2 Voltage sense 2 for card A 2 CAWP Write protect for card A 3 CACD2 Card detect 2 for card A 4 CACD1 Card detect 1 for card A 5 CABVD2 Battery voltage SPKR_A input for card A 6 CABVD1 Battery voltage STSCHG_A input for card A 7 CARDY RDY IRQ of card A pin 8 15 Reserved should be cleared 16 CBVS1 Voltage sense 1 for ca...

Page 532: ...Reset Undefined R W R W Addr IMMR 0xFFFF0000 0x0EA Figure 16 4 PCMCIA Interface Status Changed Register PSCR Table 16 9 PSCR Field Descriptions Bits Name Description 0 CAVS1_C Voltage sense 1 for card A changed 1 CAVS2_C Voltage sense 2 for card A changed 2 CAWP_C Write protect for card A changed 3 CACD2_C Card detect 2 for card A changed 4 CACD1_C Card detect 1 for card A changed 5 CABVD2_C Batte...

Page 533: ...RQ of card B pin is high Device and socket interrupt 26 CBRDY_R RDY IRQ of card B pin rising edge detected Device and socket interrupt 27 CBRDY_F RDY IRQ of card B pin falling edge detected Device and socket interrupt 28 31 Reserved should be cleared 0 1 2 3 4 5 6 7 8 9 10 11 12 15 Field CA_EV S1 CA_EV S2 CA_E WP CA_EC D2 CA_EC D1 CA_EBV D2 CA_EBV D1 CA_ERDY _L CA_ERDY _H CA_ERDY _R CA_ERDY _F Res...

Page 534: ...8 CA_ERDY_L Enable for RDY IRQ of card A pin is low 9 CA_ERDY_H Enable for RDY IRQ card A pin is high 10 CA_ERDY_R Enable for RDY IRQ card A pin rising edge detected 11 CA_ERDY_F Enable for RDY IRQ card A pin falling edge detected 12 15 Reserved should be 0 16 CB_EVS1 Enable for voltage sense 1 for card B changed Setting this bit enables the interrupt on any signal change 17 CB_EVS2 Enable for vol...

Page 535: ... Control Register PGCRx Table 16 11 PGCRx Field Descriptions Bits Name Description 0 7 CxIREQLVL Card x IREQ_x interrupt level Only one bit of this field should be set at any time 8 15 CxSCHLVL Card x STSCHG_x interrupt level Only one CASCHLVLx bit should be set at any time 16 17 CxDREQ Card x DREQ Defines internal DMA request for the on chip DMA controller CADREQ controls DMA channel 0 CBDREQ con...

Page 536: ...80 PBR0 0x088 PBR1 0x090 PBR2 0x098 PBR3 0x0A0 PBR4 0x0A8 PBR5 0x0B0 PBR6 0x0B8 PBR7 Figure 16 7 PCMCIA Base Register PBR Table 16 12 PBR Field Descriptions Bits Name Description 0 31 PBA PCMCIA base address Compared to the address on the address bus to determine if a PCMCIA window is being accessed by an internal bus master PBA is used with POR BSIZE 0 4 5 11 12 15 Field BSIZE PSHT Reset Undefine...

Page 537: ...1111 1111 1111 1111 1111 1111 1110 00011 1111 1111 1111 1111 1111 1111 1111 1100 00010 1111 1111 1111 1111 1111 1111 1111 1000 00110 1111 1111 1111 1111 1111 1111 1111 0000 00111 1111 1111 1111 1111 1111 1111 1110 0000 00101 1111 1111 1111 1111 1111 1111 1100 0000 00100 1111 1111 1111 1111 1111 1111 1000 0000 01100 1111 1111 1111 1111 1111 1111 0000 0000 01101 1111 1111 1111 1111 1111 1110 0000 00...

Page 538: ...g a PCMCIA access for this window and thus it is the main parameter for determining cycle length The cycle may be lengthened by asserting WAIT 00001 Strobe asserted 1 clock cycles 00010 Strobe asserted 2 clock cycles 11111 Strobe asserted 31 clock cycles 00000 Strobe asserted 32 clock cycles 25 PPS PCMCIA port size Specifies the port size of this PCMCIA window 0 8 bits port size 1 16 bits port siz...

Page 539: ...ductor 16 17 16 5 PCMCIA Controller Timing Examples Figure 16 9 through Figure 16 18 provide examples of PCMCIA controller timings Figure 16 9 PCMCIA Single Beat Read Cycle PRS 0 PSST 1 PSL 3 PSHT 1 CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE PCOE CE1 CE2 WAIT Data TA PSL PSHT PSST ...

Page 540: ...PowerQUICC Family Reference Manual Rev 2 16 18 Freescale Semiconductor Figure 16 10 PCMCIA Single Beat Read Cycle PRS 0 PSST 2 PSL 4 PSHT 1 CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE PCOE WAIT CE1 CE2 Data TA PSL PSHT PSST ...

Page 541: ...PowerQUICC Family Reference Manual Rev 2 Freescale Semiconductor 16 19 Figure 16 11 PCMCIA Single Beat Read Cycle PRS 0 PSST 1 PSL 3 PSHT 0 CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE PCOE CE1 CE2 TA Data WAIT PSL PSHT PSST ...

Page 542: ...PowerQUICC Family Reference Manual Rev 2 16 20 Freescale Semiconductor Figure 16 12 PCMCIA Single Beat Write Cycle PRS 2 PSST 1 PSL 3 PSHT 1 CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE PCWE CE1 CE2 WAIT Data TA PSL PSHT PSST ...

Page 543: ...erQUICC Family Reference Manual Rev 2 Freescale Semiconductor 16 21 Figure 16 13 PCMCIA Single Beat Write Cycle PRS 3 PSST 1 PSL 4 PSHT 3 CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE IOWR CE1 CE2 WAIT Data TA IO16 PSL PSHT PSST ...

Page 544: ...CC Family Reference Manual Rev 2 16 22 Freescale Semiconductor Figure 16 14 PCMCIA Single Beat Write with Wait PRS 3 PSST 1 PSL 3 PSHT 0 CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE IOWR CE1 CE2 WAIT Data TA PSL PSST PSHT Wait Delay ...

Page 545: ...ICC Family Reference Manual Rev 2 Freescale Semiconductor 16 23 Figure 16 15 PCMCIA Single Beat Read with Wait PRS 3 PSST 1 PSL 3 PSHT 1 CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE IORD CE1 CE2 WAIT Data TA PSL PSST PSHT Wait Delay ...

Page 546: ...885 PowerQUICC Family Reference Manual Rev 2 16 24 Freescale Semiconductor Figure 16 16 PCMCIA I O Read PPS 1 PRS 3 PSST 1 PSL 2 PSHT 0 CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE IOWR CE2 IO16 TA Data PSL PSHT PSST CE1 ...

Page 547: ...erQUICC Family Reference Manual Rev 2 Freescale Semiconductor 16 25 Figure 16 17 PCMCIA I O Read PPS 1 PRS 3 PSST 1 PSL 2 PSHT 0 PSST PSST CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE IOWR CE1 Data TA IO16 PSL PSHT CE2 PSL PSHT ...

Page 548: ...rence Manual Rev 2 16 26 Freescale Semiconductor Figure 16 18 PCMCIA DMA Read Cycle PRS 4 PSST 1 PSL 3 PSHT 0 Data PSST PSST CLKOUT BR BG BB A 6 31 RD WR REG BURST TS ALE IORD CE1 CE2 SIZE TA PSL PSHT PSL PSHT PCOE AT 0xF AT 0xF SIZE Word SIZE Half ...

Page 549: ...and IDMA Emulation describes the two physical serial DMA SDMA channels on the MPC885 with which the CP implements virtual SDMA channels Chapter 20 Serial Interface describes the serial interface SI in which the physical interface to all SCCs and SMCs is implemented Chapter 21 Serial Communications Controllers describes the serial communications controllers SCC which can be configured independently...

Page 550: ...s such as microcontrollers EEPROMs real time clock devices and A D converters Chapter 33 Parallel Interface Port PIP describes the parallel interface port which allows data to be sent to and from the MPC885 over 8 or 16 parallel data lines with two handshake control signals Chapter 34 Parallel I O Ports describes the four general purpose I O ports A B C and D Each signal in the I O ports can be co...

Page 551: ...ates an undefined numerical value NOT logical operator AND logical operator OR logical operator Acronyms and Abbreviations Table V 1 contains acronyms and abbreviations used in this document Note that the meanings for some acronyms such as SDR1 and DSISR are historical and the words for which an acronym stands may not be intuitively obvious Table V 1 Acronyms and Abbreviated Terms Term Meaning ALU...

Page 552: ...SDN Integrated services digital network JTAG Joint Test Action Group LIFO Last in first out LRU Least recently used LSB Least significant byte lsb Least significant bit MAC Multiply accumulate MSB Most significant byte msb Most significant bit MSR Machine state register NaN Not a number NMSI Nonmultiplexed serial interface OSI Open systems interconnection PCI Peripheral component interconnect PPM ...

Page 553: ...l interface SRAM Static random access memory TDM Time division multiplexed TE Terminal endpoint of an ISDN connection TLB Translation lookaside buffer TSA Time slot assigner Tx Transmit UART Universal asynchronous receiver transmitter UPM User programmable machine USART Universal synchronous asynchronous receiver transmitter Table V 1 Acronyms and Abbreviated Terms continued Term Meaning ...

Page 554: ...MPC885 PowerQUICC Family Reference Manual Rev 2 V 6 Freescale Semiconductor ...

Page 555: ...trolling DMA The CPM supports multiple communications channels and protocols and it has flexible firmware programmability The CPM frees the core of many computational tasks in the following ways By reducing the interrupt rate The core is interrupted only upon frame reception or transmission instead of on a per character basis By implementing some of the OSI layer 2 processing which provides more c...

Page 556: ...unications channels Two independent DMA channels for memory to memory transfers or interfacing external peripherals RISC timer tables Three full duplex serial communications controllers SCCs that support the following UART protocol asynchronous or synchronous HDLC protocol AppleTalk protocol 4 Baud Rate Generators USB U Bus SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C Interrupt Controller 4 Timers Parallel I ...

Page 557: ... interface SPI support for master or slave modes Universal Serial Bus USB Supports operation as a USB function endpoint a USB host controller or both for testing purposes loop back diagnostics Inter integrated circuit I2 C bus controller Parallel interface port supporting Centronics A serial interface SI with a time slot assigner TSA that supports multiplexing of data from SCCs and SMCs onto two t...

Page 558: ... from the RISC timer tables described in Section 18 8 The RISC Timer Table Each timer consists of the following Timer mode register TMR Timer capture register TCR Timer counter TCN Timer reference register TRR Timer event register TER Timer global configuration register TGCR EEST MC68160 T1 E1 Xceiver Embedded MPC8xx Core SCC3 USB 32 Bit RISC RS 422 S T U Xceiver TDMa TDMb Time Slot Assigner PCMCI...

Page 559: ...form 32 bit timers Free run and restart modes Timer 1 is used with the PCMCIA speaker inputs to generate alerts on SPKROUT 17 2 2 CPM Timer Operation The following subsections describe the timer operation The timer mode registers TMRx and the timer global configuration register TGCR mentioned in this section are described in Section 17 2 3 CPM Timer Register Set Timer Clock Generator Capture Detec...

Page 560: ...nues or begins again When the reference value is reached the corresponding TERx event bit is set and an interrupt is issued if TMRx ORI 1 Also when the reference value is reached the timers can output a signal on their timer output pins TOUT 1 4 The output signal can be programmed to be an active low pulse or a toggle of the current output as selected by TMRx OM the output mode bit 17 2 2 3 Timer ...

Page 561: ... timers into cascaded mode as shown in Figure 17 4 Figure 17 4 Timer Cascaded Mode Block Diagram If TGCR CASx is set the two corresponding timers function as a 32 bit timer with a 32 bit TRR TCR and TCN In this case the mode registers TMR1 and TMR3 are ignored and TMR2 and TMR4 define the mode Similarly the capture is controlled by TIN2 or TIN4 and interrupts are generated by TER2 or TER4 In casca...

Page 562: ... 6 10 14 STPx Stop timer x 0 Normal operation 1 Stop the timer This bit stops all clocks to the timer except the U bus interface clock allowing the timer registers to be read or written The clocks to the timer remain inactive until this bit is cleared or a hardware reset occurs 3 7 11 15 RSTx Reset timer x The associated TMRx and TRRx registers should be initialized before enabling the timer with ...

Page 563: ... on capture event 10 OM Output mode 0 Active low pulse on TOUTx for one timer input clock cycle as defined by ICLK Thus TOUTx may be low for one general system clock period one general system clock 16 period or one TINx clock cycle period Changes to TOUTx occur on the falling edge of the system clock 1 Toggle TOUTx Changes to TOUTx occur on the falling edge of the system clock 11 ORI Output refere...

Page 564: ...s TCN1 TCN4 Each timer counter register TCN1 TCN4 shown in Figure 17 9 is an up counter A read cycle to TCN1 TCN4 yields the current value of the timer but does not affect the counting operation A write cycle to TCN1 TCN4 sets the register to the written value thus causing its corresponding prescaler TMRx PS to be reset Note that the counter registers may not be updated correctly if a write is mad...

Page 565: ...ould be generated every 250 system clocks 1 Set TGCR 0x0000 to reset timer 2 2 Set TMR2 0x001A to set the prescaler to divide by 1 and the clock source to the general system clock This value also enables an interrupt when the timer reaches the reference count and immediately clears restarts the TCN for the next interrupt 3 Set TCN2 0x0000 to clear the timer 2 counter default 4 Set TRR2 0x00FA to i...

Page 566: ...nce count and immediately clears the TCN for the next interrupt 3 Set TMR1 0x0000 Enable timer 1 to use the timer 2 output as its input TMR1 ICLK 0b00 4 Set TCN1 0x0000 and TCN2 0x0000 Initialize the count of the combined timers 1 and 2 to zero TMR1 default by using one 32 bit data move to TCN1 5 Set TRR1 0x0000 and TRR2 0x00FA Initialize the reference value of the combined timers 1 and 2 to 250 b...

Page 567: ... and contains an internal timer used to implement additional software timers The CP s architecture and instruction set are optimized for data communications and processing required by many wire line and wireless communications standards 18 1 Features The following lists the CP s main features Performs lower layer protocol processing for communication channels Protocol processing microcode routines...

Page 568: ... time 18 3 Communicating with the Peripherals The CP uses the peripheral bus to communicate with the peripherals The universal serial bus USB and the serial communications controllers SCCs have separate receive and transmit FIFOs The USB and SCC2 SCC4 receive and transmit FIFOs are 16 bytes each The serial management controllers SMCs serial peripheral interface SPI and I2 C are all double buffered...

Page 569: ...sued to the CPCR 4 IDMA emulation DREQ0 default option 1 1 1 See the RCCR DRQP description in Section 18 6 1 RISC Controller Configuration Register RCCR 5 IDMA emulation DREQ1 default option 1 1 6 USB Rx 7 USB Tx 8 SCC2 Rx 9 SCC2 Tx 10 SCC3 Rx 11 SCC3 Tx 12 SCC4 Rx 13 SCC4 Tx 14 IDMA emulation DREQ0 option 2 1 15 IDMA emulation DREQ1 option 2 1 16 SMC1 Rx 17 SMC1 Tx 18 SMC2 Rx 19 SMC2 Tx 20 SPI Rx...

Page 570: ...code REV_NUMs see the website at http www freescale com 18 5 CPM Configuration Register CPMCFG The CPM Configuration Register CPMCFG has been added to enable AAL2 functionality and APC flux compensation In the future this register may be used for additional purposes Figure 18 2 shows the CPMCFG register Table 18 2 CP Microcode Revision Number Offset1 1 Offset from the base of the miscellaneous par...

Page 571: ...rnal timer It also sets the IDMA request modes and priority This register is affected by HRESET but is not affected by SRESET Table 18 4 describes the RCCR fields Table 18 3 CPM Configuration Register CPMCFG Bit Settings Bits Name Description 0 15 Reserved should be cleared 16 AAL2 AAL2 Enable 0 AAL2 disabled 1 AAL2 enabled 17 30 Reserved should be cleared 31 APC APC Flux Compensation 0 Disabled 1...

Page 572: ...DMA Interface Signals DREQ and SDACK 0 DREQ0 is edge sensitive 1 DREQ0 is level sensitive 10 11 DRQP IDMA emulation request priority Controls the priority of the external request signals that relate to the serial channels See Section 18 3 Communicating with the Peripherals 00 IDMA requests have priority over the SCCs and USB 01 IDMA requests have priority immediately following the SCCs option 2 10...

Page 573: ...nother CP command The core can however issue the CP reset command CPCR 0x8001 at any time regardless of FLG Note that the CPCR has a different bit format for ATM operations see Section 39 4 Port to Port PTP Switching 0 1 7 Field ERAM4K Reset 0000_0000_0000_0000 R W R W Addr 0x9C7 Figure 18 4 RISC Microcode Development Support Control Register RMDS Table 18 5 RMDS Field Descriptions Bits Name Descr...

Page 574: ...issued 1 Reset issued 1 3 Reserved Should be cleared 4 7 OPCODE Operation code for the core issued CP commands See Table 18 8 8 11 CH_NUM Channel number Defines the specific sub block on which the command is to operate Some sub blocks share channel number encodings if their commands are mutually exclusive 0000 USB 0001 I2C IDMA1 001x Reserved 0100 SCC2 0101 SPI IDMA2 RISC timers 011x Reserved 1000...

Page 575: ...red when switching protocols INIT RX PARAMS Initialize receive parameters Initializes the CP s temporary Rx parameters in the parameter RAM to the user defined reset values often required when switching protocols INIT TX PARAMS Initialize transmit parameters Initializes the CP s temporary Tx parameters in the parameter RAM to the user defined reset values often required when switching protocols EN...

Page 576: ...rt transmission After STOP TX or GRACEFUL STOP TX RESTART TX starts the transmitter which begins polling the R bit of the current BD CLOSE RX BD Closes the current RxBD in mid reception reception continues using the next available BD Use CLOSE RX BD to access the data buffer without waiting for the SCC to finish filling it INIT IDMA Initialize IDMA transfers Initializes the IDMA internal CP state ...

Page 577: ...ccesses with at least one write operation the CP is delayed by one clock When the core or SDMA channel access the dual port RAM the data and address are passed through the U bus The CP can fetch data from the entire dual port RAM and microcode instructions from portions of the system RAM The controller and sub block parameters of the parameter RAM and the optional microcode packages in system RAM ...

Page 578: ...e used for microcode an additional 256 byte extension of system RAM is also locked When all four 512 byte blocks are used for microcode an additional 512 byte extension of system RAM is locked See the darker shaded areas of Figure 18 7 In addition to RCCR ERAM RMDS ERAM4K enable RAM microcode at offset 4K affects the system RAM memory configuration for microcode packages Setting RMDS ERAM4K locks ...

Page 579: ... C and IDMA channel operation Table 18 10 shows the parameter RAM memory map Table 18 9 General BD Structure BD Base Offset Field 0x00 Status and control 0x02 Data length 0x04 High order of buffer pointer 0x06 Low order of buffer pointer Table 18 10 Parameter RAM Memory Map Offset from IMMR Page Offset from DPRAM_base Controller Peripheral 0x3C00 1 0x1C00 0x1C7F USB 0x1C80 0x1CAF I2 C default area...

Page 580: ...channels Three timer modes one shot restart and PWM Maskable interrupt on timer expiration Programmable timer resolutions as low as 41 µs at 25 MHz Maximum timeout periods of 172 seconds at 25 MHz Continuously updated reference counter RISC timer table operations are based on a tick in the CP internal timer that is programmed in the RCCR see Section 18 6 1 RISC Controller Configuration Register RC...

Page 581: ...he next scan tick If SET TIMER is issued the CP makes the appropriate modifications to the timer table and parameter RAM but does not scan the timer table until the next tick of the internal CP timer Using SET TIMER properly synchronizes the timer table modifications to the execution of the CP 18 8 2 The SET TIMER Command Issued to the CP command register CPCR the SET TIMER command is used to enab...

Page 582: ...gister Only the CP uses this register to store the mode of the timer one shot 0 or restart 1 Do not modify this register directly it is modified indirectly via TM_CMD and the SET TIMER command 0x06 R_TMV Hword RISC timer valid register Only the CP uses this register to determine whether a timer is currently enabled If the corresponding timer is enabled a bit is 1 Do not modify this register direct...

Page 583: ... bit is set the timer s RTER interrupt is enabled If an RTMR bit is cleared the corresponding interrupt in the RTER is masked This register is affected by HRESET and SRESET The RISC timer table bit in the CPM interrupt mask register CIMR RTT described in Section 35 5 3 CPM Interrupt Mask Register acts as a global RISC timer interrupt mask Clearing CIMR RTT masks all RISC timer interrupts regardles...

Page 584: ...can interval for the entire timer table The timer enable bit RCCR TIME is normally set at this time however it can be set later if all RISC timers must be synchronized 2 Determine the maximum number of timers to be located in the timer table Configure TM_BASE to point to a location in the dual port RAM with 4 N bytes available where N is the number of timers used If N is less than 16 use timer 0 t...

Page 585: ...r so the RISC timers generate a system interrupt Initialize the CPM interrupt configuration register 7 Write 0xC000_0EE6 to TM_CMD This enables RISC timer 0 to timeout after 3 814 decimal ticks The timer automatically restarts after it times out 8 Write 0x0851 to the CPCR to issue SET TIMER 9 Set RCCR TIME to start RISC timer table scanning 18 8 7 RISC Timer Interrupt Handling The following sequen...

Page 586: ...mers to increment once every tick The general purpose timer should be free running and have a timeout of 65 536 5 After a few hours of operation compare the general purpose timer to the current count of RISC timer 15 If the difference between them exceeds two ticks the CP has during some scan tick interval exceeded the 96 utilization level Note that when comparing timer counts the general purpose ...

Page 587: ...emulates two general purpose independent DMA IDMA channels for memory memory and peripheral memory transfers using the two physical SDMA channels 19 1 SDMA Channels Data from the CP FECs and security engine can be routed to external memory path 1 or the internal dual port RAM path 2 as shown in Figure 19 1 On a path 1 access the SDMA channel must acquire both the U bus and the external system bus ...

Page 588: ...rror occurs when the SDMA conducts an access the CP generates a unique interrupt in the SDMA status register SDSR The interrupt service routine reads the SDMA address register SDAR to determine the address that the bus error occurred on The individual channel that caused the bus error can be found by reading the Rx and Tx internal data pointers from the protocol specific parameter RAM of the seria...

Page 589: ...protocols an SDMA writes each character to memory as it arrives without waiting for the next character and always reads using 16 bit half word transfers A transfer may take multiple bus cycles if the memory provides a less than 32 bit port size An SDMA uses back to back bus cycles for the entire transfer 4 word bursts 32 bit reads and 8 16 or 32 bit writes before relinquishing the bus For example ...

Page 590: ...guration Register SDCR The SDMA configuration register SDCR configures all 22 virtual SDMA channels It controls the channels U bus priority level and freeze signal FRZ behavior It is always read write in supervisor mode even though writing to the SDCR is not recommended unless the CPM is disabled This register is affected by HRESET but is not affected by SRESET Figure 19 3 shows the register forma...

Page 591: ...e corresponding interrupt is masked Reset clears SDMR Its internal address IMMR offset is 0x90C This register is affected by HRESET and SRESET Table 19 2 SDCR Bit Settings Bits Name Description 0 16 Reserved should be cleared 17 FRZ Freeze Recognize or ignore the freeze signal If configured to respond to the freeze signal the SDMA controller negates BR until freeze is negated or a reset occurs 00 ...

Page 592: ...tion 19 3 8 IDMA Transfers Dual Address and Single Address The IDMA controller supports two buffer handling modes auto buffering and buffer chaining In buffer chaining an IDMA moves a connected series of BDs called a chain without interruption Auto buffering allows a buffer chain to be repeatedly transferred in a loop without user intervention See Section 19 3 4 2 Auto Buffering and Buffer Chainin...

Page 593: ...e CP initializes SAPR to the BD s source buffer pointer and increments it automatically if the source is memory DCMR S D 0bx0 0x08 DAPR Word Destination data pointer internal use Points to the next destination byte to be written The CP initializes DAPR to the BD s destination buffer pointer and increments it automatically if the destination is memory DCMR S D 0b0x 0x0C IBPTR Hword Current IDMA BD ...

Page 594: ...Determines the operand transfer size per DREQx assertion for peripheral memory transfers but not for memory memory transfers For memory memory transfers the size is determined only by address alignment and the amount of data remaining to be transferred 00 Word length 01 Half word length 10 Byte length 11 Reserved Note that the memory port size is transparent to the IDMA The SIU emulates a 32 bit p...

Page 595: ... s internal address IMMR offset is 0x914 IDMR2 s is 0x91C These registers are affected by HRESET and SRESET 19 3 4 IDMA Buffer Descriptors BD An IDMA buffer descriptor contains the specific transfer information needed for its buffer IDMA BDs contain a status and control field the function code registers the buffer length and the source and destination buffer pointers The BDs are grouped together i...

Page 596: ...ust be greater than zero The word at offset 8 points to the beginning of the source buffer in internal or external memory When the source is a peripheral this field is ignored in single address mode In dual address mode this field contains the peripheral address The word at offset 0xC points to the beginning of the destination buffer in internal or external memory When the destination is a periphe...

Page 597: ...tion is detected the CP clears the V bit 1 Reserved 2 W Wrap Marks the end of the BD table 0 Not the last descriptor in the BD table 1 Last descriptor in the BD table After this descriptor has been processed the CP wraps the current BD pointer IBPTR back to the top of the BD table IBASE 3 I Interrupt Enable the maskable auxiliary done AD interrupt 0 IDSR AD is not flagged after this BD is processe...

Page 598: ...g the CPM invalidates the current BD after processing to allow the user the core to safely manipulate the contents of the buffer and modify its BD Note that the V bit behavior is the only difference between auto buffering and buffer chaining auto buffering can be thought of as continuous buffer chaining One use of auto buffering is for continuous monitoring of an external instrument such as an A D...

Page 599: ... parameter RAM programs the physical SDMA channel and provides addressing and bus control The termination phase begins when the transfer byte count reaches zero or a bus error occurs The CPM then interrupts the core unless masked and the current BD pointer moves to the next BD in the table To begin a block transfer initialize the IDMA registers and build the IDMA BDs with information describing th...

Page 600: ...utput To use a general purpose I O line follow these steps 1 Externally connect a general purpose output line to DREQ 2 Set RCCR DRnM level sensitive 3 Drive the output low when the request generation should begin The IDMA controller continuously requests the bus until the current buffer chain is completely transferred The transfer terminates with an out of buffers error IDSR OB To use a general p...

Page 601: ...d DREQ1 respectively see Section 34 4 1 5 Port C Interrupt Control Register PCINT In edge sensitive mode an IDMA channel moves one data operand per request DREQ is sampled at each rising edge of the clock When IDMA detects a request on DREQ the request is considered pending and remains pending until it is processed Subsequent requests on DREQ are ignored until the pending request is acknowledged 1...

Page 602: ...he most efficient packing algorithm possible to perform the transfer in the least number of bus cycles 19 3 8 2 Single Address Single Cycle Transfer Fly By Each IDMA channel can be independently programmed to provide single address or fly by transfers The IDMA channel bypasses or flies by internal storage since the transfer occurs directly between a device and memory DCMR S D controls the directio...

Page 603: ...gram Single Address Peripheral Write Externally Generated TA Figure 19 11 SDACK Timing Diagram Single Address Peripheral Write Internally Generated TA CLKOUT Address TS R W Data TA SDACK THOLD TPHOLD TDELAY T3 T1 T3 T1 T3 T1 T3 T1 T3 T1 T3 TSETUP CLKOUT Address TS R W Data TA SDACK THOLD TPHOLD TDELAY T3 T1 T3 T1 T3 T1 T3 T1 T3 T1 T3 TSETUP ...

Page 604: ...following are ways to externally determine if IDMA is executing a bus cycle Monitor the AT signals of the SDMA channels for the user defined function code AT0 is always high for a DMA access Monitor SDACK which shows accesses to the peripheral SDACK activates on either the source or destination bus cycles depending on DCMR S D Note that if Ethernet is running this method does not work since SCCs i...

Page 605: ...cle flags an error in SDSR and interrupts the core if not masked by SDMR The IDMA waits for the CPM to reset before starting any new bus cycles Note that data read from the source into internal storage is lost Program control passes to the handler at the machine check interrupt vector 0x00200 The machine check and system reset interrupts are described in Chapter 6 Exceptions Note that the source o...

Page 606: ...SDMA Channels and IDMA Emulation MPC885 PowerQUICC Family Reference Manual Rev 2 19 20 Freescale Semiconductor ...

Page 607: ...nterface is accomplished through a set of TDM pins and a time slot assigner TSA Two independent TDM channels TDMa and TDMb are available The user programs the TSA to route data from the TDM data stream to and from the SCCs and SMCs The TSA also provides external strobe signals L1ST 1 4 which can be used to enable external devices such as codecs to insert or take data from the TDM data stream An ex...

Page 608: ...ler QMC see the Supplement QUICC Multichannel Controller Up to 64 independent communication channels Arbitrary mapping of any of 0 63 channels to any of 0 63 TDM time slots Time Slot Assigner R clocks T clocks R clocks T clocks R sync T sync TDM a b Pins Strobes U Bus Route SI RAM Tx Rx RAM Control Mode Register TDM a b Tx Rx Tx Rx Command Register Status Register Clock Route MUX SMC1 Pins SMC1 No...

Page 609: ...enation of any not necessarily consecutive time slots to channels independently for receive transmit Supports H0 H11 and H12 ISDN channels Allows dynamic allocation of channels Ability to connect the TDM channels independently Each TDM can be one of the following T1 or CEPT line Pulse code modulation highway PCM Integrated services digital network ISDN primary rate ISDN basic rate using an interch...

Page 610: ...k IDL and general circuit interface GCI also known as IOM 2 are supported With two TDM channels the TSA can simultaneously support two different TDM frame formats TSA programming is independent of the protocol used by the SCC or SMC The SCCs and SMCs can be programmed for any synchronous protocol without affecting TSA programming The TSA simply routes programmed portions of the received data frame...

Page 611: ...lex TDM Example Unique Routing Slot 1 SCC2 Slot 2 SMC1 TDM Tx TDM Rx 1 TDM Clk 1 TDM Sync SMC1 SCC2 TDM TSA Even More Complex TDM Example Multiple Time Slots per Channel with Varying Sizes of Time Slots SCC2 SMC1 SCC2 SCC2 NOTE The two shaded areas of SCC2 Rx are received as one high speed data stream by the SCC2 and stored together in the same data buffers TDM Tx TDM Rx TDM Tx Clk TDM Tx Sync SMC...

Page 612: ... in a multi transmitter system Note that the open drain option on the TXDx pins to support multiple transmitters is programmed in the parallel I O block see Chapter 34 Parallel I O Ports The strobes can also generate output waveforms for such applications as stepper motor control The TSA routing is programmed in a 512 byte core accessible SI RAM located in the internal register section of the MPC8...

Page 613: ...DMx see Section 20 2 4 2 SI Mode Register SIMODE Loopback mode can also be programmed on a time slot basis in an individual SI RAM entry see Section 20 2 3 7 Programming the SI RAM Note that loopback operation requires that the receive and transmit sections of the TDM use common clock and synchronization signals The maximum external serial clock that may be an input to the TSA is SYNCCLK 2 5 If an...

Page 614: ...and SMC routing information for the TDM channels The SI RAM totals 128 32 bit entries 64 entries each for receive and transmit routing Representing one time slot an entry controls from 1 to 16 bits bytes and up to four strobe pins all active high The TDM channel options with their corresponding SI RAM partitioning follow A single TDM channel with static routing SI RAM is divided into Rx and Tx par...

Page 615: ...hen the TSA is configured for static frames 1 SCC and SMC connections to the TSA must be disabled 2 The SI configuration can be modified 3 SCC and SMC connections to the TSA must be reenabled 20 2 3 2 One TDM Channel with Static Frames In an SI configuration using one multiplexed channel with static frames shown in Figure 20 5 there are 64 entries in the SI RAM for Rx data strobe routing and 64 en...

Page 616: ...CMR CSRRx CSRTx when the swap takes effect These steps can be repeated with the former current route RAM always becoming the new shadow RAM and vice versa When using only one channel TDMa with dynamic changes as in Figure 20 7 the initial current route RAM byte addresses are as follows 0 127 Rxa route 256 383 Txa route The shadow RAMs are at addresses 128 255 Rxa route 384 511 Txa route When using...

Page 617: ...he second part of the RAM CSRxn 0 current route RAMs 256 319 320 383 384 447 448 511 RAM Address CSRTa 0 CSRRb 0 CSRTb 0 CSRRa 1 CSRTa 1 CSRRb 1 CSRTb 1 CSRRa 0 CSRTa 0 CSRRb 0 CSRTb 0 L1TCLKb L1TSYNCb 16 Txb Shadow 16 Txa 16 Txb Route Route Framing Signals L1TCLKa L1TSYNCa 16 Txa Shadow RAM Address CSRxn L1RCLKb L1RSYNCb 16 Rxb Shadow 16 Rxa 16 Rxb Route Route Framing Signals L1RCLKa L1RSYNCa 16 ...

Page 618: ...th Dynamic Frames In an SI configuration using both TDM channels with dynamic frames each channel has 16 entries apiece for Tx and Rx data strobe routing as shown in Figure 20 9 One partition is the current route RAM the other is shadow RAM that can be safely reprogrammed After programming the shadow RAM the user sets SICMR CSRx When the next frame sync arrives the SI swaps the current route RAM w...

Page 619: ... duration of this entry Note that erratic results may occur if the Tx and Rx sections of the TDM do not use a common clock source 2 5 SSELn Strobe select 1 4 The four strobes L1ST 1 4 can be assigned to the Rx or the Tx RAM and asserted negated in sync with the corresponding L1RCLKx or L1TCLKx Using active high logic each SSELn will be the value of the corresponding strobe during this time slot Mu...

Page 620: ...iet time slot is used 7 9 CSEL Channel select Indicates which channel the time slot is routed to 000 This time slot is not used Tx data signal is three stated Rx data signal is ignored 001 This time slot is not used 010 SCC2 011 SCC3 100 SCC4 101 SMC1 110 SMC2 111 This time slot is not used Also used in SCIT mode to indicate the D channel grant bit 10 13 CNT Count The number of bits bytes the unit...

Page 621: ... the IDL requires the same routing for both receiving and sending the above entries should be written to both the Rx and Tx route RAM Set SIMODE CRTx common receive transmit to instruct the TSA to use the same clock and sync for both sets of SI RAM entries For examples showing register programming see Section 20 2 5 2 Programming the IDL Interface and Section 20 2 6 3 GCI Interface SCIT Mode Progr...

Page 622: ...should be cleared 4 ENb Enable TDMb 0 TDMb is disabled SI RAM and TDM routing are in a state of reset all other SI functions still operate 1 TDMb is enabled 5 ENa Enable TDMa 0 TDMa is disabled SI RAM and TDM routing are in a state of reset all other SI functions still operate 1 TDMa is enabled 6 7 RDM RAM division mode Defines the SI RAM partitioning based on the number of TDM channels supported ...

Page 623: ...de SMCx can take its Tx and Rx clocks from a baud rate generator or one of four pins from the bank of clocks However Tx and Rx clocks must be common when connected to the NMSI 000 BRG1 001 BRG2 010 BRG3 011 BRG4 100 CLK1 for SMC1 CLK5 for SMC2 101 CLK2 for SMC1 CLK6 for SMC2 110 CLK3 for SMC1 CLK7 for SMC2 111 CLK4 for SMC1 CLK8 for SMC2 4 5 20 21 SDMx SI diagnostic mode for TDMa b In modes 01 10 ...

Page 624: ...nd L1TSYNCx for framing 1 Common pins Both the transmit and receive section use L1RCLKx as the clock pin of the channel and L1RSYNCx as the sync pin Use for IDL and GCI Useful when the transmit and receive section of a given TDM share clock and sync signals L1TCLKx and L1TSYNCx can be used for their alternate functions 10 26 STZx Set L1TXDx to zero for TDMa b 0 Normal operation 1 L1TXDx is cleared...

Page 625: ...ess controls transmission on the D channel See Section 20 2 5 2 Programming the IDL Interface Note that if GMa 1 then the RTS4 signal on ports B and C functions as L1RQa The RTS4 function is still available on port D Note that if GMb 1 then the RTS3 signal on ports B and C functions as L1RQb The RTS3 function is still available on port D 14 15 30 31 TFSDx Transmit frame sync delay for TDMa b Deter...

Page 626: ...ay of one bit Figure 20 16 Falling Edge FE Effect When CE 1 and xFSD 01 Figure 20 17 Falling Edge FE Effect When CE 0 and xFSD 01 L1TxD Rx Sampled Here L1ST L1SYNC L1SYNC L1CLK Bit 0 On Bit 0 L1ST Driven from Clock High for Both FE Settings xFSD 01 FE 0 FE 1 CE 1 L1TXD Rx Sampled Here L1ST L1SYNC L1SYNC L1CLK Bit 0 On Bit 0 L1ST is Driven from Clock Low FE 0 FE 1 CE 0 in Both the FE Settings xFSD ...

Page 627: ...ect When CE 1 and xFSD 00 L1TXD L1ST L1SYNC L1CLK Bit 0 On Bit 0 xFSD 00 FE 0 CE 1 The L1ST is Driven from Sync Data is Driven from Clock Low L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 0 L1ST is Driven from Clock High L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 1 Both Data Bit 0 and L1ST are Driven from Sync Rx Sampled Here Rx Sampled Here L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 1 L1ST and Data Bit 0 is Driven from ...

Page 628: ...our baud rate generators or an input from the bank of clock pins The SICR also connects the SCCs to the TSA and enables the grant mechanism chosen in SIMODE L1TXD L1ST L1SYNC L1CLK Bit 0 On Bit 0 xFSD 00 FE 1 CE 0 The L1ST is Driven from Sync Data is Driven From Clock High L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 1 L1ST is Driven from Clock Low L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 0 Both the Data and L1...

Page 629: ...MODE GMx 1 9 17 SCx SCCx connection 0 SCCx is not connected to the TSA It is either connected directly to the NMSI pins or is not used The choice of general purpose I O port versus SCCx functionality is made in the parallel I O control register see Chapter 34 Parallel I O Ports 1 SCCx is connected to the multiplexed SI NMSIx receive pins can be used for other purposes 24 25 Reserved should be clea...

Page 630: ...ue of SISTR is valid only when the corresponding SICMR bit is clear This register is affected by HRESET but is not affected by SRESET Table 20 8 describes the SISTR fields 0 1 2 3 4 7 Field CSRRa CSRTa CSRRb CSRTb Reset 0 R W R W Addr 0xAE7 Figure 20 21 SI Command Register SICMR Table 20 7 SICMR Field Descriptions Bits Name Description 0 2 CSRRx Change shadow RAM for TDMx receiver transmitter Set ...

Page 631: ...IRP changes on serial clock transitions Before acting on the information in this register perform two reads to verify the same value is returned One of the four strobes can be connected externally to an interrupt pin to generate an interrupt on a particular SI RAM entry to start or stop TSA execution The pointers in SIRP indicate the SI RAM entry word offset that is in progress Table 20 8 SISTR Fi...

Page 632: ...t in the fifth entry the pointer reflects values 0 4 When the SI processes the fifth the pointer returns to 0 Pointer values are described in Table 20 10 and are based on SIGMR RDM Table 20 10 SIRP Pointer Values RDM Configuration 00 RaPTR TaPTR point to the first 32 entries and RbPTR TbPTR point to the second 32 entries RaPTR RbPTR and TaPTR TbPTR point to the active Rx and Tx entries respectivel...

Page 633: ...y and has only one function RaPTR points to the active Rxa entry and RbPTR points to the active Rxb entry TaPTR points to the active Txa entry and TbPTR points to the active Txb entry 11 Each pointer is used continuously The section of SI RAM it points to depends on whether its value is in the first half 0 15 or the second half 16 31 RaPTR points to the active Rxa entry If RaPTR 0 15 the current r...

Page 634: ...lock Input to the MPC885 L1RSYNCx IDL sync signal Input to the MPC885 This signal indicates that the clock periods following the pulse designate the IDL frame L1RXDx IDL receive data Input to the MPC885 Valid only for bits supported by the IDL ignored for other signals that may be present L1TXDx IDL transmit data Output from the MPC885 Valid only for bits supported by the IDL otherwise three state...

Page 635: ...e physical layer device monitors the physical layer bus for activity on the D channel and indicates that the channel is free by asserting L1GRx The MPC885 samples L1GRx when the IDL sync signal L1RSYNCx is asserted If L1GRx is asserted the MPC885 sends the first zero of the opening flag in the first bit of the D channel If a collision is detected on the D channel the physical layer device negates ...

Page 636: ...rocedure for an IDL bus on the second TDM channel For example based on the same 10 bit format as in Section 20 2 3 8 SI RAM Programming Example implement an IDL bus using SCC2 SCC3 and SMC2 connected to the TDM channel as follows 1 Program both the Rx and Tx sections of the SI RAM as in Table 20 11 Write unused entries with 0x0001_0000 2 SIMODE 0x8000_0145 Only TDMa is used SMC2 is connected to th...

Page 637: ...h up to eight physical layer devices multiplex their GCI channels In the GCI bus the clock rate is twice the data rate The SI divides the input clock by two to produce the data clock The MPC885 also has data strobe lines and the 1 data rate clock L1CLKOx outputs used as an interface for devices that do not support the GCI bus Shown in Figure 20 27 the GCI signals for each Tx and Rx channel are as ...

Page 638: ...ata to send on the D channel it checks an SCIT bus bit that is marked with a special route code usually bit 4 of C I channel 2 The physical layer device monitors the physical layer bus for activity on the D channel and indicates on this bit that the channel is free If a collision is detected on the D channel the physical layer device drives bit 4 of C I channel 2 to logic high The MPC885 then abor...

Page 639: ... program SICR GRx to transfer the D channel grant to the supporting SCC The received bit grant should be marked by programming the CSEL channel select bits of the SI RAM to 0b111 for an internal assertion of a strobe This bit is sampled by the SI and transferred to the D channel SCC as the grant The grant is generally bit 4 of the C I in channel 2 of the GCI bus but any bit slot can be selected in...

Page 640: ...de by consulting the pinout in Chapter 2 Memory Map The clocks that are provided to the SCCs and SMCs are derived from four internal baud rate generators and eight external CLK pins There are two main advantages to this bank of clocks approach First an SCC or SMC is not forced to choose its clock from a predefined pin or baud rate generator Second if a group of receivers and transmitters need the ...

Page 641: ...RG1 BRG4 CLK1 CLK4 RCLK2 BRG1 BRG4 CLK1 CLK4 RTS2 CTS2 CD2 The SCC3 in NMSI mode has its own set of modem control signals TXD3 RXD3 TCLK3 BRG1 BRG4 CLK5 CLK8 RCLK3 BRG1 BRG4 CLK5 CLK8 RTS3 CTS3 CD3 SMC1 SMC2 SCC2 Rx SCC2 Tx BRG1 BRG2 BRG3 BRG4 CLK1 CLK2 SMCLK1 RCLK1 TCLK1 SMCLK2 RCLK2 TCLK2 BRGO1 BRGO2 BRGO3 BRGO4 Bank of Clocks Selection Logic SCC clock source selected in SICR SMC clock source se...

Page 642: ...s can be used for other functions or configured for parallel I O 20 4 Baud Rate Generators BRGs The CPM contains four independent identical baud rate generators BRG that can be used with the SCCs and SMCs The clocks produced by the BRGs are sent to the bank of clocks selection logic where they can be routed to the SCCs or SMCs In addition the output of a BRG can be routed to a pin to be used exter...

Page 643: ... periods The prescaler output is sent internally to the bank of clocks and can also be output externally on BRGOn through either the port A or port B parallel I O If the BRG divides the clock by an even value the transitions of BRGOn always occur on the falling edge of the source clock If the divide factor is odd the transitions alternate between the falling and rising edges of the source clock Ad...

Page 644: ...e only if BRGO is connected to the corresponding parallel I O pin 0 Enable the BRG 1 Reset the BRG software reset 15 EN Enable BRG count Used to dynamically stop the BRG from counting useful for low power modes 0 Stop all clocks to the BRG 1 Enable clocks to the BRG 16 17 EXTC External clock source Selects the BRG input clock 00 BRGCLK internal clock generated by the clock synthesizer in the SIU 0...

Page 645: ...re should then check for other characters such as t or T and program the preferred parity mode in the UART s protocol specific mode register PSMR Note that the SCC associated with this BRG must be programmed to UART mode and select the 16 option for TDCR and RDCR in the general SCC mode register GSMR_L Input frequencies such as 1 8432 3 68 7 36 and 14 72 MHz should be used The SCC performing the a...

Page 646: ...d to be 16 the baud rate that is GSMR_L TDCR GSMR_L RDCR 0b10 For synchronous communication the internal clock is identical to the baud rate output To get the preferred rate select the system clock according to the following sync baud rate BRGCLK or CLK2 or CLK6 1 or 16 according to BRGCx DIV16 clock divider 1 For example to get a rate of 64 kbps the system clock can be 24 96 MHz DIV16 0 and the c...

Page 647: ...urthermore the choice of protocol is independent from the choice of interface An SCC is described in terms of the protocol it runs When an SCC is programmed to a certain protocol or mode it implements functionality that corresponds to parts of the protocol s link layer layer 2 of the OSI reference model Many SCC functions are common to protocols of the following controllers UART described in Chapt...

Page 648: ...RZ and NRZI are supported An SCC can be connected to its own set of pins on the MPC885 This configuration is called the non multiplexed serial interface NMSI and is described in Chapter 20 Serial Interface Using NMSI an SCC can support standard modem interface signals RTS CTS and CD through the port C pins and the CPM interrupt controller CPIC If required software and additional parallel I O lines...

Page 649: ... bytes per BD Deep FIFOs SCC2 SCC4 FIFOs are 16 bytes each Transmit on demand feature decreases time to frame transmission transmit latency Low FIFO latency option for send and receive in character oriented and totally transparent protocols Frame preamble options Full duplex operation Fully transparent option for one half of an SCC Rx Tx while another protocol executes on the other half Tx Rx exce...

Page 650: ...litch detection Clear GDE if the external serial clock exceeds the limits of glitch detection logic 6 25 MHz assuming a 25 MHz system clock if an internal BRG supplies the SCC clock or if external clocks are used and glitch detection matters less than power consumption 1 Glitches can be detected and reported as maskable interrupts in the SCC event register SCCE 16 17 TCRC Transparent CRC valid for...

Page 651: ...ransition while the Rx Tx clock is low at which time the transfer begins Useful for connecting MPC885 in transparent mode since the RTS of one MPC885 can connect directly to the CD CTS of another 25 TFL Transmit FIFO length 0 Normal operation SCC2 SCC4 Tx FIFOs are 16 bytes each 1 The Tx FIFO is 1 byte This option is used with character oriented protocols such as UART to ensure a minimum FIFO late...

Page 652: ... DSR 11 16 bit sync Also called BISYNC The receiver synchronizes on a 16 bit sync pattern stored in the DSR 30 RTSM RTS mode Determines whether flags or idles are to be sent Can be changed on the fly 0 Send idles between frames as defined by the protocol and the TEND bit RTS is negated between frames default 1 Send flags syncs between frames according to the protocol RTS is always asserted wheneve...

Page 653: ...ve data setup time for the external transceiver 4 5 TSNC Transmit sense Determines the amount of time the internal carrier sense signal stays active after the last transition on RXD indicating that the line is free For instance AppleTalk can use TSNC to avoid a spurious CS changed SCCE DCC interrupt that would otherwise occur during the frame sync sequence before the opening flags If RDCR is confi...

Page 654: ...es are sent 14 15 TDCR Transmitter receiver DPLL clock rate If the DPLL is not used choose 1 mode except in asynchronous UART mode where 8 16 or 32 must be chosen TDCR should match RDCR in most applications to allow the transmitter and receiver to use the same clock source If an application uses the DPLL the selection of TDCR RDCR depends on the encoding decoding If communication is synchronous se...

Page 655: ...nd CTS are ignored See the loopback bit description above for clocking requirements For TDM operation the diagnostic mode is selected by SIMODE SDMx see Section 20 2 4 2 SI Mode Register SIMODE 26 ENR Enable receive Enables the receiver hardware state machine for the SCC 0 The receiver is disabled and data in the Rx FIFO is lost If ENR is cleared during reception the receiver aborts the current ch...

Page 656: ...y HRESET and SRESET Figure 21 4 shows the sync fields 21 2 4 Transmit on Demand Register TODR In normal operation if no frame is being sent by an SCC the CP periodically polls the R bit of the next TxBD to see if a new frame buffer is requested Depending on the SCC configuration this polling occurs every 8 32 serial Tx clocks The transmit on demand option selected in the transmit on demand registe...

Page 657: ... the buffer closed In frame based protocols but not including SCC transparent operation this field contains the total frame length including CRC bytes Also if a received frame s length including CRC is an exact multiple of MRBLR the last BD holds no actual data but does contain the total frame length For a TxBD this is the number of bytes the controller should send from its buffer Normally this va...

Page 658: ...criptors buffers are usually put in external RAM especially if they are large Usually the internal U bus transfers data to the buffer The CP processes TxBDs in a straightforward manner Once the transmit side of an SCC is enabled it starts with the first BD in that SCC TxBD table Once the CP detects that the R bit is set in the TxBD it starts processing the buffer The CP detects that the BD is read...

Page 659: ...t from each SCC base area The protocol specific portions of the SCC parameter RAM are discussed in the specific protocol descriptions and the part that is common to all SCC protocols is shown in Table 21 5 Some parameter RAM values must be initialized before the SCC can be enabled Other values are initialized or written by the CP Once initialized most parameter RAM values do not need to be accesse...

Page 660: ...e value in the RBASE Although most applications do not need to write RBPTR it can be modified when the receiver is disabled or when no Rx buffer is in use 0x12 RCOUNT Hword Rx internal byte count 2 The Rx internal byte count is a down count value initialized with MRBLR and decremented with each byte written by the supporting SDMA channel 0x14 RTEMP Word Rx temp3 0x18 TSTATE Word Tx internal state3...

Page 661: ...is determined in the CPM interrupt configuration register CICR To allow interrupt handling for SCC specific events further event mask and status registers are provided within each SCC s internal memory map area see Table 21 7 Since interrupt events are protocol dependent event descriptions are found in the specific protocol chapters 0 2 3 4 5 7 Field BO AT 1 3 Reset 0000_0000 R W R W Addr SCCx bas...

Page 662: ... these signals are required 4 If the time slot assigner TSA is used the serial interface SI must be configured If the SCC is used in NMSI mode SICR must still be initialized 5 Write all GSMR bits except ENT or ENR Table 21 7 SCCx Event Mask and Status Registers Register IMMR Offset Description SCCEx 0xA30 SCC2 0xA50 SCC3 0xA70 SCC4 SCC event register This 16 bit register reports events recognized ...

Page 663: ... CTS and CD When GSMR_L DIAG is programmed to normal operation CD and CTS are controlled by the SCC In the following subsections it is assumed that GSMR_L TCI is zero implying normal transmit clock operation 21 4 4 1 Synchronous Protocols RTS is asserted when the SCC data is loaded into the Tx FIFO and a falling Tx clock occurs At this point the SCC starts sending data once appropriate conditions ...

Page 664: ...chronous Protocols If CTS is programmed to envelope data negating it during frame transmission causes a CTS lost error Negating CTS forces RTS high and Tx data to become idle If GSMR_H CTSS is zero the SCC must sample CTS before a CTS lost is recognized otherwise the negation of CTS immediately causes the CTS lost condition See Figure 21 11 1 GSMR_H CTSS 0 CTSP is a don t care TCLK TXD Last Bit of...

Page 665: ...ed on the rising Rx clock edge before data is received If GSMR_H CDS is 1 CD transitions cause data to be immediately gated into the receiver 1 GSMR_H CTSS 0 CTSP 0 or no CTS lost can occur TCLK TXD First Bit of Frame Data NOTE CTS Sampled Low Here 1 GSMR_H CTSS 1 CTSP 0 or no CTS lost can occur TCLK First Bit of Frame Data NOTE CTS Sampled High Here Data Forced High RTS Forced High Data Forced Hi...

Page 666: ...r In addition the UART protocol has an option for CTS flow control as described in Chapter 22 SCC UART Mode If CTS is already asserted when RTS is asserted transmission begins in two additional bit times If CTS is not already asserted when RTS is asserted and GSMR_H CTSS 0 transmission begins in three additional bit times If CTS is not already asserted when RTS is asserted and GSMR_H CTSS 1 transm...

Page 667: ... can be bypassed by selecting 1x mode for GSMR_L RDCR TDCR If the DPLL is bypassed only NRZ or NRZI encodings are available The DPLL must not be used when an SCC is programmed to Ethernet and is optional for other protocols Figure 21 13 shows the DPLL receiver block Figure 21 14 shows the transmitter block diagram Figure 21 13 DPLL Receiver Block Diagram DPLL HSRCLK RXD RINV TSNC EDGE RDCR RENC Re...

Page 668: ...begins DPLL operation While the counter is counting the DPLL watches the incoming data stream for transitions when one is detected the DPLL adjusts the count to produce an output clock that tracks incoming bits The DPLL has a carrier sense signal that indicates when data transfers are on RXD The carrier sense signal asserts as soon as a transition is detected on RXD it negates after the programmed...

Page 669: ...l baud rate generator may be up to 25 MHz on a 25 MHz MPC885 if the DPLL 8 16 or 32 option is used Note the 1 2 system clock serial clock ratio does not apply when the DPLL is used to recover the clock in the 8 16 or 32 modes Synchronization occurs internally after the DPLL generates the Rx clock Therefore even the fastest DPLL clock generation the 8 option easily meets the required 1 2 ratio cloc...

Page 670: ...at the beginning of the bit A zero is represented by a transition at the beginning of the bit and another transition at the center of the bit FM1 A one is represented by a transition at the beginning of the bit and another transition at the center of the bit A zero is represented by a transition only at the beginning of the bit Manchester A one is represented by a high to low transition at the cen...

Page 671: ...ially during prototype testing 21 4 7 Reconfiguring the SCCs The proper reconfiguration sequence must be followed for SCC parameters that cannot be changed dynamically For instance the internal baud rate generators allow on the fly changes but the DPLL related GSMR does not The steps in the following sections show how to disable reconfigure and re enable an SCC to ensure that buffers currently in ...

Page 672: ...nd 3 If the INIT RX PARAMETERS command was not issued in step 2 issue an ENTER HUNT MODE command 4 Set GSMR_L ENR Reception begins using the RxBD pointed to by RBPTR assuming the E bit is set 21 4 7 4 Reset Sequence for an SCC Receiver To reinitialize the SCC receiver to the state it was in after reset follow these steps 1 Clear GSMR_L ENR 2 Make any modifications then issue the INIT RX PARAMETERS...

Page 673: ...t idle condition Because the start bit is always a zero the receiver can detect when real data is once again on the line UART specifies an all zeros break character which ends a character transfer sequence The most popular protocol that uses asynchronous characters is the RS 232 standard which specifies baud rates handshaking protocols and mechanical electrical details Another popular format is RS...

Page 674: ...gnal and address bit It also supports synchronous operation where a clock internal or external must be provided with each bit received 22 1 Features The following list summarizes main features of an SCC UART controller Flexible message based data structure Implements synchronous and asynchronous UART Multidrop operation Receiver wake up on idle line or address bit Receive entire messages into buff...

Page 675: ...pped by the SCC A parity bit can be generated in transmission and checked during reception although it is not stored in the buffer its value can be inferred from the buffer s reporting mechanism Similarly the optional address bit is not stored in the transmit or receive buffer but is supplied in the BD itself Parity generation and checking includes the optional address bit GSMR_H RFW must be set f...

Page 676: ...1 start bit each break character consists of 10 zero bits 0x3E PAREC Hword User initialized 16 bit modulo 2 16 counters incremented by the CP PAREC counts received parity errors FRMEC counts received characters with framing errors NOSEC counts received characters with noise errors BRKEC counts break conditions on the signal A break condition can last for hundreds of bit times yet BRKEC is incremen...

Page 677: ...d Control character 1 8 These characters define the Rx control characters on which interrupts can be generated 0x52 CHARACTER2 Hword 0x54 CHARACTER3 Hword 0x56 CHARACTER4 Hword 0x58 CHARACTER5 Hword 0x5A CHARACTER6 Hword 0x5C CHARACTER7 Hword 0x5E CHARACTER8 Hword 0x60 RCCM Hword Receive control character mask Used to mask comparison of CHARACTER1 8 so classes of control characters can be defined ...

Page 678: ...cluding the TxBD can be modified TBPTR points to the next TxBD in the table Transmission begins once the R bit of the next BD is set and a RESTART TRANSMIT command is issued RESTART TRANSMIT Enables transmission The controller expects this command after it disables the channel in its PSMR after a STOP TRANSMIT command after a GRACEFUL STOP TRANSMIT command or after a transmitter error Transmission...

Page 679: ... be cleared The incoming address is checked against UADDR1 and UADDR2 When a match occurs RxBD AM indicates whether UADDR1 or UADDR2 matched Manual multidrop mode The controller receives all characters An address character is always written to a new buffer and can be followed by data characters User software performs the address comparison Figure 22 2 Two UART Multidrop Configurations 22 9 Receivi...

Page 680: ...8 15 0x50 E R CHARACTER1 0x52 E R CHARACTER2 0x5E E R CHARACTER8 0x60 1 1 RCCM 0x62 RCCR 1 From SCCx base address Figure 22 3 Control Character Table RCCM and RCCR Table 22 4 Control Character Table RCCM and RCCR Descriptions Offset Bits Name Description 0x50 0x5E 0 E End of table In tables with eight control characters E is always 0 0 This entry is valid 1 The entry is not valid and is not used 1...

Page 681: ...a higher priority than the other characters in the transmit buffer but does not preempt characters already in the transmit FIFO This means that the XON or XOFF character may not be sent for four SCC2 SCC4 character times To reduce this latency set GSMR_H TFL to decrease the FIFO size to one character before enabling the transmitter 0x60 0 1 0b11 Must be set Used to mark the end of the control char...

Page 682: ...he buffer For example for 8 data bits no parity 1 stop bit and 1 start bit a preamble of 10 ones is sent before the first character in the buffer 0 1 2 3 4 5 6 7 8 15 Field REA I CT A CHARSEND Reset 0000_0000_0000_0000 R W R W Addr SCC base 0x4E Figure 22 4 Transmit Out of Sequence Register TOSEQ Table 22 5 TOSEQ Field Descriptions Bit Name Description 0 1 Reserved should be cleared 2 REA Ready Se...

Page 683: ...egister DSR Table 22 6 DSR Fields Descriptions Bit Name Description 0 0b0 1 4 FSB Fractional stop bits For 16 oversampling 1111 Last transmitted stop bit 16 16 Default value after reset 1110 Last transmitted stop bit 15 16 1000 Last transmitted stop bit 9 16 0xxx Invalid Do not use For 32 oversampling 1111 Last transmitted stop bit 32 32 Default value after reset 1110 Last transmitted stop bit 31 ...

Page 684: ...hunt mode immediately CD Lost during Character Reception If this error occurs and the channel is using this pin to automatically control reception the channel terminates character reception closes the buffer sets RxBD CD and generates the RX interrupt if not masked This error has the highest priority The last character in the buffer is lost and other errors are not checked In automatic multidrop m...

Page 685: ...ived the UART sets SCCE BRKE which generates an interrupt if not masked If the UART is receiving characters when it receives a break it closes the Rx buffer sets RxBD BR and sets SCCE RX which can generate an interrupt if not masked If PSMR RZS 1 when the UART is in synchronous mode a break sequence is detected after two successive break characters are received 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1...

Page 686: ...buffer that was frozen 1 The SCC completes transmission of any data already transferred to the Tx FIFO the number of characters depends on GSMR_H TFL and then freezes After FRZ is cleared transmission resumes from the next character 7 RZS Receive zero stop bits 0 The receiver operates normally but at least one stop bit is needed between characters A framing error is issued if a stop bit is missing...

Page 687: ...ty mode bits 12 13 14 15 RPM TPM Receiver transmitter parity mode Selects the type of parity check the receiver transmitter performs can be modified on the fly Receive parity errors can be ignored but not disabled 00 Odd parity If a transmitter counts an even number of ones in the data word it sets the parity bit so an odd number is sent If a receiver receives an even number a parity error is repo...

Page 688: ...inter 0 E ID Rx BD 2 Status Length Pointer 1 XXXX 32 Bit Buffer Pointer E Rx BD 3 Status Length Pointer Byte 1 Byte 2 Byte 8 Buffer Byte 9 Byte 10 Buffer Byte 1 Byte 2 Byte 3 Buffer Byte 4 Error Empty Additional Bytes will be Stored Unless Idle Count Expires MAX_IDL 8 Bytes 8 Bytes 8 Bytes 8 Bytes Characters Received by UART Fourth Character 10 Characters Long Idle Period has Framing Error Present...

Page 689: ...the CPM indicating the need for the core to process the buffer Setting SCCE RX causes an interrupt if not masked 4 C Control character 0 This buffer does not contain a control character 1 The last byte in this buffer matches a user defined control character 5 A Address 0 The buffer contains only data 1 For manual multidrop mode A indicates the first byte of this buffer is an address byte Software ...

Page 690: ...et when a receiver overrun occurs during reception 15 CD Carrier detect lost Set when the carrier detect signal is negated during reception 0 1 2 3 4 5 6 7 8 9 14 15 Offset 0 R W I CR A CM P NS CT Offset 2 Data Length Offset 4 Tx Buffer Pointer Offset 6 Figure 22 9 SCC UART Transmit Buffer Descriptor TxBD Table 22 11 SCC UART TxBD Status and Control Field Descriptions Bit Name Description 0 R Read...

Page 691: ...ecutive buffers 5 A Address Valid only in multidrop mode automatic or manual 0 This buffer contains only data 1 This buffer contains address characters All data in this buffer is sent as address characters 6 CM Continuous mode 0 Normal operation The CPM clears R after this BD is closed 1 The CPM does not clear R after this BD is closed allowing the buffer to be resent next time the CPM accesses th...

Page 692: ...KS BRKE IDL CD Break Line Idle 10 Characters RXD CD Characters Received by UART Time Line Idle TXD RTS Characters Transmitted by UART CTS TX CTS CTS Line Idle Line Idle 7 Characters Notes UART SCCE Events 1 The first RX event assumes Rx buffers are 6 bytes each 2 The second IDL event occurs after an all ones character is received 3 The second RX event position is programmable based on the MAX_IDL ...

Page 693: ...Break start Set when the first character of a break sequence is received Multiple BRKS events are not received if a long break sequence is received 11 Reserved should be cleared 12 CCR Control character received and rejected Set when a control character is recognized and stored in the receive control character register RCCR 13 BSY Busy Set when a character is received and discarded due to a lack o...

Page 694: ... is not used and the divider is 162 decimal The resulting BRG1 clock is 16 the preferred bit rate 4 Connect BRG1 to SCC2 using the serial interface Clear SICR R2CS T2CS 5 Initialize the SDMA configuration register SDCR 0x0001 for normal operation 6 Connect the SCC2 to the NMSI Clear SICR SC2 7 Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD tables in dual port RAM Ass...

Page 695: ...pt The CICR should also be initialized 23 Write 0x0000_0020 to GSMR_H2 to configure a small Rx FIFO width 24 Write 0x0002_8004 to GSMR_L2 to configure 16 sampling for transmit and receive CTS and CD to automatically control transmission and reception DIAG bits and the SCC for UART mode Notice that the transmitter ENT and receiver ENR have not been enabled yet 25 Set PSMR2 to 0xB000 to configure au...

Page 696: ...om continually scanning for control characters Table 22 14 UART Control Characters for S Records Example Character Description Line Feed Both the E and R bits should be cleared When an end of line character is received the current buffer is closed and made available to the core for processing This buffer contains an entire S record that the processor can now check and copy to memory or disk as req...

Page 697: ... protocols permit addressing beyond 16 bits The 8 or 16 bit control field provides a flow control number and defines the frame type control or data The exact use and structure of this field depends on the protocol using the frame The length of the data in the data field depends on the frame protocol Layer 3 frames are carried in this data field Error control is implemented by appending a cyclic re...

Page 698: ...a closing flag is sent the SCC updates the frame status bits of the BD and clears TxBD R buffer ready At the end of the current buffer if TxBD L is not set multiple buffers per frame only TxBD R is cleared Before the SCC proceeds to the next TxBD in the table an interrupt can be issued if TxBD I is set This interrupt programmability allows the core to intervene after each buffer after a specific b...

Page 699: ...C then waits for a new frame Back to back frames can be received with only one shared flag between frames The received frames threshold parameter RFTHR can be used to postpone interrupts until a specified number of frames is received This function can be combined with a timer to implement a timeout if fewer than the specified number of threshold frames is received Note that an SCC in HDLC mode or ...

Page 700: ...he frame address from the HDLC receiver compares it with the HADDRs and masks the result with HMASK Setting an HMASK bit enables the corresponding comparison bit clearing a bit masks it When a match occurs the frame address and data are written to the buffers When no match occurs and a frame is error free the nonmatching address received counter NMARC is incremented The eight low order bits of HAD...

Page 701: ...vents this GRACEFUL STOP TRANSMIT Stops transmission smoothly Unlike a STOP TRANSMIT command it stops transmission after the current frame is finished or immediately if no frame is being sent SCCE GRA is set when transmission stops HDLC Tx parameters and Tx BDs can then be updated TBPTR points to the next TxBD Transmission begins once TxBD R of the next BD is set and a RESTART TRANSMIT command is ...

Page 702: ...er RETRC in the parameter RAM Table 23 5 Receive Errors Error Description Overrun Each SCC maintains an internal FIFO for receiving data The CPM begins programming the SDMA channel if the buffer is in external memory and updating the CRC when a full or partial FIFO s worth of data according to GSMR_H RFW is received in the Rx FIFO When an Rx FIFO overrun occurs the previous byte is overwritten by ...

Page 703: ...ved CRC to the buffer closes the buffer sets RxBD CR generates a maskable RXF interrupt and increments the CRC error counter CRCEC After receiving a frame with a CRC error the receiver enters hunt mode An immediate back to back frame is still received CRC checking cannot be disabled but the CRC error can be ignored if checking is not required 0 3 4 5 6 7 8 9 10 11 12 13 15 Field NOF CRC RTE FSE DR...

Page 704: ...s Mode with Collision Detection 11 BRM HDLC bus RTS mode Valid only if BUS 1 Otherwise it is ignored 0 Normal RTS operation during HDLC bus mode RTS is asserted on the first bit of the Tx frame and negated after the first collision bit is received 1 Special RTS operation during HDLC bus mode RTS is delayed by one bit with respect to the normal case which helps when the HDLC bus protocol is being r...

Page 705: ...ne or more of the CD OV AB and LG bits are set The SCC writes the number of frame octets to the data length field 5 F First in frame 0 Not the first buffer in a frame 1 First buffer in a frame 6 CM Continuous mode Note that RxBD E is cleared if an error occurs during reception regardless of CM 0 Normal operation 1 RxBD E is not cleared by the CPM after this BD is closed allowing the associated buf...

Page 706: ...er Address 1 Address 2 Control Byte Buffer CRC Byte 1 CRC Byte 2 Buffer Address 1 Address 2 Buffer Control Byte Empty 8 Bytes 8 Bytes 8 Bytes 8 Bytes Two Frames Received in HDLC Unexpected Abort Stored in Rx Buffer Line Idle Occurs before Present Time Time Stored in Rx Buffer Buffer Full Buffer Closed when Closing Flag Buffer Still Empty 1 AB 5 Empty MRBLR 8 Bytes for the SCC Empty Last I Field By...

Page 707: ...BDs in this table is determined by TxBD W and the space constraints of the dual port RAM 3 I Interrupt 0 No interrupt is generated after this buffer is processed 1 SCCE TXB or SCCE TXE is set when this buffer is processed causing interrupts if not masked 4 L Last 0 Not the last buffer in the frame 1 Last buffer in the frame 5 TC Tx CRC Valid only when TxBD L 1 Otherwise it is ignored 0 Transmit th...

Page 708: ... SCCM Field Descriptions Bits Name Description 0 2 Reserved should be cleared 3 4 GLR GLT Glitch on Rx Tx Set when the SCC detects a clock glitch on the receive transmit clock See Section 21 4 6 Clock Glitch Detection 5 DCC DPLL carrier sense changed Set when the carrier sense status generated by the DPLL changes Real time status can be read in SCCS CS This is not the CD status reported in port C ...

Page 709: ... CD Line Idle Stored in Rx Buffer RXD CD Frame Received by HDLC Time Line Idle TXD RTS Frame Transmitted by HDLC CTS TXB CTS CTS Line Idle Line Idle Stored in Tx Buffer NOTES HDLC SCCE Events 1 RXB event assumes receive buffers are 6 bytes each 2 The second IDL event occurs after 15 ones are received in a row 3 The FLG interrupts show the beginning and end of flag reception 4 The FLG interrupt at ...

Page 710: ...D2 Set PCPAR 14 and PCSO 8 9 and clear PCPAR 8 9 and PCDIR 8 9 14 0 4 5 6 7 Field FG CS ID Reset 0000_0000 R W R Addr 0xA37 SCCS2 0xA57 SCCS3 0xA77 SCCS4 Figure 23 9 SCC HDLC Status Register SCCS Table 23 10 HDLC SCCS Field Descriptions Bits Name Description 0 4 Reserved should be cleared 5 FG Flags The line is checked after the data has been decoded by the DPLL 0 HDLC flags are not being received...

Page 711: ...FTHR with 0x0001 to allow interrupts after each frame 16 Write HMASK with 0x0000 to allow all addresses to be recognized 17 Clear HADDR1 HADDR4 for clarity 18 Initialize the RxBD Assume the buffer is at 0x0000_1000 in main memory RxBD Status and Control 0xB000 RxBD Data Length 0x0000 not required and RxBD Buffer Pointer 0x0000_1000 19 Initialize the TxBD Assume the Tx data frame is at 0x0000_2000 ...

Page 712: ...lementation of an HDLC based LAN and other point to multipoint configurations The HDLC bus is based on techniques used in the CCITT ISDN I 430 and ANSI T1 605 standards for D channel point to multipoint operation over the S T interface However the HDLC bus does not fully comply with I 430 or T1 605 and cannot replace devices that implement these protocols Instead it is more suited to non ISDN LAN ...

Page 713: ... transfer data to or from any other LAN station Transmissions are half duplex which is typical in LANs Figure 23 10 Typical HDLC Bus Multimaster Configuration In single master configuration a master station transmits to any slave station without collisions Slaves communicate only with the master but can experience collisions in their access over the bus In this configuration a slave that communica...

Page 714: ...mit the HDLC bus controller monitors the bus using CTS It counts the one bits on CTS When eight consecutive ones are counted the HDLC bus controller starts transmitting on the line if a zero is detected the internal counter is cleared During transmission data is continuously compared with the external bus using CTS CTS is sampled halfway through the bit time using the rising edge of the Tx clock I...

Page 715: ...essfully sending a frame a station waits for 10 rather than eight consecutive one bits before attempting another transmission This mechanism ensures that another station waiting to transmit acquires the bus before a station can transmit twice When a low priority station detects 10 consecutive ones it tries to transmit if it fails it reinstates the high priority of waiting for only eight ones 23 14...

Page 716: ... bit which is useful when the HDLC bus connects multiple local stations to a transmission line If the transmission line driver has a one bit delay the delayed RTS can be used to enable the output of the line driver As a result the electrical effects of collisions are isolated locally Figure 23 15 shows RTS timing Figure 23 15 Delayed RTS Mode Local HDLC Bus HDLC Bus Controller RXD CTS TXD A HDLC B...

Page 717: ...k edges of the particular SCC time slot 23 14 6 HDLC Bus Protocol Programming The HDLC bus is implemented using the SCC in HDLC mode with bus specific options selected in the PSMR and GSMR as outlined below See also Section 23 5 Programming the SCC HDLC Controller 23 14 6 1 Programming GSMR and PSMR for the HDLC Bus Protocol To program the protocol specific mode register PSMR set the bits as descr...

Page 718: ...efault Configure the DIAG bits for normal operation 0b00 Configure RDCR and TDCR for 1 clock 0b00 Configure TENC and RENC for NRZ 0b000 Clear RTSM to send idles between frames Set GSMR_L ENT ENR as the last step to begin operation 23 14 6 2 HDLC Bus Controller Programming Example Except for the above discussion in Section 23 14 6 1 Programming GSMR and PSMR for the HDLC Bus Protocol use the exampl...

Page 719: ...n three bits is sent This sequence consists of at least one logical one bit FM0 encoded followed by two bit times or more of line idle with no particular maximum time specified The idle time allows LocalTalk equipment to sense a carrier by detecting a missing clock on the line The remainder of the frame is a typical half duplex HDLC frame Two or more flags are sent allowing bit byte and frame deli...

Page 720: ...e powers up and enters the network A higher level protocol controls the uniqueness and transmission of ENQ frames In addition to the frame fields LocalTalk requires that the frame be FM0 differential Manchester space encoded which requires one level transition on every bit boundary If the value to be encoded is a logical zero FM0 requires a second transition in the middle of the bit time The purpo...

Page 721: ...he GSMR as described below 1 Set MODE to 0b0010 AppleTalk 2 Set DIAG to 0b00 for normal operation with CD and CTS grounded or configured for parallel I O This causes CD and CTS to be internally asserted to the SCC 3 Set RDCR and TDCR to 0b10 a 16 clock 4 Set the TENC and RENC bits to 0b010 FM0 5 Clear TEND for default operation 6 Set TPP to 0b11 for a preamble pattern of all ones 7 Set TPL to 0b00...

Page 722: ...SMR Follow these steps to program the protocol specific mode register 1 Set NOF to 0b0001 giving two flags before frames one opening flag plus one additional flag 2 Set CRC 16 bit CRC CCITT 3 Set DRT 4 Set all other bits to zero or default For the PSMR definition see Section 23 8 HDLC Mode Register PSMR 24 4 3 Programming the TODR Use the transmit on demand TODR register to expedite a transmit fra...

Page 723: ...a frame be sent or received Separate interrupts for received frames and transmitted buffers Automatic CRC generation and checking Support for nonmultiplexed serial interface control signals Automatic generation of opening and closing flags Reception of frames with a single shared flag Automatic generation and stripping of transparency characters according to RFC 1549 using transmit and receive con...

Page 724: ...he incoming frame into the buffer When the buffer is full the controller clears RxBD E If the incoming frame is larger than the buffer the controller fetches the next BD and if E is set continues transferring the rest of the frame into its buffer The receiver decodes the transparency character required by asynchronous HDLC protocol as described in Section 25 5 Receiver Transparency Decoding When t...

Page 725: ...en inserted in the character stream by an intermediate device and is not part of the original frame It reverses the transmission transparency sequence by discarding a received control escape character 0x7D and exclusive ORing the following byte with 0x20 before performing the CRC calculation and writing the byte into memory Figure 25 2 shows the algorithm because some cases are not covered by RFC ...

Page 726: ... neither generated nor examined by the microcode while sending or receiving The destination address field of the frame must be included in the Tx buffer Any address field compression expansion or checking must be performed by the core Control field The control field is neither generated nor examined by the microcode during a transfer The control field of the frame must be included in the buffer An...

Page 727: ...served 0x46 ZERO Hword Clear this field 0x48 Hword Reserved 0x4A RFTHR Hword Received frames threshold Number of Rx frames needed to trigger SCCE RXF 0x4C Word Reserved 0x50 TXCTL_TBL Word Control character tables Stores the bit array used for the Tx Rx control characters See Figure 25 3 Each bit corresponds to a character that should be mapped according to RFC 1549 If a TXCTL_TBL bit is set its c...

Page 728: ...nterrupt is generated when the status of either line changes 25 11 Asynchronous HDLC Commands The transmit and receive commands are issued to the CP command register CPCR Table 25 2 Asynchronous HDLC Specific GSMR Field Descriptions Name Description IRP Infrared Rx polarity GSMR_H 13 Determines the polarity of the received signal when SCC2 uses IrDA encoding decoding for SCC2 only See Section 25 1...

Page 729: ...at unlike with other SCC protocols the STOP TRANSMIT command does not flush the FIFO Up to 16 characters can be sent ahead of the abort sequence unless GSMR_H TFL 1 GRACEFUL STOP TRANSMIT Not supported by the asynchronous HDLC controller RESTART TRANSMIT Reenables transmission of characters the asynchronous HDLC controller expects it after a STOP TRANSMIT command or transmitter error The controlle...

Page 730: ...CE RXF The receiver then looks for the next frame CD Lost during Frame Reception The channel stops receiving frames closes the buffer and sets SCCE RXF and RxBD CD This error has highest priority The rest of the frame is lost and other errors are not checked in that frame The receiver then searches for the next frame once CD is reasserted Abort Sequence When an abort sequence 0x7D 0x7E for PPP 0x7...

Page 731: ...ected after a break sequence 10 BRKS Break start Set when the first break character of a break sequence is received Only one BRKS event occurs per break sequence no matter the length of the sequence 11 TXE Tx error Set when an error occurs on the transmitter channel 12 RXF Rx frame Set when the number of frames specified in RFTHR are received RXF is set no sooner than when the midpoint of the clos...

Page 732: ...or at least a full character time 0 The line is not idle 1 The line is idle 0 1 2 3 4 15 Field FLC CHLN Reset 0 R W R W Addr 0xA28 PSMR2 0xA48 PSMR3 0xA68 PSMR4 Figure 25 6 Asynchronous HDLC Mode Register PSMR Table 25 9 PSMR Field Descriptions Bits Name Description 0 FLC Flow control 0 Normal operation 1 Asynchronous flow control When CTS is negated the transmitter stops at the end of the current...

Page 733: ...I Interrupt 0 SCCE RXB is not set after this buffer is used SCCE RXF is unaffected 1 SCCE RXB or SCCE RXF is set when this buffer is used by the asynchronous HDLC controller 4 L Last in frame 0 Not the last buffer in a frame 1 Set by SCC when a buffer is the last in a frame which happens when a closing flag or error is received If an error occurs one or more of the BRK CD OV BOF CR and AB bits are...

Page 734: ... Offset 4 Tx Buffer Pointer Offset 6 Figure 25 8 SCC Asynchronous HDLC TxBDs Table 25 11 Asynchronous HDLC TxBD Status and Control Field Descriptions Bits Name Description 0 R Ready 0 The buffer is not ready for transmission the BD and the buffer can be updated The CPM clears R after the buffer is sent or after an error condition 1 The buffer is ready but is not sent or is being sent Do not update...

Page 735: ...haracters for which all three samples are not identical are not accounted for in the asynchronous HDLC controller It is assumed that the CRC catches any data integrity problems 25 17 SCC Asynchronous HDLC Programming Example The following example shows initialization for an SCC in asynchronous HDLC mode 1 Initialize SDCR 2 In NMSI mode configure ports A and C to enable RXD TXD CTS CD and RTS In ot...

Page 736: ...C However SCC2 includes additional hardware to support the encoding decoding required by the IrDA physical layer IrDA defines a family of specifications for interconnecting computers and peripherals using a directed half duplex serial infrared communications medium The IrDA data link layer protocol is based on a preexisting standard asynchronous HDLC protocol Figure 25 9 shows a serial infrared SI...

Page 737: ... receive decoder are nominally the same duration as those between the IR transmit encoder output driver and LED Figure 25 10 UART and IR Frames The SIR encoding decoding is supported only for SCC2 To activate it set GSMR_L2 SIR and configure GSMR_L2 RDCR TDCR for 16x clock operation b a Data Bits Start Bit Stop Bit 3 16 Bit Time IR Frame 1 0 0 1 0 0 1 1 0 1 UART Frame ...

Page 738: ...SCC Asynchronous HDLC Mode and IrDA MPC885 PowerQUICC Family Reference Manual Rev 2 25 16 Freescale Semiconductor ...

Page 739: ...ceded by a DLE character This is sometimes called byte stuffing The physical layer of the BISYNC communications link must synchronize the receiver and transmitter usually by sending at least one pair of synchronization characters before each frame BISYNC protocol is unusual in that a transmit underrun need not be an error If an underrun occurs a synchronization pattern is sent until data is again ...

Page 740: ...er a buffer is sent if the last TxBD L and the Tx block check sequence TxBD TB bits are set the BISYNC controller appends the CRC16 LRC and then writes the message status bits in TxBD status and control fields and clears the ready bit TxBD R It then starts sending the SYN1 SYN2 pairs or idles according to GSMR RTSM If the end of the current BD is reached and TxBD L is not set only TxBD R is cleare...

Page 741: ...a exceeds the buffer length the controller fetches the next BD if E is zero reception continues to its buffer When a BCS is received it is checked and written to the buffer The BISYNC controller sets the last bit writes the message status bits into the BD clears the E bit and then generates a maskable interrupt indicating that a block of data was received and is in memory The BCS calculations do n...

Page 742: ...uent data without interrupting the core 0x40 BDLE Hword BISYNC DLE register Contains the value to be sent as the first byte of a DLE SYNC pair and stripped on receive See Section 26 8 SCC BISYNC DLE Register BDLE 0x42 CHARACTER1 Hword Control character 1 8 These values represent control characters that the BISYNC controller recognizes See Section 26 6 SCC BISYNC Control Character Recognition 0x44 ...

Page 743: ...T TRANSMIT is issued RESTART TRANSMIT Lets characters be sent on the transmit channel The BISYNC controller expects it after a STOP TRANSMIT or a GRACEFUL STOP TRANSMIT command is issued after a transmitter error occurs or after a STOP TRANSMIT is issued and the channel is disabled in its SCCM The controller resumes transmission from the current TBPTR in the channel s TxBD table INIT TX PARAMETERS...

Page 744: ...ws the remainder of the block to be received without interrupting software Up to eight control characters can be defined to inform the BISYNC controller that the end of the current block is reached and whether a BCS is expected after the character For example the end of text character ETX implies an end of block ETB with a subsequent BCS An enquiry ENQ character designates an end of block without ...

Page 745: ...r the buffer is closed 0 The character is written into the receive buffer and the buffer is closed 1 The character is written into the receive buffer The receiver waits for one LRC or two CRC bytes of BCS and then closes the buffer This should be used for ETB ETX and ITB 2 H Hunt mode Enables hunt mode when the current buffer is closed 0 The BISYNC controller maintains character synchronization af...

Page 746: ...fer is closed with the DLE follow character error bit set If the valid bit is not set the receiver treats the character as a normal character When using 7 bit characters with parity the parity bit should be included in the DLE register value Table 26 6 describes BDLE fields 26 9 Sending and Receiving the Synchronization Sequence The BISYNC channel can be programmed to send and receive a synchroniz...

Page 747: ...NSMIT command is received Table 26 9 Receive Errors Error Description Overrun The controller maintains a receiver FIFO for receiving data The CP begins programming the SDMA channel if the buffer is in external memory and updating the CRC when the first byte is received in the Rx FIFO If an Rx FIFO overrun occurs the controller writes the received byte over the previously received byte The previous...

Page 748: ...e the channel is enabled for odd LRC they should be initialized to ones Note that the receiver checks character parity when BCS is programmed to LRC and the receiver is not in transparent mode The transmitter sends character parity when BCS is programmed to LRC and the transmitter is not in transparent mode Use of parity in BISYNC assumes that 7 bit data characters are being used 6 RBCS Receive BC...

Page 749: ...leared 12 13 RPM Receiver parity mode Selects the type of parity check that the receiver performs RPM can be modified on the fly and is ignored unless CRC 11 LRC Receive parity errors cannot be disabled but can be ignored 00 Odd parity The transmitter counts ones in the data word If the sum is not odd the parity bit is set to ensure an odd number An even sum indicates a transmission error 01 Low p...

Page 750: ...the number of frame octets to the data length field 0 Not the first buffer in the frame 1 The first buffer in the frame 5 F First in frame Set when this is the first buffer in a frame 0 Not the first buffer in a frame 1 First buffer in a frame 6 CM Continuous mode 0 Normal operation 1 The CP does not clear E after this BD is closed the buffer is overwritten when the CP accesses this BD next Howeve...

Page 751: ...n 0 R Ready 0 The buffer is not ready for transmission The current BD and buffer can be updated The CP clears R after the buffer is sent or after an error condition 1 The user prepared buffer has not been sent or is being sent This BD cannot be updated while R 1 1 Reserved should be cleared 2 W Wrap last BD in table 0 Not the last BD in the table 1 Last BD in the table After this buffer is used th...

Page 752: ...ic DLE transmission can occur before the data buffer 1 The transmitter sends a DLE character before sending the buffer which saves writing the first DLE to a separate buffer in transparent mode See TR for information on control characters 9 TR Transparent mode 0 The transmitter enters and stays in normal mode after sending the buffer The transmitter automatically inserts SYNCs if an underrun condi...

Page 753: ...carrier sense status generated by the DPLL changes Real time status can be found in SCCS This is not the CD status discussed elsewhere Valid only when DPLL is used 6 7 Reserved should be cleared 8 GRA Graceful stop complete Set as soon the transmitter finishes any message in progress when a GRACEFUL STOP TRANSMIT is issued immediately if no message is in progress 9 10 Reserved should be cleared 11...

Page 754: ...block either set PSMR RTR or issue a RESET BCS CALCULATION command For example if a DLE STX is received enter transparent mode By setting the appropriate PSMR bit the controller strips the leading DLE from DLE character sequences Thus control characters are recognized only when they follow a DLE character PSMR RTR should be cleared after a DLE ETX is received Alternatively after an SOH is received...

Page 755: ...e RxBD at the beginning of dual port RAM followed by one TxBD write RBASE with 0x0000 and TBASE with 0x0008 8 Write 0x0041 to CPCR to execute the INIT RX AND TX PARAMS command for SCC2 This command updates RBPTR and TBPTR of the serial channel with the new values of RBASE and TBASE 9 Write RFCR and TFCR with 0x10 for normal operation 10 Write MRBLR with the maximum number of bytes per receive buff...

Page 756: ...y control transmission and reception DIAG bits and the BISYNC mode Notice that the transmitter ENT and receiver ENR are not yet enabled 26 Set PSMR2 to 0x0600 to configure CRC16 CRC checking on receive and normal operation not transparent 27 Write 0x00000038 to GSMR_L2 to enable the transmitter and receiver This additional write ensures that ENT and ENR are enabled last Note that after 5 bytes are...

Page 757: ...n pattern on which to lock The start frame delimiter follows the preamble signifying the beginning of the frame The 48 bit destination address is next followed by the 48 bit source address Original versions of the IEEE 802 3 specification allowed 16 bit addressing but this addressing has never been widely used and is not supported The next field is the ethernet type field IEEE 802 3 length field T...

Page 758: ... Mbps ethernet interframe gap is 9 6 µs and the slot time is 52 µs 27 1 Ethernet on the MPC885 Setting GSMR MODE to 0b1100 selects ethernet The SCC performs the full set of IEEE 802 3 ethernet CSMA CD media access control and channel interface functions Figure 27 2 shows the ethernet block diagram Figure 27 2 Ethernet Block Diagram The MPC885 ethernet controller requires an external serial interfa...

Page 759: ...CRC generation and checking Automatically pads short frames on transmit Framing error dribbling bits handling Full collision support Enforces the collision jamming Truncated binary exponential backoff algorithm for random wait Two nonaggressive backoff modes Automatic frame retransmission until the retry limit is reached Automatic discard of incoming collided frames Delay transmission of new frame...

Page 760: ...should first read the following Chapter 21 Serial Communications Controllers describes basic operation of the SCCs Chapter 17 Communications Processor Module and CPM Timers describes how the CPM issues special commands to the ethernet channel The dual port RAM loads ethernet parameters and initializes BDs for the ethernet channel to use Chapter 19 SDMA Channels and IDMA Emulation discusses how SDM...

Page 761: ...The carrier sense signal is referenced in ethernet descriptions because it indicates when the LAN is in use Carrier sense is defined as the logical OR of RENA and CLSN Figure 27 3 shows the basic components and signals required to make an ethernet connection between the MPC885 and EEST Figure 27 3 Connecting the MPC885 to Ethernet The EEST has similar names for its connection to the above seven MP...

Page 762: ...ision This improves bus usage and latency when the backoff timer output requires an immediate retransmission If a collision occurs during frame transmission the controller returns to the first buffer for a retransmission The only restriction is that the first buffer must contain at least 9 bytes Note that if an ethernet frame consists of multiple buffers do not reuse the first BD until the CPM cle...

Page 763: ... station If a match is found the ethernet controller fetches the next RxBD and if it is empty starts transferring the incoming frame to the RxBD associated data buffer If a collision is detected during the frame the RxBDs associated with this frame are reused Thus there will be no collision frames presented to you except late collisions which indicate serious LAN problems When the data buffer has ...

Page 764: ...y down counter for counting retries 0x4A MFLR Hword Maximum frame length register typically 1518 decimal The ethernet controller checks the length of an incoming ethernet frame against this limit If it is exceeded the rest of the frame is discarded and LG is set in the last BD of that frame The controller reports frame status and length in the last BD MFLR is defined as all in frame bytes between ...

Page 765: ...the retry count in the backoff algorithm to reduce the chance of transmission on the next time slot Note Using P_PER is fully allowed in the ethernet 802 3 specifications A less aggressive backoff algorithm used by multiple stations on a congested ethernet LAN increases overall throughput by reducing the chance of collision PSMR SBT offers another way to reduce the aggressiveness of the ethernet c...

Page 766: ...ritten PADDR_L 6655 PADDR_M 4433 and PADDR_H 2211 The TADDR should be written in the same way as the PADDR Table 27 3 Transmit Commands Command Description STOP TRANSMIT When used with the ethernet controller this command violates a specific behavior of an ethernet IEEE 802 3 station It should not be used GRACEFUL STOP TRANSMIT Used to ensure that transmission stops smoothly after the current fram...

Page 767: ...iver then enters hunt mode waiting for an incoming frame The ENTER HUNT MODE command is generally used to force the ethernet receiver to stop receiving the current frame and enter hunt mode in which the ethernet controller continually scans the input data stream for a transition of carrier sense from inactive to active and then a preamble sequence followed by the start frame delimiter After receiv...

Page 768: ...g operate using certain processes The ethernet controller maps any 48 bit address into one of 64 bins each represented by a bit stored in GADDRx or IADDRx When a SET GROUP ADDRESS command is executed the ethernet controller maps the selected 48 bit address into one of the 64 bits by passing the 48 bit address through the on chip 32 bit CRC generator and selecting 6 bits Check Address I G Address H...

Page 769: ...es with a minimum interpacket spacing of 9 6 µs In addition after the backoff algorithm the transmitter waits for carrier sense to be negated before resending the frame Retransmission begins 9 6 µs after carrier sense is negated if it stays negated for at least 6 4 µs 27 13 Handling Collisions If a collision occurs as a frame is being sent the ethernet controller continues sending for at least 32 ...

Page 770: ...urs Carrier sense is the logical OR of RENA and CLSN Retransmission retry limit expired The channel stops sending the buffer closes it sets the RL bit in the TxBD and SCCE TXE The channel resumes transmission after it receives a RESTART TRANSMIT command Late collision When this error occurs the channel stops sending the buffer closes it sets SCCE TXE and the LC bit in the TxBD The channel resumes ...

Page 771: ...C PRO BRO SBT LPB SIP LCW NIB FDE Reset 0000_0000_0000_0000 R W R W Addr 0xA28 PSMR2 0xA48 PSMR3 0xA68 PSMR4 Figure 27 5 Ethernet Mode Register PSMR Table 27 7 PSMR Field Descriptions Bits Name Description 0 HBC Heartbeat checking 0 No heartbeat checking is performed Do not wait for a collision after transmission 1 Wait 20 transmit clocks or 2 µs for a collision asserted by the transceiver after t...

Page 772: ... for loopback operation 10 SIP Sample input pins 0 Normal operation 1 After a frame is received the value on PB 16 23 is sampled and written to the end of the last buffer of the frame This value is called a tag byte If the frame is discarded the tag byte is also discarded 11 LCW Late collision window 0 A late collision is any collision that occurs at least 64 bytes from the preamble 1 A late colli...

Page 773: ... SH NO and LG bits are set The ethernet controller writes the number of frame octets to the data length field 0 The buffer is not the last one in a frame 1 The buffer is the last one in a frame 5 F First in frame The ethernet controller sets this bit when this buffer is the first one in a frame 0 The buffer is not the first one in a frame 1 The buffer is the first one in a frame 6 Reserved should ...

Page 774: ... Receive BD 2 Status Length Pointer 1 XXXX 32 Bit Buffer Pointer E Receive BD 3 Status Length Pointer Destination Address 6 Source Address 6 Type Length 2 Buffer CRC Bytes 4 Tag Byte 1 Buffer Buffer Old Data from Empty 64 Bytes 64 Bytes 64 Bytes 64 Bytes Two Frames Received in ethernet Collision Line Idle Present Time Time Buffer Full Buffer Closed after CRC Received Buffer Still Empty Empty MRBLR...

Page 775: ... Pad bytes are inserted until the length of the sent frame equals the MINFLR and they are stored in PADs in the parameter RAM 2 W Wrap final BD in table 0 Not the last BD in the table 1 Last BD in the table After this buffer is used the CPM receives incoming data into the first BD that TBASE points to in the table The number of TxBDs in this table is determined only by the W bit Note The TxBD tabl...

Page 776: ...of retries required before the frame was sent successfully If RC 0 the frame was sent correctly the first time If RC 15 and RET_LIM 15 in the parameter RAM 15 retries were required Because the counter saturates at 15 if RC 15 and RET_LIM 15 then 15 or more retries were required The controller writes this field after it successfully sends the buffer 14 UN Underrun Set when the ethernet controller e...

Page 777: ...s Name Description RXB Line Idle Stored in Rx Buffer RXD RENA Frame Received in ethernet Time Line Idle TXD TENA Frame Transmitted by ethernet CLSN TXB GRA TXB Line Idle Line Idle Stored in Tx Buffer NOTES ethernet SCCE Events 1 RXB event assumes receive buffers are 64 bytes each 2 The RENA events if required must be programmed in the port C parallel I O not in the SCC itself 3 The RxF interrupt m...

Page 778: ...ogram the CPCR to execute an INIT RX AND TX PARAMETERS command for this channel 10 Write RFCR and TFCR with 0x10 for normal operation 11 Write MRBLR with the maximum number of bytes per receive buffer Here assume 1520 bytes so MRBLR 0x05F0 In this example the user wants to receive an entire frame into one buffer so MRBLR is the first value larger than 1518 evenly divisible by four 12 Write C_PRES ...

Page 779: ...CLSN and CD RENA to automatically control transmission and reception DIAG bits and the ethernet mode TCI is set to allow more setup time for the EEST to receive the MPC885 transmit data TPL and TPP are set for ethernet requirements The DPLL is not used with ethernet Note that the ENT and ENR are not enabled yet 32 Write 0xD555 to the DSR 33 Set the PSMR2 to 0x0A0A to configure 32 bit CRC promiscuo...

Page 780: ...SCC Ethernet Mode MPC885 PowerQUICC Family Reference Manual Rev 2 27 24 Freescale Semiconductor ...

Page 781: ...in GSMR_H TTX TRX for the transmitter and receiver respectively Setting both bits enables full duplex transparent operation If only one is set the other half of the SCC uses the protocol specified in GSMR_L MODE This allows loop back modes to DMA data from one memory location to another while data is converted to a specific serial format The SCC operations are asynchronous with the core and can be...

Page 782: ...each transparent frame if it is enabled in the TxBD When the time slot assigner TSA is used with a transparent mode channel synchronization is provided by the TSA There is a start up delay for the transmitter but delays will always be some whole number of complete TSA frames This means that n byte transmit buffers can be mapped directly into n byte time slots in the TSA frames 28 2 SCC Transparent...

Page 783: ...chronization Signals If GSMR_H SYNL is 0b00 the transmitter uses CTS and the receiver uses CD to begin the sequence These signals share two options pulsing and sampling GSMR_H CDP and GSMR_H CTSP determine whether CD or CTS need to be asserted only once to begin reception transmission or whether they must remain asserted for the duration of the transparent frame Pulse operation allows an uninterru...

Page 784: ...itter provide a falling edge by manipulating the I O pin in software Enable the receiver and transmitter for the SCC in loop back mode and then change GSMR_L DIAG to 0b00 while the transmitter and receiver and enabled RXD CD CLKx TXD RTS CD RXD BRGOx RTS TXD CLKx BRGOx BRGOx Last Bit of Frame Data First Bit of Frame Data Output is CLKx Input TXD Output is RXD Input RTS Output is CD Input or CRC Tx...

Page 785: ...pecified data pattern arrives To synchronize on an in line pattern Set GSMR_H SYNL Program the DSR with the desired pattern Clear GSMR_H CDP Set GSMR_H CTSP CTSS CDS If GSMR_H TXSY is also used the transmitter begins transmission eight clocks after the receiver achieves synchronization 28 3 2 2 Inherent Synchronization Inherent synchronization assumes synchronization by default when the channel is...

Page 786: ...s reset and the channel is enabled in the GSMR the channel is in transmit enable mode and starts polling the first BD every 64 clocks or immediately if TODR TOD 1 STOP TRANSMIT disables frame transmission on the transmit channel If the transparent controller receives the command during frame transmission transmission is aborted after a maximum of 64 additional bits and the transmit FIFO is flushed...

Page 787: ...eceiver is disabled INIT TX AND RX PARAMETERS resets receive and transmit parameters Table 28 5 Transmit Errors Error Description Transmitter Underrun When this occurs the channel stops sending the buffer closes it sets TxBD UN and generates a TXE interrupt if it is enabled Transmission resumes after a RESTART TRANSMIT command is received Underrun occurs after a transmit frame for which TxBD L was...

Page 788: ...s Bits Name Description 0 E Empty 0 The buffer is full or stopped receiving data because an error occurred The core can read or write to any fields of this RxBD The CPM does not use this BD when RxBD E is zero 1 The buffer is not full This RxBD and buffer are owned by the CPM Once E is set the core should not write any fields of this RxBD 1 Reserved should be cleared 2 W Wrap final BD in table 0 N...

Page 789: ...ffer be overwritten when the CPM next accesses this BD However RxBD E is cleared if an error occurs during reception regardless of how CM is set 7 Reserved should be cleared 8 DE DPLL error Set by the transparent controller when a DPLL error occurs as this buffer is received In decoding modes where a transition is promised every bit DE is set when a missing transition occurs If a DPLL error occurs...

Page 790: ...t sent yet or is being sent This BD cannot be updated while R 1 1 Reserved should be cleared 2 W Wrap final BD in table 0 Not the last BD in the table 1 Last BD in the table After this buffer is used the CPM receives incoming data into the first BD that TBASE points to The number of TxBDs in this table is determined only by TxBD W 3 I Interrupt Note that clearing this bit does not disable SCCE TXE...

Page 791: ...status changes valid only when the DPLL is used Real time status can be read in SCCS This is not the CD status mentioned elsewhere 6 7 Reserved should be cleared 8 GRA Graceful stop complete Set when a graceful stop initiated by completes as soon as the transmitter finishes any frame in progress when the GRACEFUL STOP TRANSMIT command was issued Immediately if no frame was in progress when the com...

Page 792: ...CS and SICR T2CS 5 Connect the SCC2 to the NMSI its own set of pins and clear SICR SC2 6 Initialize the SDMA configuration register SDCR to 0x0001 7 Write RBASE with 0x0000 and TBASE with 0x0008 in the SCC2 parameter RAM to point to one RxBD at the beginning of dual port RAM followed by one TxBD 8 Write 0x0041 to CPCR to execute the INIT RX AND TX PARAMS command for SCC2 This command updates RBPTR...

Page 793: ...nterrupts 17 Write 0x2000_0000 to the CPM interrupt mask register CIMR to allow SCC2 to generate a system interrupt The CICR should also be initialized 18 Write 0x0000_1980 to GSMR_H2 to configure the transparent channel 19 Write 0x0000_0000 to GSMR_L2 to configure CTS and CD to automatically control transmission and reception DIAG bits Normal operation of the transmit clock is used Note that the ...

Page 794: ...SCC Transparent Mode MPC885 PowerQUICC Family Reference Manual Rev 2 28 14 Freescale Semiconductor ...

Page 795: ...el such as a T1 line or directly to its own set of pins The receive and transmit clocks are derived from the TDM channel the internal BRGs or from an external 1 clock The transparent protocol allows the transmitter and receiver to use the external synchronization pin The SMC in transparent mode is not as complex as the SCC in transparent mode Each SMC supports the C I and monitor channels of the G...

Page 796: ...ocol can use SMSYN for synchronization to determine when to start a transfer SMSYN is not used when the SMC is in UART mode 29 1 SMC Features The following is a list of the main SMC features Each SMC can implement the UART protocol on its own pins Each SMC can implement a totally transparent protocol on a multiplexed TDM or non multiplexed NMSI line The transparent mode can also be used for a fast...

Page 797: ...ength set SL to one stop bit and disable parity For a 13 bit data length with parity enabled set SL to one stop bit Writing values 0 to 3 to CLEN causes erratic behavior Character length transparent The values 3 15 specify 4 16 bits per character If a character is less than 8 bits the msbs of the byte in buffer memory are not used on transmit and are written with zeros on receive If character leng...

Page 798: ...ormal mode Should be selected if the character length is not larger than 8 bits 1 Transmit lower address byte first Reserved should be cleared GCI 7 PM Parity mode UART 0 Odd parity 1 Even parity REVD Reverse data transparent 0 Normal mode 1 Reverse the character bit order The msb is sent first C SCIT channel number GCI 0 SCIT channel 0 1 SCIT channel 1 Required for Siemens ARCOFI and SGS S T chip...

Page 799: ...e half word long for receive For more information on these half word structures see Section 29 5 SMC in GCI Mode 29 2 3 SMC Parameter RAM Each SMC parameter RAM area begins at the same offset from each SMC base The protocol specific portions of the SMC parameter RAM are discussed in the sections that follow The SMC parameter RAM shared by the UART and transparent protocols is shown in Table 29 2 P...

Page 800: ...hile the SMC receiver is disabled MRBLR should be greater than zero and should be even if character length exceeds 8 bits 0x08 RSTATE Word Rx internal state Can be used only by the CP 0x0C Word Rx internal data pointer 2 Updated by the SDMA channels to show the next address in the buffer to be accessed 0x10 RBPTR Hword RxBD pointer Points to the next BD for each SMC channel that the receiver trans...

Page 801: ...he value to appear on the function code pins AT 1 3 when the associated SDMA channel accesses memory The FCRs also control byte ordering See Figure 29 4 Table 29 3 describes RFCR fields 0x28 Hword First half word of protocol specific area 0x32 Hword Last half word of protocol specific area 1 From SMC base address SMC base IMMR 3E80 SMC1 3F80 SMC2 2 Not accessed for normal operation May hold helpfu...

Page 802: ...quired 2 Clear SMCMR TEN to disable the SMC transmitter and put it in reset state 3 Update SMC transmit parameters including the parameter RAM To switch protocols or reinitialize parameters issue an INIT TX PARAMETERS command 4 Issue a RESTART TRANSMIT if an INIT TX PARAMETERS was not issued in step 3 5 Set SMCMR TEN Transmission now begins using the TxBD that the TBPTR value points to as soon as ...

Page 803: ...N are zero the SMC consumes very little power 29 2 6 Handling Interrupts in the SMC Follow these steps to handle an interrupt in the SMC 1 Once an interrupt occurs read SMCE to identify the interrupt source The SMCE bits are usually cleared at this time 2 Process the TxBD to reuse it if SMCE TX is set Extract data from the RxBD if SMCE RX is set To send another buffer set R in the TxBD 3 Clear CIS...

Page 804: ...n Table 29 4 Table 29 4 SMC UART Specific Parameter RAM Memory Map Offset1 Name Width Description 0x28 MAX_IDL Hword Maximum idle characters When a character is received on the line the SMC starts counting idle characters received If MAX_IDL idle characters arrive before the next character an idle time out occurs and the buffer closes which sends an interrupt request to the core to receive data fr...

Page 805: ...in the BD 29 3 4 SMC UART Channel Reception Process When the core enables the SMC receiver it enters HUNT mode and waits for the first character The CP then checks the first RxBD to see if it is empty and starts storing characters in the buffer When the buffer is full or the MAX_IDL timer expires if enabled the SMC clears the E bit in the BD and generates an interrupt if the I bit in the BD is set...

Page 806: ...ription STOP TRANSMIT Disables transmission of characters on the transmit channel If the SMC UART controller receives this command while sending a message it stops sending The SMC UART controller finishes sending any data that has already been sent to its FIFO and shift register and then stops sending data The TBPTR is not advanced when this command is issued The SMC UART controller sends a progra...

Page 807: ...no transmission errors Table 29 7 SMC UART Errors Error Description Overrun The SMC maintains a two character length FIFO for receiving data Data is moved to the buffer after the first character is received into the FIFO if a receiver FIFO overrun occurs the channel writes the received character into the internal FIFO It then writes the character to the buffer closes it sets RxBD OV and generates ...

Page 808: ...ero 1 The buffer is empty or reception is in progress This RxBD and its buffer are owned by the CP Once E is set the core should not write any fields of this RxBD 1 Reserved should be cleared 2 W Wrap last BD in RxBD table 0 Not the last BD in the table 1 Last BD in the table After this buffer is used the CP receives incoming data into the first BD that RBASE points to in the table The number of R...

Page 809: ...tion of break Set when the buffer closes because a break sequence was received The CP writes BR after the received data is in the buffer 11 FR Framing error Set when a character with a framing error is received and located in the last byte of this buffer A framing error is a character with no stop bit A new receive buffer is used to receive additional data The CP writes FR after the received data ...

Page 810: ...D 2 Status Length Pointer 1 XXXX 32 Bit Buffer Pointer E Receive BD 3 Status Length Pointer Byte 1 Byte 2 Byte 8 Buffer Byte 9 Byte 10 Buffer Byte 1 Byte 2 Byte 3 Buffer Byte 4 Error Empty Additional Bytes will be Stored Unless Idle Count Expires MAX_IDL 8 Bytes 8 Bytes 8 Bytes 8 Bytes Characters Received by UART Fourth Character 10 Characters Long Idle Period has Framing Error Present Time Time 5...

Page 811: ...29 9 SMC UART TxBD Status and Control Field Descriptions Bits Name Description 0 R Ready 0 The buffer is not ready for transmission BD and its buffer can be altered The CP clears R after the buffer has been sent or an error occurs 1 The buffer has not been completely sent This BD must not be updated while R is set 1 Reserved should be cleared 2 W Wrap final BD in the TxBD table 0 Not the last BD i...

Page 812: ... be cleared before the CP clears the internal interrupt request These registers are affected by HRESET and SRESET Table 29 10 describes SMCE SMCM fields 0 1 2 3 4 5 6 7 Field BRKE BRK BSY TX RX Reset 0 R W R W Addr 0xA86 SMCE1 0xA96 SMCE2 0xA8A SMCM1 0xA9A SMCM2 Figure 29 9 SMC UART Event Register SMCE Mask Register SMCM Table 29 10 SMCE SMCM Field Descriptions Bits Name Description 0 Reserved sho...

Page 813: ...h 0x0008 5 Write 0x0091 to CPCR to execute the INIT RX AND TX PARAMETERS command 6 Initialize the SDMA configuration register SDCR to 0x0001 7 Write RFCR and TFCR with 0x10 for normal operation 8 Write MRBLR with the maximum number of bytes per receive buffer Assume 16 bytes so MRBLR 0x0010 9 Write MAX_IDL with 0x0000 in the SMC UART specific parameter RAM to disable the MAX_IDL functionality for ...

Page 814: ...ta causes a busy out of buffers condition since only one RxBD is ready 29 4 SMC in Transparent Mode Compared to the SCC in transparent mode the SMCs generally have less functionality simpler functions and slower speeds Transparent mode is selected by setting SMCMR SM to 0b11 Section 29 2 1 SMC Mode Registers SMCMRn describes other protocol specific bits in the SMCMR The SMC in transparent mode doe...

Page 815: ...nd the L bit is not set only R is cleared In both cases an interrupt is issued according to the I bit in the BD By appropriately setting the I bit in each BD interrupts can be generated after each buffer a specific buffer or each block is sent The SMC then proceeds to the next BD If no additional buffers have been presented to the SMC for transmission and the L bit was cleared an underrun is detec...

Page 816: ...of the state of SMSYN until REN is cleared Once SMCMR TEN is set the first rising edge of SMCLK that finds SMSYN low synchronizes the SMC transmitter which begins sending ones asynchronously from the falling edge of SMSYN After one character of ones is sent if the transmit FIFO is loaded the TxBD is ready with data data starts being send on the next falling edge of SMCLK after one character of one...

Page 817: ...ver transmitter after the frame sync indication rather than the falling edge of SMSYN Chapter 20 Serial Interface describes how to configure time slots The TSA allows the SMC receiver and transmitter to be enabled simultaneously and synchronized separately SMSYN does not provide this capability Figure 29 12 shows synchronization using the TSA SMCLK SMSYN SMTXD 1s are sent Five 1s are sent TEN set ...

Page 818: ...n is always synchronized to the beginning of that time slot If multiple time slots in a TDM frame are assigned to the SMC as shown in Figure 29 12 then synchronization depends on the order of initialization When the transmit FIFO is loaded synchronization and transmission begins depending on the following If a buffer is made ready before the SMC is enabled the first byte is placed in time slot 1 i...

Page 819: ... not advanced to the next BD no new BD is accessed and no new buffers are sent for this channel The transmitter sends idles until a RESTART TRANSMIT command is issued RESTART TRANSMIT Starts or resumes transmission from the current TBPTR in the channel TxBD table When the channel receives this command it polls the R bit in this BD The SMC expects this command after a STOP TRANSMIT is issued The ch...

Page 820: ...ding after a RESTART TRANSMIT command Underrun cannot occur between frames Overrun The SMC maintains an internal FIFO for receiving data If the buffer is in external memory the CP begins programming the SDMA channel when the first character is received into the FIFO If a FIFO overrun occurs the SMC writes the received data character over the previously received character The previous character and...

Page 821: ...d only by the W bit 3 I Interrupt 0 No interrupt is generated after this buffer is filled 1 SMCE RX is set when the CP completely fills this buffer indicating that the core must process the buffer The RX bit can cause an interrupt if it is enabled 4 5 Reserved should be cleared 6 CM Continuous mode 0 Normal operation 1 The CP does not clear E after this BD is closed allowing the buffer to be overw...

Page 822: ... error occurs 1 The user prepared buffer is not sent or is being sent BD fields must not be updated if R is set 1 Reserved should be cleared 2 W Wrap final BD in table 0 Not the last BD in the table 1 Last BD in the table After this buffer is used the CP transmits outgoing data from the first BD that TBASE points to The number of TxBDs in this table is programmable and determined by the W bit 3 I ...

Page 823: ...er pin functions are the timers or the TSA These alternate functions cannot be used on this pin 3 Connect CLK3 to SMC1 using the SI Clear SIMODE SMC1 and set SIMODE SMC1CS to 0b110 0 2 3 4 5 6 7 Field TXE BSY TX RX Reset 0 R W R W Address 0xA86 SMCE1 0xA96 SMCE2 0xA8A SMCM1 0xA9A SMCM2 Figure 29 15 SMC Transparent Event Register SMCE Mask Register SMCM Table 29 16 SMCE SMCM Field Descriptions Bits...

Page 824: ...ld also be initialized 14 Write 0x3830 to the SMCMR to configure 8 bit characters unreversed data and normal operation not loopback The transmitter and receiver are not enabled yet 15 Write 0x3833 to the SMCMR to enable the SMC transmitter and receiver This additional write ensures that TEN and REN are enabled last After 5 bytes are sent the TxBD is closed after 16 bytes are received the receive b...

Page 825: ...on of GCI one SMC can handle SCIT channel 0 and the other can handle SCIT channel 1 The main features of the SMC in GCI mode are as follows Each SMC channel can support both the C I and monitor channels of the GCI IOM 2 in ISDN applications Two SMCs support both sets of C I and monitor channels in SCIT channels 0 and 1 Full duplex operation Local loopback and echo capability for testing To use the...

Page 826: ...d A TRANSMIT ABORT REQUEST command causes the MPC885 to send an abort request on the E bit 29 5 3 Handling the GCI C I Channel The C I channel is used to control the OSI layer 1 device The OSI layer 2 device in the TE sends commands and receives indication to or from the upstream layer 1 device through C I channel 0 In the SCIT configuration C I channel 1 is used to convey real time status informa...

Page 827: ...receiver command can be issued when the MPC885 implements the monitor channel protocol When it is issued the MPC885 sends an abort request on the A bit TIMEOUT This transmitter command can be issued when the MPC885 implements the monitor channel protocol It is usually issued because the device is not responding or A bit errors are detected The MPC885 sends an abort request on the E bit at the time...

Page 828: ...7 8 15 Offset 0 R L AR Data Figure 29 17 SMC GCI Monitor Channel TxBD Table 29 20 SMC Monitor Channel TxBD Field Descriptions Bits Name Description 0 R Ready 0 Cleared by the CP after transmission The TxBD is now available to the core 1 Set by the core when the data byte associated with this BD is ready for transmission 1 L Last EOM When L 1 the SMC first transmits the buffer data and then transmi...

Page 829: ... 29 21 SMC C I Channel RxBD Field Descriptions Bits Name Description 0 E Empty 0 Cleared by the CP to indicate that the byte associated with this BD is available to the core 1 The core sets E to indicate that the byte associated with this BD has been read Note that additional data received is discarded until E bit is set 1 7 Reserved should be cleared 8 13 C I Data Command indication data bits For...

Page 830: ...MC GCI Event Register SMCE Mask Register SMCM Table 29 23 SMCE SMCM Field Descriptions Bits Name Description 0 3 Reserved should be cleared 4 CTXB C I channel buffer transmitted Set when the C I transmit buffer becomes empty 5 CRXB C I channel buffer received Set when the C I receive buffer becomes full 6 MTXB Monitor channel buffer transmitted Set when the monitor transmit buffer becomes empty 7 ...

Page 831: ...me clock which is derived from the SPI baud rate generator in master mode and generated externally in slave mode During an SPI transfer data is sent and received simultaneously Because the SPI receiver and transmitter are double buffered as shown in Figure 30 1 the effective FIFO size latency is 2 characters The SPI s msb is shifted out first When the SPI is disabled in the SPI mode register SPMOD...

Page 832: ...d Four combinations of SPICLK phase and polarity can be configured with SPMODE CI CP SPI signals can also be configured as open drain to support a multimaster configuration in which a shared SPI signal is driven by the MPC885 or an external SPI device The SPI master in slave out SPIMISO signal acts as an input for master devices and as an output for slave devices Conversely the master out slave in...

Page 833: ... which sends back a simultaneous reply A single master MPC885 with multiple slaves can use general purpose parallel I O signals to selectively enable slaves as shown in Figure 30 2 To eliminate the multimaster error in a single master environment the master s SPISEL input can be forced inactive by selecting port B 31 for general purpose I O PBPAR DD31 0 Figure 30 2 Single Master Multi Slave Config...

Page 834: ...transfers the slave s core writes data to be sent into a buffer configures a TxBD with TxBD R set and configures one or more RxBDs The core then sets SPCOM STR to activate the SPI Once SPISEL is asserted the slave shifts data out from SPIMISO and in through SPIMOSI A maskable interrupt is issued when a full buffer finishes receiving and sending or after an error The SPI uses successive RxBDs in th...

Page 835: ... SELOUT0 SPISEL SPICLK SELOUT3 SELOUT2 SPI 0 Notes All signals are open drain For a multi master system with more than two masters SPISEL and SPIE MME It is the responsibility of software to arbitrate for the SPI bus with token passing for example will not detect all possible conflicts SELOUTx signals are implemented in software with general purpose I O signals SPISEL1 SPISEL0 SPISEL3 SPISEL2 SPIM...

Page 836: ...vert Inverts SPI clock polarity See Figure 30 5 and Figure 30 6 0 The inactive state of SPICLK is low 1 The inactive state of SPICLK is high 3 CP Clock phase Selects the transfer format See Figure 30 5 and Figure 30 6 0 SPICLK starts toggling at the middle of the data transfer 1 SPICLK starts toggling at the beginning of the data transfer 4 DIV16 Divide by 16 Selects the clock source for the SPI b...

Page 837: ... and 1111 16 bits A value less than 4 causes erratic behavior If the value is not greater than a byte every byte in memory holds LEN valid bits If the value is greater than a byte every half word holds LEN valid bits See Section 30 4 1 2 SPI Examples with Different SPMODE LEN Values 12 15 PM Prescale modulus select Specifies the divide ratio of the prescale divider in the SPI clock generator BRGCL...

Page 838: ...ring transmitted is firstnmlk_jihg__vuts_rqpo last with REV 1 the string is transmitted firstghij_klmn__opqr_stuv last Example 3 with LEN 0xC data size 13 the following data is selected msb ghij_klmn__xxxr_stuv lsb with REV 0 the string transmitted firstnmlk_jihg__vuts_r last with REV 1 the string is transmitted firstghij_klmn__r_stuv last 30 4 2 SPI Event Mask Registers SPIE SPIM The SPI event re...

Page 839: ... transmission 4 Reserved should be cleared 5 BSY Busy Set after the first character is received but discarded because no Rx buffer is available 6 TXB Tx buffer Set when the Tx data of the last character in the buffer is written to the Tx FIFO Wait two character times to be sure data is completely sent over the transmit signal 7 RXB Rx buffer Set after the last character is written to the Rx buffer...

Page 840: ...o be sent is programmed in TxBD Data Length MRBLR is not intended to be changed while the SPI is operating However it can be changed in a single bus cycle with one 16 bit move not two 8 bit bus cycles back to back The change takes effect when the CPM moves control to the next RxBD To guarantee the exact RxBD on which the change occurs change MRBLR only while the SPI receiver is disabled MRBLR shou...

Page 841: ...elp experienced users in debugging 0 2 3 4 5 7 Field BO AT 1 3 Reset 0000_0000 R W R W Addr SPI Base 04 RFCR SPI Base 05 TFCR Figure 30 9 Receive Transmit Function Code Registers RFCR TFCR Table 30 6 RFCR TFCR Field Descriptions Bits Name Description 0 Reserved should be cleared 3 4 BO Byte ordering Set BO to select the required byte ordering for the buffer If BO is changed on the fly it takes eff...

Page 842: ...igure 30 11 and Figure 30 12 has the following structure The half word at offset 0 contains status and control bits The CPM updates the status bits after the buffer is sent or received Table 30 7 SPI Commands Command Description INIT TX PARAMETERS Initializes all transmit parameters in the parameter RAM to their reset state and should be issued only when the transmitter is disabled The INIT TX AND...

Page 843: ...rnal or external memory For a TxBD the pointer can be even or odd unless the character exceeds 8 bits for which it must be even The buffer can be in internal or external memory 30 7 1 1 SPI Receive BD RxBD The CPM uses RxBDs to report on each received buffer It closes the current buffer generates a maskable interrupt and starts receiving data in the next buffer once the current buffer is full The ...

Page 844: ...n the buffer 0 This buffer does not contain the last character of the message 1 This buffer contains the last character of the message 5 Reserved should be cleared 6 CM Continuous mode Master mode only in slave mode CM should be cleared 0 Normal operation 1 The CPM does not clear RxBD E after this BD is closed the buffer is overwritten when the CPM next accesses this BD This allows continuous rece...

Page 845: ...BD in the table 1 Last BD in the table After this buffer is used the CPM receives incoming data using the BD pointed to by TBASE top of the table The number of BDs in this table is determined only by the W bit 3 I Interrupt 0 No interrupt is generated after this buffer is processed if an error does not occur 1 SPIE TXB or SPIE TXE are set when this buffer is processed and causes interrupts if not ...

Page 846: ...x37 to SPIM to enable all possible SPI interrupts 12 Write 0x0000_0020 to the CPM interrupt mask register CIMR This sets CIMR SPI to enable SPI generated system interrupts The CICR should also be initialized 13 Write 0x0370 to SPMODE to enable normal operation not loopback master mode SPI enabled 8 bit characters and the fastest speed possible 14 Clear PBDAT 156 assuming PB156 is chosen above to c...

Page 847: ...e SPI enabled and 8 bit characters Baud rate generator speed is ignored in slave mode 13 Set SPCOM STR to enable the SPI to be ready once the master begins the transfer Note that if the master sends 3 bytes and negates SPISEL the RxBD is closed but the TxBD remains open If the master sends 5 or more bytes the TxBD is closed after the fifth byte If the master sends 16 bytes and negates SPISEL the R...

Page 848: ...Serial Peripheral Interface SPI MPC885 PowerQUICC Family Reference Manual Rev 2 30 18 Freescale Semiconductor ...

Page 849: ...t connection between the host and a hub or function or a hub connected to another hub or a function The USB transfers signal and power over a four wire cable and the signalling occurs over two wires and point to point segments The USB full speed signalling bit rate is 12 Mbps Also a limited capability low speed signalling mode is defined at 1 5 Mbps Refer to the USB Specification Revision 1 1 and ...

Page 850: ...RC5 is calculated on 11 bits this task should not impose much software overhead Retransmission after an error and error recovery Generation and transmission of an SOF start of frame token every 1 ms Scheduling the various transfers within and between frames Because the MPC885 USB host controller does not integrate the root hub an external hub is required when more than one device is connected to t...

Page 851: ... MHz for a 12 Mbps full speed transfer or 6 MHz for a 1 5 Mbps low speed transfer There are six I O pins associated with the USB port Their functionality is described in Table 31 1 Additional control lines that might be needed by some transceivers e g speed select low power control may be supported by general purpose output lines Table 31 1 USB Pins Functions Signal I O Function USBTXN USBTXP O Ou...

Page 852: ...s four independent FIFOs each containing 16 bytes There is a dedicated FIFO for each of the four supported endpoints The USB receiver has a single 16 byte FIFO USBRXD I Receive data Input to the USB receiver from the differential line receiver USBRXP USBRXN I Gated version of D and D Used to detect single ended zeros and the interconnect speed Table 31 1 USB Pins Functions continued Signal I O Fun...

Page 853: ...gramming the endpoint registers refer to Section 31 11 3 USB Endpoint Registers USEP0 USEP3 NOTE It is mandatory that endpoint 0 be configured as a control transfer type This endpoint is used by the USB system software as a control pipe Additional control pipes may be provided by other endpoints Once enabled the USB function controller looks for valid token packets Figure 31 3 and Table 31 2 descr...

Page 854: ...of the packet to its buffer The entire packet including the DATA0 DATA1 PID is written to the receive buffers Software must check data packet synchronization by monitoring the DATA0 DATA1 PID sequence toggle If the packet reception has no CRC or bit stuff errors the USB receiver sends the handshake selected in the endpoint configuration register USEPn RHS see table below to the host If an error oc...

Page 855: ...is sent the USB controller waits for a handshake packet If the host fails to acknowledge the packet the timeout status bit TxBD TO is set Software must set the proper DATA0 DATA1 PID in the transmitted packet USB In Token Reception USEPn THS FIFO Loaded Handshake Sent to Host 00 Normal No NAK Yes Data packet is sent 01 Ignore None 10 NAK NAK 11 STALL STALL SETUP The format of setup transactions is...

Page 856: ...oints Each endpoint can be configured to support either control interrupt bulk or isochronous transfers modes This is done by programming the endpoint registers refer to Section 31 11 3 USB Endpoint Registers USEP0 USEP3 Endpoint 0 must be used for host transactions After reset the host should enumerate the functions in the system The enumeration process is done by software Once enabled the USB ho...

Page 857: ... is controlled by LSS in USMOD Figure 31 5 USB Controller Operating Modes The SOF transaction is initiated and generated using a CPM timer and a microcode routine Once the SOF token is loaded to the host FIFO it is transmitted as is When the TEST bit is programmed in the USMOD register both the host state machine and the function state machine are active Endpoints 1 3 receive transmit data accordi...

Page 858: ... fetches a TxBD containing an IN token and loads the token to FIFO After the IN token is transmitted the USB host controller waits for reception of data within expected time interval On reception of a correct DATA PID an RxBD is fetched The received data and DATA PID are stored in the receive FIFO If RxBD E is set PID data will be moved to the buffer While receiving the data the USB host controlle...

Page 859: ...actions prior to the 1 ms tick Figure 31 6 SOF Generation DREQ0 should be configured as external interrupt When there are no hardware originated requests to the CP it enters stall state Configuring DREQ0 as an external interrupt request ensures that only a hardware interrupt request can wake up the host controller 31 8 USB Function and Host Parameter RAM Memory Map The USB controller parameter RAM...

Page 860: ... 32 in the dual port RAM See Figure 31 8 The map of the endpoint parameter block is shown in Table 31 4 Note When USB host mode is set EP0PTR must be used for the host endpoint USB Base 02 EP1PTR Half Word USB Base 04 EP2PTR Half Word USB Base 06 EP3PTR Half Word USB Base 08 RSTATE Word Receive internal state Reserved for CP use only Should be cleared before enabling the USB controller USB Base 0C...

Page 861: ...16 bit move not two 8 bit bus cycles back to back Transmit buffers for the USB controller are not affected by the MRBLR value Transmit buffer lengths can vary individually as needed The number of bytes to be sent is chosen by programming TxBD Data Length 0x08 RBPTR 16 bits RxBD pointer Points to the next BD the receiver will transfer data to when it is in an idle state or to the current BD while p...

Page 862: ...ved The software should prepare the frame number and the crc and place it in FRAME_N field 0x1C TXUSBU_PTR 16 bits Tx microcode return address temp 0x1E 16 bits Reserved 1 Offset from endpoint parameter block base 2 Note that the items in boldface should be initialized by the user 3 These parameters need not be accessed in normal operation but may be helpful for debugging 0 1 4 5 15 Field V1 1 Thi...

Page 863: ...FCR control the value that the user wants to appear on the address type pins AT1 AT3 when the associated SDMA channel accesses memory as well as the required byte ordering for the data buffer Figure 31 11 shows the USB function code registers 0 1 4 5 15 Field CRC5 FRAME NUMBER Reset 0000_0000_0000_0000 R W R W Addr USB base 0x10 Figure 31 10 Frame Number FRAME_N in HOST mode Table 31 6 FRAME_N in ...

Page 864: ...rder of bytes within a buffer word is reversed as compared to the Motorola mode This mode is supported only for 32 bit port size memory 01 PowerPC little endian byte ordering As data is transmitted onto the serial line from the data buffer the least significant byte of the buffer double word contains data to be transmitted earlier than the most significant byte of the same buffer double word 1X Mo...

Page 865: ... bit should be used if the function wants to exit the suspend state 2 3 Reserved should be cleared 4 SFTE 0 The external interrupt from the I O passes through to the CPM controller 1 Timer1 is used to generate the SOF signal The events from this timer are used as the CPM external interrupt instead of the signal that arrives from the I O 5 TEST USB controller test loopback mode 0 Test mode is disab...

Page 866: ...function controller 00 Control 01 Interrupt 10 Bulk 11 Isochronous Transfer mode for USB host controller 00 Control interrupt bulk 11 Isochronous 8 9 Reserved should be cleared Reserved should be cleared 10 MF Enable multi frame For USB function controller allows loading of the next transmit packet into the FIFO before transmission completion of the previous packet 0 Transmit FIFO may hold only on...

Page 867: ... 00 Normal handshake 0 1 2 5 6 7 Field STR FLUSH EP Reset 0000_0000 R W R W Addr 0xA02 Figure 31 15 USB Command Register USCOM Table 31 11 USCOM Fields Bits Name Description 0 STR Start FIFO fill Setting the STR bit to one causes the USB controller to start the filling the corresponding endpoint transmit FIFO with data Transmission will begin once the IN token for this endpoint is received The STR...

Page 868: ... 13 14 15 Field RESET IDLE TXE4 TXE3 TXE2 TXE1 SOF BSY TXB RXB Reset 0000_0000_0000_0000 R W R W Addr 0xA10 Figure 31 16 USB Event Register USBER Table 31 12 USBER Fields Bit Name Description 0 5 Reserved should be cleared 6 RESET Reset condition detected USB reset condition was detected asserted 7 IDLE IDLE status changed A change in the status of the serial line was detected The real time suspen...

Page 869: ... configuration as those used by the SCCs and SMCs There are four separate transmit BD rings and four separate receive BD rings one for each endpoint The BD ring allows the user to define buffers for transmission and buffers for reception Each BD ring forms a circular queue The CP confirms reception and transmission or indicates error conditions using the BDs to inform the processor that the buffer...

Page 870: ...DESCRIPTORS TX DATA BUFFER RX DATA BUFFER EP0 RxBD TABLE POINTER EP0 TxBD TABLE POINTER FRAME STATUS DATA LENGTH DATA POINTER TX BUFFER DESCRIPTORS TX DATA BUFFER ENDPOINT 3 TxBD TABLE ENDPOINT 0 TxBD TABLE ENDPOINT 0 RxBD TABLE ENDPOINT 3 RxBD TABLE EP3 RxBD TABLE POINTER EP3 TxBD TABLE POINTER FRAME STATUS DATA LENGTH DATA POINTER RX BUFFER DESCRIPTORS FRAME STATUS DATA LENGTH DATA POINTER RX BU...

Page 871: ...4 15 OFFSET 0 E W I L F PID NO AB CR OV OFFSET 2 DATA LENGTH OFFSET 4 RX DATA BUFFER POINTER OFFSET 6 Figure 31 19 USB Receive Buffer Descriptor RxBD 1 2 1 Entries in boldface must be initialized by the user 2 All fields should be written by the CPU core before enabling the USB Table 31 14 USB RxBD Fields Offset Bit Name Description 0x00 0 E Empty 0 The data buffer associated with this RxBD has be...

Page 872: ...ontroller after the received data has been placed into the associated data buffer 00 Buffer contains DATA0 packet 01 Buffer contains DATA1 packet 10 Buffer contains SETUP packet This option can never be set on host RxBD 10 Reserved should be cleared 11 NO Rx non octet aligned packet A packet that contained a number of bits not exactly divisible by eight was received Written by the USB controller a...

Page 873: ...s this bit after the buffer has been transmitted or after an error condition is encountered 1 The data buffer which has been prepared for transmission by the user has not been transmitted or is currently being transmitted No fields of this BD may be written by the user once this bit is set 1 Reserved should be cleared 2 W Wrap Final BD in Table 0 This is not the last BD in the TxBD table 1 This is...

Page 874: ... is valid for the first BD of a packet otherwise it is ignored 0X Do not append PID to the data 10 Transmit DATA0 PID before sending the data 11 Transmit DATA1 PID before sending the data 10 12 Reserved should be cleared 13 TO1 Time out Indicates that the host failed to acknowledge the packet 14 UN 1 Underrun Indicates that the USB encountered a transmitter underrun condition while sending the buf...

Page 875: ...upts if they are enabled 4 L Last 0 Buffer does not contain the last byte of the message 1 Buffer contains the last byte of the message 5 TC Transmit CRC Valid only when the L bit is set otherwise it is ignored Prepare TC before sending data 0 Transmit end of packet after the last data byte This setting can be used for testing purposes to send a bad CRC after the data 1 Transmit the CRC sequence a...

Page 876: ...he USB This command is expected by the USB controller after a STOP Tx Command or after transmission error underrun or time out 0x00 cont 11 NAK1 NAK received Indicates that the endpoint has responded with a NAK handshake The packet was received error free however the endpoint could not accept it 12 STAL 1 STALL received Indicates that the endpoint has responded with a STALL handshake The endpoint ...

Page 877: ...f an IN token is received but the corresponding endpoint s transmit FIFO is empty or if the target endpoint is configured to NAK or STALL The controller sets USBER TXEn reception of nak or stall hand shake For USB host mode only If this error occurs the channel closes the buffer sets the corresponding status bit in the TxBD nak or stal and sets the TXE bit in the USB event register The host will r...

Page 878: ... up the TxBD Status and Control Data Length fields of endpoint 1 11 Write DPRAM 0x210 to DPRAM 0x2C to set up the TxBD Buffer Pointer field of endpoint 1 12 Write 0xBC80_0004 to DPRAM 0x30 to set up the TxBD Status and Control Data Length fields of endpoint 2 13 Write DPRAM 0x220 to DPRAM 0x34 to set up the TxBD Buffer Pointer field of endpoint 2 14 Write 0xBCC0_0004 to DPRAM 0x38 to set up the Tx...

Page 879: ... TSTATE field of the endpoint 3 parameter RAM 36 Write 0x0000 to USEP0 for control transfer one packet only and manual handshake 37 Write 0x1200 to USEP1 for bulk transfer one packet only and manual handshake 38 Write 0x2200 to USEP2 for bulk transfer one packet only and manual handshake 39 Write 0x3200 to USEP3 for bulk transfer one packet only and manual handshake 40 Write 0x00 to the USMOD for ...

Page 880: ...Host Controller Initialization Example The following is a local loopback example initialization sequence for the USB controller operating as a host It can be used to set up endpoints 0 and 1 to fill up transmit FIFOs to demonstrate an IN token transaction 1 Enable CLK2 on proper cpm port CLK2 frequency should be 48 Mhz 2 Program SICR to connect CLK2 to the USB controller program SICR R4CS to 101 3...

Page 881: ...meter RAM 24 Write 0x0020 to USEP0 for the host control transfer multi packet 25 Write 0x1100 to USEP1 for endpoint 1 interrupt transfer one packet only 26 Write 0x06 to USMOD for full speed 12 Mbps signaling local loopback configuration test and host modes set and disable the USB 27 Write 0x05 to the USAD for slave address 5 28 Set USMOD EN to enable the USB controller 29 Write 0x81 to the USCOM ...

Page 882: ...Universal Serial Bus USB MPC885 PowerQUICC Family Reference Manual Rev 2 31 34 Freescale Semiconductor ...

Page 883: ...ck which is derived from the I2 C BRG when in master mode and generated externally when in slave mode Wait states are inserted during a data transfer if SCL is held low by a slave device In the middle of a data transfer the master I2C controller recognizes the need for wait states by monitoring SCL However the I2 C controller has no automatic time out mechanism if the slave device does not release...

Page 884: ...ts input from the BRG clock BRGCLK which is described in Section 14 3 Clock Signals SDA and SCL are bidirectional signals connected to a positive supply voltage through an external pull up resistor When the bus is free both signals are pulled high The general I2C master slave configuration is shown in Figure 32 2 Figure 32 2 I2 C Master Slave General Configuration When the I2 C controller is the m...

Page 885: ...lect master or slave mode for the controller using the I2 C command register I2COM M S Set the master s start bit I2COM STR to begin a transfer setting a slave s I2COM STR activates the slave to wait for a transfer request from a master If a master or slave transmitter s current TxBD L is set transmission stops once the buffer is sent that is I2COM STR must be set again to reactivate transfers If ...

Page 886: ...k operation for master write requests The master I2C controller simply issues a write request directed to its own address programmed in I2ADD The master s receiver monitors the transmission and reads the transmitted data into its receive buffer Loopback operation requires no special register programming 32 3 3 I2C Master Read Slave Write Before initiating a master read with the MPC885 prepare a tr...

Page 887: ...op condition is detected 32 3 4 I2 C Multi Master Considerations The I2 C controller supports a multi master configuration in which the I2 C controller must alternate between master and slave modes The I2 C controller supports this by implementing I2 C master arbitration in hardware However due to the nature of the I2C bus and the implementation of the I2C controller certain software consideration...

Page 888: ...rongly recommended to ensure consistent bit ordering across devices 3 GCD General call disable Determines whether the receiver acknowledges a general call address all zeros 0 General call address is enabled 1 General call address is disabled 4 FLT Clock filter Determines if the I2 C input clock SCL is filtered to prevent spikes in a noisy environment 0 SCL is not filtered 1 SCL is filtered by a di...

Page 889: ...d the I2 C controller sets the corresponding I2CER bit I2CER bits are cleared by writing ones writing zeros has no effect Setting a bit in the I2C mask register I2CMR enables and clearing a 0 6 7 Field SAD Reset Undefined R W R W Addr 0x864 Figure 32 7 I2C Address Register I2ADD Table 32 2 I2ADD Field Descriptions Bits Name Description 0 6 SAD Slave address 0 6 Holds the slave address for the I2 C...

Page 890: ...ription 0 2 Reserved and should be cleared 3 TXE Tx error Set when an error occurs during transmission 4 Reserved and should be cleared 5 BSY Busy Set after the first character is received but discarded because no Rx buffer is available 6 TXB Tx buffer Set when the Tx data of the last character in the buffer has been sent 7 RXB Rx buffer Set after the last character is written to the Rx buffer and...

Page 891: ...x05 TFCR Byte 0x06 MRBLR Hword Maximum receive buffer length Defines the maximum number of bytes the I2 C receiver writes to a receive buffer before moving to the next buffer The receiver writes fewer bytes to the buffer than the MRBLR value if an error or end of frame occurs Receive buffers should not be smaller than MRBLR Transmit buffers are unaffected by MRBLR and can vary in length the number...

Page 892: ...remented with every byte read by the SDMA channels 0x24 TTEMP Word Tx temp Reserved for CP use 0x28 0x2F Used for I2 C SPI relocation see Section 18 7 3 Parameter RAM 1 As programmed in I2C_BASE The default value is IMMR 0x3C80 See Section 18 7 3 Parameter RAM 2 Normally these parameters need not be accessed 0 2 3 4 5 7 Field BO AT 1 3 Reset 0000_0000 R W R W Addr I2C Base 04 RFCR I2C Base 05 TFCR...

Page 893: ...eive Commands Command Description INIT TX PARAMETERS Initializes all transmit parameters in the parameter RAM to their reset state Should be issued only when the transmitter is disabled The INIT TX AND RX PARAMETERS command can also be used to reset both the Tx and Rx parameters CLOSE RXBD Forces the I2 C controller to close the current Rx BD and use the next BD for subsequently received data If t...

Page 894: ...inning of the buffer For an RxBD the pointer must be even and can point to internal or external memory For a TxBD the pointer can be even or odd The buffer can reside in internal or external memory 32 7 1 1 I2 C Receive Buffer Descriptor RxBD Using RxBDs the CPM reports on each buffer received closes the current buffer generates a maskable interrupt and starts receiving data in the next buffer whe...

Page 895: ...I2 C controller sets L after all received data is placed into the associated buffer or because of a stop or start condition or an overrun 5 13 Reserved and should be cleared 14 OV Overrun Set when a receiver overrun occurs during reception The I2 C controller updates this bit after the received data is placed into the associated buffer 15 Reserved and should be cleared 0 1 2 3 4 5 6 12 13 14 15 Of...

Page 896: ...e of the buffer 1 Send a start condition before the first byte of the buffer Used to separate messages Note If this BD is the first one in a message when I2COM STR is triggered a start condition is sent regardless of the value of TxBD S 6 12 Reserved and should be cleared 13 NAK No acknowledge Indicates that the transmission was aborted because the last byte sent was not acknowledged The I2 C cont...

Page 897: ...y the CP or the core There are two handshake options for strobed I O Two interlocked handshake signals Supports level sensitive handshake control signals compatible with the advanced byte transfer mode of the P1284 protocol see Section 33 7 1 Interlocked Handshake Mode Two pulsed handshake signals Supports edge sensitive handshakes like those used for a Centronics interface see Section 33 7 2 Puls...

Page 898: ... register PBDAT the PIP asserts ACK through STBO strobe out on PB15 When the PIP is configured to send and the core writes PBDAT STB is driven low on STBO strobe out on PB15 When the destination device drives ACK low onto STBI strobe in on PB14 the PIP indicates that a character was successfully sent by flagging PIPE TCH For a core controlled PIP only the PIPC PIPE PIPM and port B registers need t...

Page 899: ...ctivity centers around the buffer descriptors Table 33 1 PIP Transmitter Parameter RAM Memory Map Offset1 Name Width Description 0x00 Hword Reserved for receiving 0x02 TBASE Hword PIP TxBD table base offset from the beginning of dual port RAM Initialize TBASE before enabling the channel TBASE should be divisible by 8 0x04 PFCR Byte PIP function code Appears on AT 1 3 when the associated SDMA chann...

Page 900: ...in software by reading the individual status signals for errors When receiving core software drives the status signals using general purpose outputs Bit 0 2 3 4 5 7 Field BO AT 1 3 Reset 0000_0000_0000_0000 R W R W Addr PIP base 0x04 Figure 33 2 PIP Function Code Register PFCR Table 33 2 PFCR Field Descriptions Bits Name Description 0 2 Reserved should be cleared 3 4 BO Byte ordering Set BO to sel...

Page 901: ...is ignored 1 SELECT status line is checked during transmission If a select error occurs indication is given in TxBD S and a TXE event is generated in the PIPE 7 Reserved should be cleared Table 33 4 PIP Receiver Parameter RAM Memory Map Offset 1 Name Width Description 0x00 RBASE Hword PIP Rx BD table base offset from the beginning of dual port RAM Initialize RBASE before enabling the channel RBASE...

Page 902: ...ansmitting 0x28 MAX_SL Hword Maximum silence period The PIP controller can be programmed to close the Rx buffer after a period of inactivity determined by MAX_SL The silence counter decrements every 1 024 system clocks If the counter reaches zero before new data arrives the Rx buffer closes Clearing MAX_SL disables this function 0x2A SL_CNT Hword Silence counter internal use 0x2C CHARACTER1 Hword ...

Page 903: ...f more data is in the message A maskable interrupt is generated 1 If this character is recognized it is written to RCCR and not to the Rx buffer A maskable interrupt is generated The current Rx buffer is not closed 2 7 Reserved 8 15 CHARACTERn Control character values 1 8 Defines control characters to be compared to the incoming character For characters smaller than 8 bits the most significant bit...

Page 904: ...from PIP base address PIP base IMMR 0x3F80 SMC2 0 1 3 4 5 6 7 8 9 10 11 12 13 14 15 Field STR SACK CBSY SBSY EBSY TMOD MODL MODH HSC T R Reset 0000_0000_0000_0000 R W R W Addr 0xAB2 Figure 33 5 PIP Configuration Register PIPC Table 33 6 PIPC Field Descriptions Bits Name Description 0 STR Start transmit Applies when T R 1 Tx operation Setting STR causes the CP to poll the TxBD table looking for the...

Page 905: ...kes effect only if BUSY is configured as a PIP input PBPAR 31 PBDIR 31 0 8 9 TMOD Timing mode Used to implement a Centronics type receiver Valid only when T R 0 Rx operation and MODH 11 pulsed handshake For the definition of these timing modes see Section 33 7 2 2 Pulsed Handshake Timing 00 PIP receiver timing mode 0 01 PIP receiver timing mode 1 10 PIP receiver timing mode 2 11 PIP receiver timin...

Page 906: ...2 Reserved should be cleared 3 TXE Transmit error Indicates a general transmit error the source of the specific error can be read in the current buffer descriptor s status and control field see Section 33 5 1 The PIP Tx Buffer Descriptor TxBD 4 CCR Control character received A control character was received and stored in the received control character register RCCR in the PIP parameter RAM 5 BSY B...

Page 907: ...data signals PBDAT as inputs or outputs The direction settings for the handshake signals PB14 and PB15 are ignored See Section 34 3 1 3 Port B Data Direction Register PBDIR Port B data register PBDAT register functions as the PIP data register when the PIP is used Use this register to receive or transmit PIP data when the PIP is controlled by core software See Section 34 3 1 2 Port B Data Register...

Page 908: ...The word at offset 4 points to the beginning of the buffer For an RxBD the value must be even and can reside in internal or external memory For a TxBD this pointer can be even or odd unless the port size exceeds 8 bits for which it must be even The buffer can reside in internal or external memory 33 5 1 The PIP Tx Buffer Descriptor TxBD The CP uses buffer descriptors TxBDs to confirm buffer transm...

Page 909: ... by the CP which can cause an interrupt 4 L Last 0 Not the last buffer of the frame 1 Last buffer of the frame 5 Reserved and should be cleared 6 CM Continuous mode 0 Normal operation 1 The CP does not clear R after this buffer is closed allowing the associated buffer to be resent when the CP next accesses this BD However R is cleared if an error occurs during transmission 7 11 Reserved should be ...

Page 910: ...CP fills this buffer signaling the core to process the buffer The RXB bit causes an interrupt if not masked 4 C Control character 0 This buffer does not contain a control character 1 This buffer has a user defined control character as its last byte 5 Reserved and should be cleared 6 CM Continuous mode 0 Normal operation 1 The E bit is not cleared by the CP after this buffer is closed thus allowing...

Page 911: ...col advanced byte mode transfers To connect MPC8xxs using this interface connect STBO from one microprocessor to the STBI of the other and connect the appropriate data signals either PB 23 16 or PB 31 16 When the PIP is transmitting the CP loads data into the output latch when it receives a request from the core to begin transfers Once data is loaded STB is asserted after a programmable setup time...

Page 912: ...he PIP uses STB to latch input data and ACK to acknowledge the transfer The timing of ACK is also programmable The core configures the PIP to implement a Centronics protocol by programming the PIP configuration PIPC register When the PIP is under CP control timing attributes are set in PTPR Transmit and receive errors are reported through BDs For information about supporting a Centronics interface...

Page 913: ...re can also control the assertion and negation of BUSY via PIPC see Section 33 4 1 PIP Configuration Register PIPC BUSY is multiplexed onto PB31 It can be used only with the 8 bit PIP interface not the 16 bit interface A PIP transmitter can be configured to ignore BUSY or suspend assertion of the STB output until the receiver BUSY signal is negated 33 7 2 2 Pulsed Handshake Timing When the PIP is ...

Page 914: ...ing the relative timing of BUSY to ACK Figure 33 15 through Figure 33 18 show how the definitions of TPAR1 and TPAR2 vary for each receiver mode The receiver mode is selected in PIPC TMOD see Table 33 6 Figure 33 15 PIP Receiver Timing Mode 0 Figure 33 16 PIP Receiver Timing Mode 1 Figure 33 17 PIP Receiver Timing Mode 2 STB Data TPAR1 TPAR2 ACK BUSY TPAR1 TPAR2 PB31 ACK BUSY TPAR1 TPAR2 PB31 ACK ...

Page 915: ...nsparent Transfers 33 9 Implementing Centronics The PIP can implement a Centronics compatible interface for both sending and receiving The Centronics protocol is a parallel peripheral interface for communicating between a host computer and a printer To implement Centronics the PIP uses an 8 bit data bus two handshake signals that control the data exchange and signals that reflect the peripheral de...

Page 916: ... prepared and PIPC STR is set the PIP processes the next ready BD in the TxBD table When configured for a Centronics interface the PIP transmitter fetches data from memory and starts sending to the printer Assuming the corresponding status mask bits are set in SMASK the PIP transmitter checks the printer status lines SELECT PERROR and FAULT for Tx errors before each transfer Configure PB30 PB29 an...

Page 917: ...able If rejected the character is written to the received control character register RCCR in the PIP Rx parameter RAM and a maskable Table 33 13 Centronics Tx Errors Error Description BD Not Ready The current BD to be processed is not ready PIPE TXE is flagged The channel continues sending after S W prepares the BD and sets PIPC STR Printer Off Line The printer is off line TxBD S and PIPE TXE are ...

Page 918: ... are not automatically generated they are controlled by software and driven on general purpose outputs Figure 33 22 PIP as a Centronics Receiver 33 9 2 1 Centronics Rx Errors and the PIPE The Centronics receiving error is described in Table 33 14 The relevant PIPE event bits for Centronics receiving are CCR BSY RCH and RXB see Section 33 4 2 PIP Event Register PIPE For core controlled receiving on...

Page 919: ...nals Port E is for general purpose I O shared with the signals used by the TDM the MII and Reduced MII interfaces and SCC 3 4 The read write port signals can be configured as inputs or outputs with a latch for data output They can be configured to be either general purpose I O or dedicated peripheral signals Regardless of the programmed function the I O signals state can always be read from their ...

Page 920: ...pplied and Power ON Reset POR is asserted All ports have alternate on chip peripheral functions and all signal values can be read while the signal is connected to an on chip peripheral Ports A B and E have open drain capability Port C has 12 interrupt input signals 34 2 Port A Port A signals are configured as follows in the port A pin assignment register PAPAR General purpose I O signal the corres...

Page 921: ...als with serial channel output capability are configured in a normal or wired OR configuration Setting the PAODR bits configure the signals for open drain operation PA9 PORT A9 RXD3 L1TXDA RXD3 TXD3 PA8 PORT A8 TXD3 L1RXDA L1RXDA GND PA7 PORT A7 CLK1 TIN1 L1RCLKA2 BRGO1 CLK1 TIN1 L1RCLKA BRGO1 PA6 PORT A6 CLK2 TOUT1 CLK2 GND PA5 PORT A5 CLK3 TIN2 L1TCLKA2 BRGO2 CLK3 TIN2 L1TCLKA BRGO2 PA4 PORT A4 ...

Page 922: ... direction register PADIR bits configure port A signals as general purpose inputs or outputs If a signal is not programmed for general purpose I O PADIR selects the peripheral function to be performed 0 7 8 9 10 11 12 13 14 15 Field OD8 OD9 OD10 OD11 OD12 OD14 Reset 0 R W R W Addr 0x954 Figure 34 1 Port A Open Drain Register PAODR Table 34 2 PAODR Bit Descriptions Bits Name Description 0 7 13 15 R...

Page 923: ...R W R W R W R W R W R W R W R W R W R W R W R W R W R W Addr 0x950 Figure 34 3 Port A Data Direction Register PADIR Table 34 4 PADIR Bit Descriptions Bits Name Description 0 15 DRn Port A data direction Configures port A signals as inputs or outputs when functioning as general purpose I O otherwise used to select the peripheral function 0 Select the signal for general purpose input or select perip...

Page 924: ... to BRG01 Chapter 20 Serial Interface describes CLK1 and L1RCLKA PA4 can be configured as a general purpose I O signal but not an open drain signal If PADIR DR4 0 PA4 can be CTS4 If DR4 1 PA4 can be MII1 TXD1 or RMII1 TXD1 If PA4 is a general purpose I O signal the CTS4 can be input from PC7 34 2 3 Port A Functional Block Diagrams Using PA15 as an example Figure 34 5 shows the functional block dia...

Page 925: ...ted as a general purpose I O signal it can be accessed through the PBDAT where data is stored in an output latch If a port B signal is configured as an output the output latch data is gated onto the port signal When PBDAT is read the port signal itself is read All port B signals can have multiple configurations which include on chip peripheral functions for UTOPIA SPI I2 C SMCs and the TDMs Port B...

Page 926: ...t B29 SPIMOSI SPIMOSI V DD PB28 Port B28 BRGO4 SPIMISO SPIMISO SPIMOSI PB27 Port B27 BRGO1 I2CSDA I2CSDA V DD PB26 Port B26 BRGO2 I2CSCL I2CSCL GND PB25 Port B25 SMTXD1 RxAddr 3 TxAddr 3 PB24 Port B24 SMRXD1 TxAddr 3 RxAddr 3 SMRXD1 GND PB23 Port B23 SMSYN1 TxAddr 2 SDACK1 RxAddr 2 SMSYN1 GND PB22 Port B22 SMSYN2 TxAddr 4 SDACK2 RxAddr 4 SMSYN2 GND PB21 Port B21 SMTXD2 TxAddr 1 BRG01 RxAddr 1 PB20...

Page 927: ...aring the written data with the data on the signal Data written to PBDAT is latched if the corresponding PBDIR bit is configured as an output the latched value is driven onto its respective signal PBDAT can be read or written at any time and is not initialized This register is affected by HRESET and SRESET 0 15 Field Reset 0000_0000_0000_0000 R W Addr 0xAC0 16 17 18 19 20 21 22 23 24 25 26 27 28 2...

Page 928: ...r 0xAC4 Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Reset Undefined R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Addr 0xAC6 Figure 34 8 Port B Data Register PBDAT Table 34 8 PBDAT Bit Descriptions Bits Name Description 0 13 Reserved 14 31 Dn Contains the data on the corresponding signal 0 13 14 15...

Page 929: ...nput or select peripheral function 0 1 Select the signal for general purpose output or select peripheral function 1 DR14 and DR15 are ignored when port B is used by the PIP controller 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field DD14 DD15 Reset 0 0 R W R W R W Addr 0xABC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 ...

Page 930: ...al is configured as an output port C interrupts are not generated 1 Write the corresponding PCPAR bit with a 0 2 Write the corresponding PCDIR bit with a 1 3 Write the corresponding PCSO bit with a zero for clarity 4 The corresponding PCINT bit is a don t care Table 34 11 Port C Pin Assignment Signals PCPAR DDn 0 PCPAR DDn 1 Input to On Chip Peripherals Default PCDIR DRn 1 or PCSO n 0 PCDIR DRn 0 ...

Page 931: ...ndently in the CPM interrupt mask register CPMR See Section 35 5 3 CPM Interrupt Mask Register The following steps configure a port C signal as a general purpose input that generates an interrupt 1 Write the corresponding PCPAR bit with a 0 2 Write the corresponding PCDIR bit with a 0 3 Write the corresponding PCSO bit with a 0 4 Set the PCINT bit to determine which edges cause interrupts 5 Write ...

Page 932: ...s register PCSO determines whether certain port C signals can connect to on chip peripherals and generate an interrupt at the same time The remaining port C registers PCDAT PCDIR and PCPAR have the same functions as their counterparts on ports A and B Port C has no open drain capability 34 4 1 1 Port C Data Register PCDAT When read the port C data PCDAT register always reflects the current status ...

Page 933: ...d 4 15 DRn Port C data direction Configures port C signals as inputs or outputs when functioning as general purpose I O otherwise used with PCSO to select the peripheral function 0 Select the signal for general purpose input or select peripheral function 0 1 Select the signal for general purpose output or select peripheral function 1 0 3 4 5 6 7 8 9 10 11 12 13 14 15 Field DD4 DD5 DD6 DD7 DD8 DD9 ...

Page 934: ...sponding SCC input as well as being a general purpose interrupt signal 5 7 9 CTSx Clear to send 0 PCx is a general purpose interrupt I O signal The SCC internal CTSx signal is always asserted If PCDIR configures this signal as an input the signal can generate an interrupt to the core as controlled by the PCINT bits 1 PCx is connected to the corresponding SCC input as well as being a general purpos...

Page 935: ...nable DMA request to the CPM Set DREQx only if IDMA is being used Note that the IDMA request function and the general purpose interrupt function operate concurrently and independently 0 PCx is a general purpose interrupt I O signal If PCDIR configures this signal as an input the signal can generate an interrupt to the core as controlled by the PCINT bits 1 As well as being a general purpose interr...

Page 936: ...described in Chapter 45 Fast Ethernet Controller FEC 34 5 1 Port D Registers Port D has three memory mapped read write control registers 34 5 1 1 Port D Data Register A read of the port D data PDDAT register returns the value of the signal regardless of whether it is an input or output This allows output conflicts to be found on the signal by comparing the written data with Table 34 18 Port D Pin ...

Page 937: ...R W Addr 0x976 Figure 34 16 Port D Data Register PDDAT Table 34 19 PDDAT Bit Descriptions Bits Name Description 0 2 Reserved 3 15 Dn Contains the data on the corresponding signal 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field OD8 OD10 DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 Reset 0000_0000_0000_0000 R W R W Addr 0x970 Figure 34 17 Port D Data Direction Register PDDIR Table 34 20 PDDIR...

Page 938: ...s general purpose inputs Table 34 22 describes port E signal options If a port E signal is selected as a general purpose I O signal it can be accessed through the PEDAT where data is stored in an output latch If a port E signal is configured as an output the output latch data is gated onto the port signal When PEDAT is read the port signal itself is read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field...

Page 939: ...MII1 RXCLK CLK8 L1TCLKB PD5 PE30 Port E30 L1RXDB MII1 RXD2 GND PE29 Port E29 MII2 CRS GND PE28 Port E28 TOUT3 MII2 COL GND PE27 Port E27 RTS3 L1RQB MII2 RXER RMII2 RXER GND PE26 Port E26 L1CLKOB MII2 RXDV RMII2 CRS_DV GND PE25 Port E25 RXD4 MII2 RXD3 L1ST2 RXD4 PD8 PE24 Port E24 SMRXD1 BRGO1 MII2 RXD2 SMRXD1 PB24 PE23 Port E23 SMSYN2 TXD4 MII2 RXCLK L1ST1 SMSYN2 PB22 PE22 Port E22 TOUT2 MII2 RXD1 ...

Page 940: ...r output This allows output conflicts to be found on the signal by comparing the written data with the data on the signal Data written to PEDAT is latched if the corresponding PEDIR bit is configured as an output the latched value is driven onto its respective signal PEDAT can be read or written at any time and is not initialized This register is affected by HRESET and SRESET 0 15 Field Reset 0000...

Page 941: ...23 24 25 26 27 28 29 30 31 Field D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Reset Undefined R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Addr 0xADA Figure 34 20 Port E Data Register PEDAT Table 34 24 PEDAT Bit Descriptions Bits Name Description 0 13 Reserved 14 31 Dn Contains the data on the corresponding signal 0 13 14 15 Field DR14 DR15 Reset 0 0 R W R...

Page 942: ...ct the peripheral function 0 Select the signal for general purpose input or select peripheral function 0 1 Select the signal for general purpose output or select peripheral function 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field DD14 DD15 Reset 0 0 R W R W R W Addr 0xACC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 ...

Page 943: ... 0xAD0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field SO16 SO17 SO18 SO19 SO20 SO21 SO22 SO23 SO24 SO25 SO26 SO27 SO28 SO29 SO30 SO31 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Addr 0xAD2 Figure 34 23 Port E Special Options Register PESO Table 34 27 PESO Bit Descriptions Bits Name Description 0 13 Reserved 14 31 SOn Port E Speci...

Page 944: ...Parallel I O Ports MPC885 PowerQUICC Family Reference Manual Rev 2 34 26 Freescale Semiconductor ...

Page 945: ... the 12 general purpose timers and port C parallel I O signals described in Section 34 4 Port C More than one of these sources may generate interrupts at the same time therefore the CIMR register is provided for masking individual sources Additional masking is provided for specific interrupt events within each controller that reports interrupts through the CPIC These mask registers are described i...

Page 946: ... request and then acknowledges the interrupt by setting the IACK bit in the CPM interrupt vector register CIVR When CIVR IACK is set the contents of CIVR VN are updated with the 5 bit vector corresponding to the sub block with the highest current priority CIVR IACK is cleared after one clock cycle 35 2 CPM Interrupt Source Priorities The CPIC has 29 interrupt sources that assert a single programma...

Page 947: ...ere the USB and 3 SCCs function at a very high data rate and interrupt latency is critical Table 35 1 Prioritization of CPM Interrupt Sources Priority Source Description Multiple Events Priority Source Description Multiple Events 0x1F Highest Parallel I O PC151 1 Port C interrupts external sources are described in Section 34 4 1 5 Port C Interrupt Control Register PCINT No 0x0F Parallel I O PC11 1...

Page 948: ...rrupt within the same interrupt level to be presented to the core before a lower priority interrupt service completes Each CISR bit corresponds to a CPM interrupt source When the core acknowledges the interrupt by setting IACK the CPIC sets the CISR bit for that interrupt source This prevents subsequent CPM interrupt requests at this priority level or lower until the current interrupt is serviced ...

Page 949: ...M interrupts are pending The error vector cannot be masked 35 4 Generating and Calculating Interrupt Vectors Unmasked CPM interrupts are presented to the core in order of priority The core responds to an interrupt request by setting CIVR IACK The CPIC passes the five low order bits of the vector corresponding to the highest priority unmasked pending CPM interrupt in CIVR VN These encodings are sho...

Page 950: ...upt mask register CIMR Can be used to mask CPM interrupt sources CPM interrupt in service register CISR Allows nesting interrupt requests within the CPM interrupt level Note that the names and placement of bits is identical in the CIPR CIMR and CISR 35 5 1 CPM Interrupt Configuration Register CICR The CPM interrupt configuration register CICR defines CPM interrupt request levels the priority betwe...

Page 951: ... SCC3 asserts its request in the SCCc position 11 SCC4 asserts its request in the SCCc position 12 13 SCbP1 SCCb priority order Defines whether USB or SCCs asserts its request in the SCCb priority position 00 USB asserts its request in the SCCb position 01 SCC2 asserts its request in the SCCb position 10 SCC3 asserts its request in the SCCb position 11 SCC4 asserts its request in the SCCb position...

Page 952: ... the service routine Acknowledge interrupts from port C by clearing the CIPR bit directly by writing ones For all other interrupt sources however clear the unmasked event register bits instead thus causing the CIPR bit to be cleared 24 IEN Interrupt enable Master enable for CPM interrupts 0 CPM interrupts are disabled 1 CPM interrupts are enabled 25 30 Reserved 31 SPS Spread priority scheme Select...

Page 953: ...t after servicing is complete If an event register exists for this peripheral its bits would normally be cleared Write ones to clear CISR bits writing zeros has no effect Bits set in this register indicate which interrupt requests are in progress for each CPM interrupt source More than one CISR bit can be set if higher priority CPM interrupts are allowed to interrupt lower priority level interrupt...

Page 954: ...main unmasked in SCCE2 This is an example of a handler for an interrupt source with multiple events Notice that the handler must clear the CISR bit but not the CIPR bit 1 Set the CIVR IACK 2 Read CIVR VN to determine the vector number for the interrupt handler 3 Immediately read the SCC2 event register into a temporary location 4 Decide which events in the SCCE2 must be handled and clear those bit...

Page 955: ...Rev 2 Freescale Semiconductor 35 11 7 Execute the rfi instruction If any unmasked SCCE bits remain either not cleared by the software or set by the MPC885 during the execution of this handler this interrupt source is pending again immediately after the rfi instruction ...

Page 956: ...CPM Interrupt Controller MPC885 PowerQUICC Family Reference Manual Rev 2 35 12 Freescale Semiconductor ...

Page 957: ...tion Tables describes the structure and configuration of the buffer descriptors BDs and the transmit and receive connection tables TCTs and RCTs used with ATM Chapter 38 ATM Parameter RAM describes how the parameter RAM is used to configure the SCCs for serial ATM and the UTOPIA interface The CP also uses parameter RAM to store operational and temporary values used during SAR activities Chapter 39...

Page 958: ... a destination GPR REG FIELD Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text Specific bits fields or numerical ranges appear in brackets For example MSR LE refers to the little endian mode enable bit in the machine state register x In certain contexts such as in a signal encoding or a bit field indicates a don t care n Indicates an undefined numerical valu...

Page 959: ...n part convergence sublayer CPCS PDU Common part convergence sublayer protocol data unit CPCS UU Common part convergence sublayer user to user information CPI Common part indicators CPM Communications processor module CPS Cells per slot CSMA Carrier sense multiple access CSMA CD Carrier sense multiple access with collision detection DMA Direct memory access DPLL Digital phase locked loop DPR Dual ...

Page 960: ...rs IrDA Infrared Data Association ISDN Integrated services digital network JTAG Joint Test Action Group LAN Local area network LIFO Last in first out LRU Least recently used LSB Least significant byte lsb Least significant bit MAC Multiply accumulate or media access control MBS Maximum burst size MII Media independent interface MSB Most significant byte msb Most significant bit MSR Machine state r...

Page 961: ...ceive SAR Segmentation and reassembly SCC Serial communications controller SCP Serial control port SCR Sustained cell rate SDLC Synchronous Data Link Control SDMA Serial DMA SI Serial interface SIU System interface unit SMC Serial management controller SNA Systems network architecture SPI Serial peripheral interface SRAM Static random access memory SRTS Synchronous residual time stamp TCT Transmit...

Page 962: ...rammable machine USART Universal synchronous asynchronous receiver transmitter VCC Virtual channel connection VCI Virtual circuit identifier VP Virtual path VPC Virtual path connection VPI Virtual path identifier UTOPIA Universal test and operations physical interface for ATM VBR Variable bit rate VC Virtual channel or virtual circuit WAN Wide area network Table VI 1 Acronyms and Abbreviated Terms...

Page 963: ...r UTOPIA level 1 specification is also supported Parameter RAM for both SPI and I2 C can be relocated without RAM based microcode Supports full duplex UTOPIA master ATM side and slave PHY side operation using UTOPIA split bus mode AAL2 VBR functionality is ROM resident 36 1 ATM Capabilities The MPC885 can be used as an adaptable ATM controller suited for a variety of applications including the fol...

Page 964: ... 1 Control Character Table RCCM and RCCR In ESAR mode In UTOPIA split bus mode PCMCIA port A signals are unavailable However in UTOPIA muxed bus mode the PCMCIA port A signals are still available on the PCMCIA port A pins In ESAR multi PHY mode The PHY address signals are multiplexed with the signals of both SMCs However when a PHY address signal is not activated the pin s other signal functions b...

Page 965: ...cuit VC basis AAL0 support allows other AAL types to be implemented in application software AAL2 support Support for 32 active VCs using internal dual port RAM and up to 64K using external memory Flexible and efficient cell rate pacing support for CBR VBR and UBR with software hooks provided for host managed ABR services Supports UTOPIA and serial E1 T1 interfaces Compliant with ATM Forum UNI 4 0 ...

Page 966: ...ut host software intervention May be activated per channel as programmed in the RCT PTP connection between any combination of serial UTOPIA multi PHY ports Cell scheduling may be done by one of the following methods Using the ATM pace controller APC to reshape traffic Using the priority based APC levels to maintain traffic shaping requirements over multiple channels BD table wrap counter used for ...

Page 967: ...real time variable bit rate rt VBR and nrt VBR pacing using sustained cell rate SCR and maximum burst size MBS parameters Unspecified bit rate UBR pacing Available bit rate ABR pacing pace is managed by upper layer host software when establishing a connection Queue handler ATM PTP fair queueing mechanism using configurable APC priority levels Flexible priority combinations of PTP queues and APC sc...

Page 968: ...ollowing sections describe the transfer mechanisms for the serial and UTOPIA interface modes and the functionality of the ATM pace controller APC which is utilized in both modes of operations Internal and external ATM channels are introduced Port to port cell switching and memory to memory SAR operation is also discussed 36 6 UTOPIA Operation In UTOPIA mode the ATM controller handles transfers on ...

Page 969: ... an AAL5 frame the transmitter appends the trailer of the common part conversion sublayer protocol data unit CPCS PDU to the user frame It pads as required appends the length calculated during the frame transmit and copies the CPCS UU and CPI from the TxBD The transmitter also sets the PTI 1 bit in the header An interrupt can be optionally generated to declare the end of the transmit frame For AAL...

Page 970: ...r copies the cell except the HEC from the UTOPIA interface to the channel s current buffer and optionally performs a CRC10 check on the cell payload The CRC10 option is used to support OAM cell checking by host software according to the ITU specification I 610 Note that the received HEC is not checked by the ATM controller in UTOPIA mode it is the responsibility of the PHY to check the HEC and dis...

Page 971: ...where the CRC32 and HEC are calculated the cell header is appended and scrambling is optionally performed After the cell assembly process the cell is moved into the SCC s transmit FIFO for transmission The transmitter appends the trailer of the CPCS PDU in the last cell of an AAL5 user frame The CPCS PDU consists of the frame length which is calculated during the frame transmit the CPCS UU and CPI...

Page 972: ...er copies the cell except the HEC from the SCC FIFO to the next receive buffer in the channel s BD table The ATM controller calculates and optionally checks CRC10 on the cell payload This option supports the OAM cell check per ITU specification I 610 36 7 2 1 Cell Delineation In serial mode cell delineation is part of the receiver flow control The ATM controller provides SDH PDH oriented cell deli...

Page 973: ...ts the APC parameters in response to incoming resource management RM cells and defines the ABR available cell rate ACR The APC period can be changed on the fly thereby allowing the bit rate for a channel to be changed dynamically which is necessary to control transmission of traffic types such as ABR For ABR it is the user s responsibility to evaluate RM cells and update the APC pace values in the...

Page 974: ...its ATM PDUs that is each transmitted AAL5 CPCS PDU can be converted into ATM PDUs looped back and stored into receive buffers as individual ATM PDUs by programming the RCT for the same channel to AAL0 mode For reassembly operations stored ATM PDUs can be transmitted in AAL0 mode looped back and reassembled as AAL5 CPCS PDUs by converting each sequence of received ATM PDUs in AAL5 mode 36 12 Gener...

Page 975: ... accommodate multiple ATM channels each channel number is given its own pair of BD tables located in external memory The base pointers to a channel s BD tables are programmed as part of the channel specific information in the channel s RCT and TCT see Section 37 2 Receive and Transmit Connection Tables RCTs and TCTs Each transmit channel has a separate TxBD table and a TCT which holds the TxBD poi...

Page 976: ... of a frame The last buffer of a frame is padded automatically by the transmitter to fit an AAL5 cell payload according to ITU specification I 363 The transmit buffer data length for AAL5 transmit buffers must be greater than or equal to 48 bytes for all buffers except the first and last buffer of a frame the first and last buffers of a frame must have a data length greater than zero Note that AAL...

Page 977: ...the user The AAL0 buffer structure is shown in Figure 37 2 Figure 37 2 AAL0 Buffer Structure Unlike other protocols both the AAL0 transmit and receive buffers should be 16 byte aligned 37 1 3 ATM Receive Buffer Descriptors RxBDs The format of the ATM receive buffer descriptor RxBD applies to both UTOPIA and serial ATM modes ATM RxBDs are 12 bytes as shown in Figure 37 3 For UTOPIA operation a glob...

Page 978: ...he E bit is cleared 1 The data buffer associated with this RxBD is empty or reception is currently in progress This RxBD and its associated receive buffer are in use by the CP Once the E bit is set the CPU core should not write to this RxBD 1 Reserved should be cleared during initialization 2 W Wrap Determines that this is the final BD in the table 0 This is not the last BD in the RxBD table 1 Thi...

Page 979: ...e monitoring RCT PM 1 0 Not an FMC cell 1 An FMC cell to which BRC fields have been added 8 HEC HEC error AAL5 A receiver HEC error occurred on at least one cell of the frame Cells with HEC errors are passed to the global raw cell queue with this bit set 9 CLP Cell loss priority Indicates that at least one cell was received with its CLP bit set This bit is set in the last BD in the frame by the CP...

Page 980: ...plies only when filtering is activated SRSTATE MCF 1 When not operating in extended channel mode the CH_CODE field contains the channel s RCT address in dual port RAM In extended channel mode CH_CODE is the actual channel number 0x04 Receive data buffer pointer Receive data buffer pointer Points to the first location of this BD s data buffer which may reside in either internal or external memory T...

Page 981: ...SET 0 R W I L OAM CM ICNG RH ICLP OFFSET 2 DATA LENGTH OFFSET 4 TX DATA BUFFER POINTER OFFSET 8 CPCS UU CPI HEADER_L OFFSET A RESERVED HEADER_H Figure 37 5 ATM TxBD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFFSET 0 R W I L OAM CM ICNG RH ICLP OFFSET 2 DATA LENGTH OFFSET 4 TX DATA BUFFER POINTER OFFSET 8 CPCS UU CPI HEADER_L OFFSET A RESERVED HEADER_H OFFSET C CELL HEADER EXPANSION 1 OFFSET 10 CELL HE...

Page 982: ...irst BD in the channel s TxBD table the BD pointed to by the channels s TCT TBASE address will be used The number of TxBDs in the table is programmable and is limited by the 256K memory space for all the transmit channels 3 I Interrupt Enables interrupts generated when the contents of the buffer have been sent 0 No interrupt is generated after the buffer has been transmitted 1 The TXB bit is set i...

Page 983: ...re used as the lower order half of the HEADER field The transmitter sends a dummy field of all zeros for the CPCS UU and CPI field The RH mechanism can be used to implement a global AAL5 queue for different VC VP It can also be used for frame relay to ATM CLP and EFCI interoperability 0 Do not replace TCT CHEAD 1 Copy TxBD HEADER into TCT CHEAD and then clear TxBD HEADER 15 ICLP Invert CLP AAL5 on...

Page 984: ...ns CPI The transmitter copies this field to the AAL5 frame trailer HEADER_L Lower order half word of the replacement header AAL5 only and RH 1 HEADER_L and HEADER_H comprise the new cell header to be stored in the TCT CHEAD field See the TxBD RH description above The byte ordering of the 4 byte HEADER field is little endian that is the MSB is at location 0x0B and the LSB is at location 0x08 0x0A H...

Page 985: ...ts own separate raw cell queue 37 2 1 Receive Connection Table RCT Each receive connection table RCT holds parameters channel configuration pointers status flags and temporary data for a single ATM receive channel Figure 37 8 shows the RCT structure RCT Internal Use TCT Internal Use RCT0 Global raw cell queue TCT0 RCT1 TCT1 RCT2 RCT3 TCT31 CTBASE Dual port RAM Reserved in 32 x 64 Bytes RCT32 TCT32...

Page 986: ...on or a restart and is currently in frame hunt mode In frame hunt mode the CP discards all received cells until a new frame is started indicated by the CPI bit of the last cell header FHNT is cleared by the user during initialization and is modified accordingly by the CP thereafter 0 Not in frame hunt mode 1 In frame hunt mode 1 PM Performance monitoring Should be set if PM cell termination is req...

Page 987: ...eported in the last cell of the current frame RCT CNG is set only if the last cell of the current AAL5 frame has arrived with the PTI EFCI bit set in its header At the end of the frame this bit is copied to the last RxBD CNG of the frame 0 No congestion has been reported 1 Congestion has been reported NCRC No CRC AAL0 only NCRC is used to disable CRC10 calculations If CRC10 is not required for thi...

Page 988: ...R is the physical address of the current buffer location to which data is being written Should be cleared during initialization 0x0C RTMLEN AAL5 only Frame buffer count Contains the total number of bytes received during the current AAL5 frame The CP clears RTMLEN at the beginning of a frame and increments it by the value in SMRBLR in parameter RAM as each additional buffer is received The receiver...

Page 989: ...ee Section 41 3 Interrupt Queue Mask IMASK 0x16 0 1 FT Filter type Selects the filter type used for this channel FT is part of the management cell filtering mechanism see Section 39 2 Management Cell Filter MCF for the programming of this field 2 NIM Non intrusive monitoring Can be set for AAL0 channels only If set NIM enables non intrusive monitoring and or non intrusive PM of all types of OAM ce...

Page 990: ...T Frame hunt mode Indicates that this channel has had a busy exception or a restart and is currently in frame hunt mode In frame hunt mode the CP discards all received cells until a new frame is started indicated by the CPI bit of the last cell header FHNT is cleared by the user during initialization and is modified accordingly by the CP thereafter 0 Not in frame hunt mode 1 In frame hunt mode 1 9...

Page 991: ...the APC 1 Automatically inserts TX_CHANNEL into SCC PHY Transmit Queue There is no need for APC scheduling for this channel No need for Tx Activate Channel command 1 PPD PPD enable Partial packet discard also known as early packet discard or frame discard is a more efficient way to handle congestion for AAL5 channels Instead of individual cells whole user frames except the last cell indicated in t...

Page 992: ...for transferring the PTP cells 00 SCC1 page1 01 SCC2 page2 10 SCC3 page3 11 SCC4 or UTOPIA page4 8 IAQ Insert into the APC PTP queue 0 No IAQ The channel can be scheduled by the APC reshaping or APC BYPASS command 1 IAQ The receive cell is placed directly into a PTP buffer using the PTP BD table of the associated transmit channel PTP_TX_CH and the PTP counter is incremented to indicate the number ...

Page 993: ...ld indicate the MPHY PTP route PTP_BD_PTR should be initialized to PTP_BASE 0x10 0 15 PTP_BASE 0x12 Reserved should be cleared during initialization 0x14 Reserved should be cleared during initialization 0x14 1 15 IMASK Interrupt mask Contains the interrupt mask for both the receive and transmit sides of this channel number The interrupt mask allows the user to enable or disable interrupt generatio...

Page 994: ...NR TSERVICE APCP CT_Offset 3E APCPF Figure 37 10 Transmit Connection Table TCT Table 37 5 TCT Field Descriptions CT Offset Bits Name Description 0x20 0 Reserved should be cleared 1 PM Performance monitoring Should be set if PM cell generation is required on this channel TPMT defines the PM table to be used with this channel An FMC containing the parameters collected in the PM table is automaticall...

Page 995: ...buffer TBALEN is initialized with the data length field of the TxBD when a new buffer opens and is decremented by 48 for each cell sent 0x24 TCRC Temporary CRC32 AAL5 only CP scratch pad area for the CRC32 calculation 0x28 TB_PTR Transmit buffer pointer Contains the real address of the current data position in the transmit buffer 0x2C TTMLEN Transmit total message length AAL5 only Counts bytes sen...

Page 996: ...SMIT DEACTIVATE CHANNEL command or when the CP is programmed to automatically deactivate the channel when buffers are not ready TCT AVCF 1 Note that ACT is not cleared until the next time the channel is encountered in the APC scheduling table maximum latency of one full pass through the APC scheduling table 1 Active Set by the CP when the host issues a TRANSMIT ACTIVATE CHANNEL command Also for PT...

Page 997: ...s 00 CBR and UBR maintain PCR 01 Reserved 10 VBR maintain PCR SCR BT and OOBR 11 UBR maintain PCR and OOBR 4 15 APCP APC pace Contains the channel s APC pacing When the channel is placed in the transmit queue the APC reschedules the channel in a new position time slot in the APC scheduling table The new slot position is the current slot position APCP modulo the table length Note that the APCP valu...

Page 998: ...37 11 PTP Transmit Connection Table PTP TCT Table 37 6 PTP TCT Field Descriptions CT Offset Bits Name Description 0x20 0 10 Reserved should be cleared during initialization 1 PM Performance monitoring Should be set if PM cell generation is required on this channel TPMT defines the PM table to be used with this channel An FMC containing the parameters collected in the PM table is automatically inse...

Page 999: ...ld be cleared during initialization 0x2A 0X2D Reserved should be cleared during initialization 0x2E PTP_BD_PTR PTP BD pointer Points to the current BD in the PTP BD table The actual address of the current BD is PTP_BD_PTR x 4 TBDBASE where TBDBASE is the base pointer to the TxBD memory space Initialize PTP_BD_PTR to the same value as PTP_BASE Note that PTP_BD_PTR is a word aligned offset pointer f...

Page 1000: ... from the APC scheduling table when the host issues a TRANSMIT DEACTIVATE CHANNEL command or when the CP is programmed to automatically deactivate the channel when buffers are not ready TCT AVCF 1 Note that ACT is not cleared until the next time the channel is encountered in the APC scheduling table maximum latency of one full pass through the APC scheduling table 1 Active Set by the CP when the h...

Page 1001: ...d is issued OUT is immediately set OUT is then cleared when the channel is actually removed from the APC scheduling table TCT ACT is cleared 0 No TRANSMIT DEACTIVATE CHANNEL command is pending 1 The channel is waiting to be removed from the APC scheduling table 1 BNR Buffer not ready Reserved for internal use should be cleared during initialization 2 3 TSERVICE Traffic service Selects the type of ...

Page 1002: ...et 8 BUPTRL TCTE_Offset C VBR2 TCTE_Offset E OOBR TCTE_Offset 10 to TCTE_Offset 1E Figure 37 13 Transmit Connection Table Extension TCTE TCTE Internal Use TCTE0 UBR TCTE1 UBR TCTE31 UBR TCTEBASE Dual port RAM Reserved in 32 x 32 Bytes TCTE32 UBR ETCTEBASE External Memory Extended Channel Mode of User Space Located in the Parameter RAM Located in the Parameter RAM TCT Extensions for Internal VBR UB...

Page 1003: ...et size used by the GCRA algorithm The relationship between BT and the maximum burst size is BT MBS 2 SCR PCR SCR 0x06 BUPT RH Reserved should be cleared during initialization Used by the CP for the GCRA algorithm leaky bucket high pointer 0x08 BUPT RL Reserved should be cleared during initialization Used by the CP for the GCRA algorithm leaky bucket low pointer 0x0C 0 VBR2 VBR type AAL5 only 0 Re...

Page 1004: ...Buffer Descriptors and Connection Tables MPC885 PowerQUICC Family Reference Manual Rev 2 37 30 Freescale Semiconductor ...

Page 1005: ...el is defined in the channel s RCT RCT RBASE or PTP RCT PTP_BASE RBDBASE must be word aligned 0x04 SRFCR Byte SAR receive function code register Contains global parameters for DMA transfers See Section 38 1 SAR Receive Function Code Register SRFCR 0x05 SRSTATE Byte SAR receive state Contains global state parameters See Section 38 2 SAR Receive State Register SRSTATE 0x06 MRBLR Hword Maximum receiv...

Page 1006: ...eceive and Transmit Connection Tables RCTs and TCTs 0x24 ECTBASE Word External connection table base address Valid only in extended channel mode SxSTATE EXT 1 Contains the 64 byte aligned base address for the connection tables of the external channels numbered 32 and higher See Section 37 2 Receive and Transmit Connection Tables RCTs and TCTs 0x28 INTBASE Word Interrupt base pointer Contains the w...

Page 1007: ...the use of idle cells Unassigned cells are used as empty cells when EHEAD 0x0000_0000 and idle cells when EHEAD 0x0100_0000 In both cases EPAYLOAD should be initialized to 0x6A6A_6A6A Note that the data for these fields must be written in little endian byte order 0x44 EPAYLOAD Word 0x48 TQBASE Hword Transmit queue base pointer Contains the user defined pointer to the base address of the transmit q...

Page 1008: ...ty level base pointer Points to the base address of the APC priority levels see Section 40 9 APC Priority Levels APCPTR is an offset from the beginning of dual port RAM It should be divisible by 32 end with 0b00000 In ESAR multi PHY master mode APCPTR points to the MPHY pointing table see Section 40 8 MPHY Pointing Table Master Only In this case APCPTR can be half word aligned divisible by two 0x5...

Page 1009: ... data location in the transmit buffer during cell transmission For internal use 0x70 TTEMP 1 Word Transmitter temporary data storage 0x74 to 0x7F 12 Bytes Reserved Note Parameters shown shaded are used for serial ATM only Nonshaded parameters are used for both serial ATM and UTOPIA operations Note Parameters shown in boldface type must be initialized by the user before enabling ATM operations Para...

Page 1010: ...ter for the OAM performance monitoring tables Contains the word aligned base address in the dual port RAM of the PM tables PMPTR is an offset from the beginning of dual port RAM See Section 39 3 4 Performance Monitoring Tables 0x8a PMCHANNEL Hword Temporary storage for the current PM channel number Should be cleared during initialization 0x8c to 0x8F 4 Bytes Reserved 0x90 MPHYST Hword UTOPIA multi...

Page 1011: ...nly 0xAC 0xBF Reserved Table 38 3 Serial ATM Parameter RAM Map Offset from SCC Base Name Width Description 0xC0 ALPHA Hword Receiver delineation alpha delta counters The ATM controller applies the HEC delineation mechanism described in ITU specification I 432 where ALPHA and DELTA are initialized by the user to a value from 0 to 63 The ITU specification I 432 recommendation is 0x7 for alpha and 0x...

Page 1012: ...emporary CRC 0xE8 TCRC 1 Word Transmitter temporary CRC 0xEC RCHAN 1 Word Receiver current channel 0xF0 TCHAN 1 Word Transmitter current channel 0xF4 to 0xFF 12 Bytes Reserved Note Parameters in boldface type are initialized by the user before ATM operations Parameters not specified as user initialized are configured by the CP and should not be modified by the user 1 During transfers the CP uses S...

Page 1013: ...eld Descriptions Bits Name Description 0 EXT Extended channel mode EXT and ACP select the address matching mechanism see Section 38 5 Address Match Parameters AM1 AM5 0 Maximum of 31 5 channels available Receive channel 0 is reserved for the raw cell queue Channel mapping and connection tables are supported internally Internal look up table channel mapping mechanism is used 1 Maximum of 65534 5 ch...

Page 1014: ...MCF is not active The address mapping mechanism is performing OAM and management demultiplexing 1 The MCF is actively screening see Section 39 2 Management Cell Filter MCF OAM cell demultiplexing can be done by the MCF 6 SER ATM physical interface type 0 UTOPIA PHY 1 Serial PHY 7 MPY Enable multi PHY mode Valid only for the SCC4 parameter RAM when in UTOPIA mode 0 Single PHY mode 1 Multiple PHY mo...

Page 1015: ...e 0 Maximum of 31 5 channels available Receive channel 0 is reserved for the raw cell queue Connection tables are supported internally 1 Maximum of 65534 5 channels available Channel 65535 and receive channel 0 are reserved Connection tables are supported externally Note SRSTATE EXT and STSTATE EXT must match both either set or cleared 1 Reserved 2 EC Expanded cell This option is valid only in UTO...

Page 1016: ...d from the top AMEND to the base so headers for the busiest connections should be at the top of the table When a match occurs the CP uses the location of the match to locate the channel number in the pointer table Initialize AMBASE to point to the last entry of the lookup table AMBASE must be word aligned AM4 AMEND Address matching end pointer Contains the address of the top entry in the lookup ta...

Page 1017: ...SE AM4 AM5 FLMASK First level mask The ATM controller masks the GFC VPI and PTI bits of the header of each incoming cell with FLMASK 1 15 and uses the resulting masked header in the first level address matching process The masking process uses a bitwise AND function to allow address bits to be masked out by clearing the relevant bits in FLMASK The FLMASK fields are shown in Figure 38 6 The FLMASK ...

Page 1018: ...Field CSER NSER NMPHY CMPHY ESAR DIS PL2 MPY Reset Oper R W Addr 0x50 in SCC parameter RAM Figure 38 7 APC State Register APCST Table 38 13 APCST Field Descriptions Bit s Name Description 0 Reserved 1 2 CSER Current serial ATM or UTOPIA port CSER is used by the APC to point to the currently active serial or UTOPIA interface if multiple physical ATM ports are active Initialize CSER with the same va...

Page 1019: ...support this multi PHY master configuration This bit should be cleared if classic SAR operation is required 0 ESAR APC functions are disabled 1 ESAR APC functions APC and MPHY are enabled 13 DIS APC disabled status flag Valid for serial ATM only Set by the transmitter when a global FIFO underrun GUN exception occurs Should be cleared during initialization 14 PL2 Reserved in ESAR mode Priority leve...

Page 1020: ...nected to the UTOPIA port 0x00 1 PHYs 0x01 2 PHYs 0x02 3 PHYs up to 0x1E 31 PHYs 0x1F Reserved 7 9 Reserved 10 14 CMPHY Current multi PHY Valid only for the SCC4 parameter RAM when in UTOPIA multi PHY mode CMPHY is used only by the CP and should be initialized with the same value programmed in NMPHY 15 Reserved 0 5 6 7 8 14 15 ORUN URUN LOCK Figure 38 9 ASTATUS Table 38 15 ASTATUS Register Field D...

Page 1021: ...for the user Indicates the current cell delineation status Should be cleared during initialization 0 The receiver is out of synchronization and is not receiving cells 1 The receiver has gained cell delineation and is receiving cells Note The receiver cell delineation status is also indicated by SCCE SYNC Table 38 15 ASTATUS Register Field Descriptions continued Bits Name Description ...

Page 1022: ...ATM Parameter RAM MPC885 PowerQUICC Family Reference Manual Rev 2 38 18 Freescale Semiconductor ...

Page 1023: ...Internal Look up Mechanism SRSTATE EXT 0 The internal look up mechanism maps the address fields in the header of incoming cells to internal channel numbers This mapping mechanism uses two tables an address matching table and a pointing table The matching table contains up to thirty one 32 bit address GFC VPI VCI PTI CLP entries and one empty entry at the base of the table reserved for the raw cell...

Page 1024: ...hree steps Note that a channel can be removed safely only when it has stopped receiving cells the upstream ATM channel has stopped sending cells If the channel is the last one at the AMEND position channel removal is achieved by simply updating AMEND to point to previous entry Remove a channel entry in the middle of the table as follows 1 Copy the top entry of the match table the address match ent...

Page 1025: ...ed FLT entries should be cleared null entry Cells with a null entry pointer are received into the default raw cell queue The size of the FLT depends on the number of mask bits in the FLMASK If for example FLMASK contains an unbroken sequence of ten bits set the index pointer into the FLT will contain 10 bits resulting in a table size of 4 Kbytes The actual address of an FLT entry is FLBASE index_p...

Page 1026: ...nel Aliasing Reliable one to one mapping of VCs to local channel numbers requires that the address bits not taken into account during the translation have a fixed value chosen to be zero Otherwise multiple VCs could translate to a single local channel number The CUMB feature check unused mask bits can be used to test the reliability of the mapping by screening out misinserted cells When FLMASK CUM...

Page 1027: ... in the parameter RAM see Table 38 12 The CP then performs a DMA write access to the CAM address CAMADD with the address generated from the masked header as its data operand The second access is a read DMA access to CAMADD During the read access the CAM should drive a match successful indication on the data bus D 0 signal and the matched channel number on the data bus D 16 31 signals The match suc...

Page 1028: ...T by terminating all management and OAM cells If SRSTATE MCF is set and RCT NIM 1 non intrusive monitoring the MCF performs as a pass all switch by passing all data and management cells but it also copies all management cells to the raw cell queue for host monitoring The FT field defines the type of FMC forward monitoring cell to be monitored segment or end to end The monitored FMC is copied to th...

Page 1029: ... cells FMC flag in BD is set for FMCs in channels that are in PM mode All but filtered OAM flag in BD is set for OAM cells 10 Segment Non user cells OAM segment F4 or F5 OAM flag in BD is set for OAM cells FMC flag in BD is set for FMCs in channels that are in PM mode All but filtered OAM flag in BD is set for OAM cells OAM end to end cells 11 x Reserved 00 1 Non Intrusive monitoring OAM flag in B...

Page 1030: ...ws the FMC and BRC structure Figure 39 4 Performance Monitoring Cell Structure FMCs and BRCs Table 39 2 describes performance monitoring cell fields Table 39 2 Performance Monitoring Cell Fields Field Description BRC FMC MCSN Monitoring cell sequence number The sequence number of the performance monitoring cell modulo 256 Yes Yes TUC0 1 Total user cell 0 1 count Counts all user cells modulo 65 536...

Page 1031: ...it cell counter TCC in the performance monitoring table reaches the PM block size BLCKSIZE the CP generates an FMC The CP copies the FMC header MCSN TUC0 1 TUC0 BEDC0 1 Tx from the PM table and places them in the FMC template The time stamp TSTP is read from the memory address specified by FMCTIMESTMP in the parameter RAM see Table 39 2 The CP then inserts the FMC into the user cell stream A TUC i...

Page 1032: ...EMPLATE 0x04 6A 6A 6A 6A FMCTEMPLATE 0x08 6A 6A 6A 6A FMCTEMPLATE 0x0C FF FF FF FF FMCTEMPLATE 0x10 6A 6A 6A 6A FMCTEMPLATE 0x14 6A 6A 6A 6A FMCTEMPLATE 0x18 6A 6A 6A 6A FMCTEMPLATE 0x1C 6A 6A 6A 6A FMCTEMPLATE 0x20 6A 6A 6A 6A FMCTEMPLATE 0x24 6A 6A 6A 6A FMCTEMPLATE 0x28 6A 6A 6A 6A FMCTEMPLATE 0x2C 6A 6A 6A 6A FMCTEMPLATE 0x30 6A 6A 6A 6A Unused 2 octets 4 octets 1 octet 29 octets 2 octets Time...

Page 1033: ... recommendation I 610 The number of user cells i e CLP 0 1 between the last two forward monitoring OAM cells does not equal the difference between the TUC values of the last two forward monitoring OAM cells The MCSN of the last two performance monitoring OAM cells used for forward monitoring are not sequential Figure 39 7 is an example of the MPC885 as an endpoint segment point The PM block size i...

Page 1034: ...cells of this block test When Nt Nr no cells are lost or misinserted 39 3 4 Performance Monitoring Tables The OAM performance monitoring tables include PM block test parameters Each block test needs a 32 byte PM table see Figure 39 8 The user assigns a PM table number to a VCC or VPC in the connection s RCT and TCT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFFSET 0 OV BLCKSIZE OFFSET 2 TX Cell Count T...

Page 1035: ...FMC is sent and the counter is reinitialized by the CP to the block size Should be cleared during initialization 0x4 0 15 TUC0 1 Total user cell counter Count of CLP 1 and CLP 0 user cells modulo 65 536 sent Should be cleared during initialization 0x6 0 15 TUC0 Total user cell CLP 0 Count of CLP 0 user cells modulo 65 536 sent Should be cleared during initialization 0x8 0 31 BEDC0 1 Rx Temporary b...

Page 1036: ...issuing a WRITE TO MEMORY command See Table 39 8 for the ATM commands Then issue another WRITE TO MEMORY command to set TCT PM to activate the PM session for this specific channel 39 3 5 2 Activating Unidirectional Receive PM After initializing a PM table issue a WRITE TO MEMORY command to program the PM table number in RCT RPMT and to program the MCF type in RCT FT according to the PM session typ...

Page 1037: ...ched connections with AAL5 content Can terminate OAM or management cells while PTP switching the data cells 39 4 1 PTP Switching Mechanism In the host controlled method of ATM to ATM cell switching the host application software handles the BDs and transfers the buffer pointers from the RxBD table to the TxBD table Figure 39 9 shows the host controlled method with the option of using APC scheduling...

Page 1038: ...ation can be done statically using the TRANSMIT ACTIVATE CHANNEL command or dynamically using the auto VC on auto VC off option PTP RCT AVCO TCT AVCF The APC BYPASS command can also be used to schedule PTP cells but this would require host software intervention If the connection s PTP BD table APC PTP queue overruns during cell reception a receiver busy interrupt is issued and the incoming cell is...

Page 1039: ...both UTOPIA and serial ATM Table 39 5 describes the PTP BD fields 1 0 1 Reserved 1 1 1 Reserved 0 1 2 3 4 15 OFFSET 0 V W I OFFSET 2 OFFSET 4 PTP Buffer Pointer OFFSET 8 OFFSET A Figure 39 11 PTP Buffer Descriptor Table 39 5 PTP BD Field Descriptions Offset from PTP_BD_PTR Bits Name Description 0x00 0 V Valid ready for switching Should be cleared during initialization 0 Empty The data buffer assoc...

Page 1040: ...M utilization The supported counters are as follows Total cell count of transmitted cells TotalTxCells Total cell count of transmitted cells with the CLP bit set TotalTxCLP1 Total cell count of received cells TotalRxCells Total cell count of received cells with the CLP bit set TotalRxCLP1 0x00 cont 2 W Wrap Determines that this is the final BD in the table 0 This is not the last BD in the PTP BD t...

Page 1041: ...STATBASE points to the statistics table for PHY0 Each PHY then has a 32 byte table starting at STATBASE 32 PHY_number 39 6 Multi PHY MPHY Configuration The MPC885 implements the UTOPIA level 2 multi PHY method as described in Section 4 2 Operation with 1 TxClav 1 RxClav Signal in the ATM Forum UTOPIA Level 2 Version 1 0 specification For a multi PHY system the number of TxAddr and RxAddr signals u...

Page 1042: ...n mechanism or an external CAM look up see Section 39 6 1 2 Address Compression Multi PHY Support or Section 39 6 1 3 CAM Multi PHY Support In multi PHY mode the 32 entry address matching and pointing tables described in Section 39 1 1 Internal Look up Mechanism SRSTATE EXT 0 are divided into four sub tables each providing a table pair for up to four PHYs The AMBASE APBASE and AMEND values used fo...

Page 1043: ...single unified CAM with the ADDR 25 31 signals used as part of the match data for the CAM See Section 39 1 3 CAM Address Mapping SRSTATE EXT ACP 10 NOTE PHYn uses RCTn as its default raw cell queue 39 6 2 Programming Slave Operation in a Multi PHY System The MPC885 should be programmed as if in single PHY mode when operating as a slave in a multi PHY environment That is if UTMODE RSL and or UTMODE...

Page 1044: ...PM initialization can start immediately after this command is issued Use RST to reset the registers and parameters for all the controllers as well as the CPM and RISC timer table RST does not however affect the serial interface or parallel I O registers 0 No reset issued 1 Reset issued 1 3 ATM OPCODE ATM opcode Contains the 3 bit opcode of the channel command See Table 39 8 000 Transmit activate c...

Page 1045: ...ble maximum latency of one full pass through the APC scheduling table STOP TRANSMIT ABORT 010 Instructs the transmitter to stop the channel specified in COMM_CH Channels are stopped on cell boundaries Transmission stops after the channel s current cell is next scheduled by the APC After the current cell is sent the BD is closed a new entry to the interrupt queue is optionally added for the channel...

Page 1046: ...rrupt Queue Entry In multi PHY mode COMM_CH2 should contain the PHY number The channel number specified in COMM_CH is inserted into the appropriate PHY transmit queue The channel number inserted by the APC_BYPASS command is placed at the front of the transmit queue and therefore becomes the next channel sent WRITE TO MEMORY 111 Write to memory location Allows the host to modify a memory location w...

Page 1047: ...aping parameters from the TCTs of each active transmit channel and uses a periodic table scanning algorithm often called calender based scheduling to determine the next channels to be scheduled Having identified the next channels it then places the channel numbers of the selected channels into the transmit queue The order in which the APC places channel numbers in the transmit queue is the order i...

Page 1048: ...of the APC timer the APC schedules up to NCITS channel numbers to the transmit queue starting from the first APC priority level If PTP is used it also schedules PTP channels as long as the PTP counter indicates that there are still PTP cells ready to be sent If the APC does not schedule NCITS channels for the first APC priority level it repeats the scheduling process for the second APC priority le...

Page 1049: ...nitialization each entry of the APC scheduling table should be programmed with 0xFFFF which is reserved as the invalid channel number Issuing the TRANSMIT ACTIVATE CHANNEL command to the CPM causes a channel s number to be inserted into the APC scheduling table at the entry pointed to by the table scan pointer APCT_PTRx Periodic timeouts of the APC timer activate the APC algorithm and cause the re...

Page 1050: ...grammed to provide a wide variety of transmit rates and support a large number of channels There are several important parameters which define its capabilities These include Cell scheduling rate This is determined by the timeout rate of the APC timer CPM timer 4 which defines the period of the scheduling time slots and the number of cells transmitted in a time slot NCITS The maximum of this rate i...

Page 1051: ...Also assume that no single ATM channel virtual connection will ever require more than 25 of this bandwidth By this assumption P max_rate is 4 and therefore NCITS is chosen to be 4 using the max_rate formula described above Also because the application has no single connection requiring a bandwidth less than 32kbps i e min_rate 32kbps the minimum APC scheduling table size is therefore equal to This...

Page 1052: ...al it is possible to use any value combination which leads to the desired period Be sure to choose the next largest period value from that which was calculated otherwise the transmit queue would eventually overrun as the APC scheduler would provide slightly more traffic than the physical layer can transmit Ensure that you do not define an arbitrarily short timer 4 period On each timer tick the APC...

Page 1053: ...e immediate pace between the 1st cell and 2nd cell of this AAL5 frame becomes OOBR which should be PCR according to VBR algorithm To solve this Tx underrun situation right before setting TxBD R bit software should first clear the BNR bit in the TCT Then the immediate pace between the 1st cell and 2nd cell of this AAL5 frame will be PCR 40 1 6 Programming Rates for VBR Channels The bit rate for a V...

Page 1054: ...vating UBR channels use the lowest APC priority level Since UBR channels typically use overbooking the total programmed bandwidth in the UBR table can be higher than the actual line rate Because the UBR channel is located at a lower APC priority level during operation the APC divides any remaining additional bandwidth among all UBR channels relative to the programmed APCP The total APC rate will e...

Page 1055: ...me whether the APC timer is active or inactive For more information see the description of the TRANSMIT ACTIVATE CHANNEL command Section 39 7 ATM Commands Also note that the physical interface serial or UTOPIA must be enabled and its associated clocks and synchronization signals must be active before the APC timer is activated Otherwise the transmit queue will simply overflow causing an APCO inter...

Page 1056: ...robed by the same the APC timer request which provides the common basic pace from which all the APCs one for each ATM port configured are scheduled The APC timer activates several independent sub timers in each APC implemented in the APCNT field of the APC parameters Scheduling of cells from a particular APC will occur only when APCNT exceeds one The APC timer should be programmed to supply an opt...

Page 1057: ... configured with four multi PHY SARs and three serial mode SARs Figure 40 5 Example of Maximum Multi PHY and Multi Serial APC Configuration 40 4 Using the APC Without Using SCC4 or UTOPIA As described in Section 40 3 Using the APC with Multiple ATM Ports the APC algorithm begins and terminates by referring to the APCST parameter on parameter page 4 Therefore the APCST parameter on parameter page 4...

Page 1058: ...mance for the APC as the receiver has higher priority and therefore degrades the paced bandwidth if overloaded An optional feature has been integrated to detect and correct temporary overload conditions that would otherwise result in lost APC bandwidth APC Flux Compensation will detect the condition and keep the APC active as required to compensate for the previously lost bandwidth A loss of APC b...

Page 1059: ... the required traffic parameters The APC can be configured to handle two n levels of priority through the configuration of APCST PL2 The APC first schedules channels from the first priority table scheduling up to NCITS channels from the APCT_PTR1 slot If there are fewer than NCITS channels in this slot and the PL2 bit is set the APC tries to select the rest of the channels from the second priority...

Page 1060: ...raps to point to the TQTPTR pointer If the transmit queue is full the APC does not insert more channels and the APCT_SPTR stalls until space is available in the transmit queue The depth of the transmit queue is equal to the number of entries minus 1 In single PHY mode TQBASE TQEND TQTPTR and TQAPTR are located in the parameter RAM In multi PHY master mode indicated by the MPHY and ESAR bits in the...

Page 1061: ...es belonging to the different PHY APC levels The unshaded portion of the table contains the parameters used to configure the first APC level while the shaded portion of the table contains the parameters used to configure the lower priority APC levels Table 40 1 APC Priority Levels Offset1 2 Name Width Description User Writes 0x00 APCT_BASE1 Half Word APC scheduling table First priority base pointe...

Page 1062: ...rd First priority PTP queue length 0000 0x1C PTP_TxCh Half Word First priority PTP channel User defined 0x1E Reserved 4 n 0x20 0x0 APCT_BASEn Half Word APC scheduling table base pointer for the N th priority APC level User defined n 0x20 0x2 APCT_ENDn Half Word N th table Length User defined n 0x20 0x4 APCT_PTRn Half Word N th APC scheduling table pointer APCT_BASEn value n 0x20 0x6 APCT_SPTRn Hal...

Page 1063: ...ling table and is set to the address of the last entry in the APC scheduling table 2 APCT_ENDn Last_Entryn 2 APCT_PTRn APC scheduling table pointer for the N th priority APC level Holds the location of the current APC time slot in the APC scheduling table The APC advances the pointer on every APC N timer timeout The APC scheduling table pointer should be initialized by the user to the APCT_BASEn v...

Page 1064: ...service pointer This parameter limits the time spent in a single APC routine thereby avoiding excessive APC latency The recommended start value for APC_MI is equal to the minimum value of TCT APCP of all channels multiplied by the number of configured priority levels The value is application dependent to a certain extent and may need to be adjusted It should be kept as low as possible for the appl...

Page 1065: ...1 12 13 14 15 Field APCOM LAST EQ ESAR MPY Reset UD UD Oper r W r W r W r W r W r W r W r W r W Bits Name Description 0 APCOM APC scheduling table overrun event mask for this APC priority level 0 APCO interrupts are enabled 1 APCO interrupts are disabled 1 Reserved 2 LAST Defines the last APC priority level for the specific PHY 0 This level is not the last 1 This level is the last 3 10 Reserved 11...

Page 1066: ...ST1 0x0018 Equal priority to APC scheduling table and PTP ESAR mode Address 0x21A PTP_COUNTER 0x0000 initialize the PTP counter Address 0x21C PTP_TxCh 0x0001 channel 1 is the PTP transmitting channel of this priority level 4 Program level2 Address 0x220 APCT_BASE2 0x0330 start address of APC scheduling table 2 Address 0x222 APCT_END2 0x0342 pointing to the next entry after the end of table table s...

Page 1067: ...host deactivate command the scheduling when VBR2 bit is set and the use of the leaky bucket credit mechanism in VBR Note that the flow describes the scheduling mechanism done for one cell in one APC level If NCITS 1 the flow may be repeated several times per APC request Note that the leaky bucket mechanism is always receiving one credit at the SCR rate and checked against BT maximum burst toleranc...

Page 1068: ...ATM Pace Control MPC885 PowerQUICC Family Reference Manual Rev 2 40 22 Freescale Semiconductor ...

Page 1069: ...d INTPTR is advanced After the CP writes the last entry in the queue W bit set it re initializes INTPTR to point to the base of the queue INTBASE For each event sent to an interrupt queue the CP decrements a down counter which has been initialized to a threshold number of interrupts When the counter reaches zero the controller s global interrupt SCCEx GINT or IDSR1 GINT is set The user controls ho...

Page 1070: ... 7 Field UTERR SYNC IQOV GINT GUN GOV Figure 41 2 UTOPIA Event Register IDSR1 and Mask Register IDMR1 Table 41 1 UTOPIA Event Register IDSR1 Field Descriptions Bits Name Description 0 1 Reserved 2 UTER R UTOPIA error When set indicates that a serious UTOPIA receiver protocol state machine error has occurred Note that during the initialization phase of the UTOPIA interface this indication could be ...

Page 1071: ...rting RxEnb while the internal FIFO is not ready RxClav is not asserted In this case a GOV interrupt is issued to indicate that the write attempt failed and the cell has been dropped 0 2 3 4 5 6 10 11 12 13 14 15 Field GLR GLT DCC SYNC IQOV GINT GUN GOV Figure 41 3 Serial ATM Event Register SCCE and Mask Register SCCM Table 41 2 Serial ATM Event Register SCCE Field Descriptions Bits Name Descripti...

Page 1072: ... error re initialize TSTATE by writing STFCR to the first byte MSB of the 32 bit value representing xSTATE clearing the second byte and leaving the third and fourth LSB of the 32 bit value representing xSTATE bytes as is Then the APC can be restarted by clearing APCST DIS This procedure results in corrupted transmit frames initially TSTATE should normally be modified only during system initializat...

Page 1073: ...bers Note however that no cells are lost only the cell rates of the channels belonging to this scheduling table have been diminished A scheduling table overrun occurs when 1 the programmed pace is greater than NCITS that is if NCITS 1 and 1 APCP1 1 APCP2 1 APCPn 1 2 the APCT_SPTR has stalled for some reason such as a full transmit queue or 3 this level s APC_MI is too low relative to higher APC pr...

Page 1074: ... has been received For AAL5 the buffer is not the last buffer in the frame indicated by RXF The RXB interrupt is also generated by other errors that occur when receiving in this case the error condition is reported in the RxBD This exception is enabled through the I bit in the RxBD or PTP BD 16 31 CHNUM _INDEX Channel number index This field represents the CH_CODE of the channel associated with th...

Page 1075: ...10 11 12 13 14 15 Field ATM UT DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 Reset 0 0 Oper R W Addr Offset to IMMR 0x972 PDPAR Figure 42 1 Port D Pin Assignment Register PDPAR Table 42 1 PDPAR Field Descriptions Bits Name Description 0 ATM ATM global enable 0 Disable ATM SAR functionality 1 Enable ATM SAR functionality 1 UT UTOPIA enable Determines whether the parameter RAM s page 4 S...

Page 1076: ...gured as described in the following sections 42 2 1 System Clock Control Register SCCR The receive and transmit UTOPIA clocks can be either internal or external and are selected in the UTOPIA mode register see Section 43 2 UTOPIA Mode Register UTMODE When an internal clock is used the system clock control register SCCR must be programmed to generate the desired UTOPIA clock frequency If both recei...

Page 1077: ...TMODE see Section 43 2 UTOPIA Mode Register UTMODE Table 42 3 shows the port programming to enable the UTOPIA signals on port B 0 26 27 29 30 31 Field As described in Section 14 6 1 System Clock and Reset Control Register SCCR DFUTP DFAUTP Reset 0 0 0 0 0 Oper R W R W R W R W R W Addr Offset to IMMR 0x280 SCCR Figure 42 2 System Clock Control Register SCCR Table 42 2 SCCR Field Descriptions for th...

Page 1078: ...2 In Slave Mode the UTOPIA signals are named from the UTOPIA Master s perspective PB31 Port B31 MII TXCLK RMII1 REFCLK SPISEL VDD PB30 Port B30 SPICLK SPICLK GND PB29 Port B29 SPIMOSI SPIMOSI V DD PB28 Port B28 BRGO4 SPIMISO SPIMISO SPIMOSI PB27 Port B27 BRGO1 I2CSDA I2CSDA V DD PB26 Port B26 BRGO2 I2CSCL I2CSCL GND PB25 Port B25 SMTXD1 RxAddr 3 TxAddr 3 PB24 Port B24 SMRXD1 TxAddr 3 RxAddr 3 SMRX...

Page 1079: ...b11 Muxed UTMODE SPLIT 0 Split UTMODE SPLIT 1 PC15 RxClav_Mux RxClav_Split_M TxClav_Split_S Table 42 5 Port D Pin Assignment Signal PDPAR 0 PDPAR 1 Input to On Chip Peripherals UT 0 UT 1 PDDIR 0 PDDIR 1 PDDIR 0 PDDIR 1 PD15 Port D15 L1TSYNCA UTPB 0 L1TSYNCA GND PD14 Port D14 L1RSYNCA UTPB 1 L1RSYNCA GND PD13 Port D13 L1TSYNCB UTPB 2 L1TSYNCB GND PD12 Port D12 L1RSYNCB UTPB 3 L1RSYNCB GND PD11 Port...

Page 1080: ...tion 43 2 UTOPIA Mode Register UTMODE 42 2 6 RISC Controller Configuration Register RCCR The RCCR DR1M DR0M bits must be set level sensitive IDMA request signals to enable UTOPIA operation Also program RCCR DRQP to 0b10 to give SCC transfers higher priority 42 2 7 UTOPIA Mode Initialization The following procedure is required for proper initialization of the UTOPIA interface 1 Because the UTOPIA p...

Page 1081: ...ter RAM If MRBLR is programmed with a non zero value the SCC operates in transparent mode Be sure to initialize the ATM parameters and data structures before enabling serial ATM operation because transfers begin as soon as the SCC is enabled in the GSMR The following sections describe the programming of the SCC registers for serial ATM operation 42 3 2 1 General SCC Mode Register GSMR To configure...

Page 1082: ...g TDM through the time slot assigner TSA See Section 20 2 TSA Implementation or Section 20 3 NMSI Configuration Note that a serial ATM port using the TSA can be connected to E1 T1 and xDSL line interface devices Either of the TDM ports can be used to provide this function 0 1 2 3 6 7 8 15 Field SCRAM COSET Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Oper R W R W R W R W R W R W R W R W R W R W R W R W R...

Page 1083: ...de Support for ATM side master mode or PHY side slave mode Supports external or internal UTOPIA clock up to 33 MHz in master mode in slave mode receive and transmit Expanded header support for up to 65 bytes including HEC with byte resolution Optional HEC insertion in expanded cell mode Includes FIFOs for three cells 2 for receive and 1 for transmit Independent receive and transmit configurations ...

Page 1084: ... master ATM side 1 The receive UTOPIA split bus is operating as slave PHY side 1 RCLK Receive auxiliary UTOPIA clock selector Valid in split bus mode only SPLIT 1 The UTOPIA clocks can be either generated internally using the system clock or supplied by an external clock 0 The auxiliary UTOPIA clock is internal See Section 42 2 1 System Clock Control Register SCCR UtpClk_Aux is an output 1 The aux...

Page 1085: ...ith PHY0 If PHY0 does not need attention polling proceeds to PHY1 and so on to the last PHY RSPYB applies to single PHY operation only Receive single PHY back to back cells 0 Disable back to back cell reception 1 Enable back to back cell reception 15 RHECI Receive HEC byte insertion in expanded cell mode REC 1 0 No HEC insertion in expanded cell 1 HEC insertion The cell HEC is read from the UTOPIA...

Page 1086: ...A Port A signals are available 25 LB Loopback mode 0 Normal mode 1 Internal loopback mode It is the user s responsibility to program one port Tx or Rx as master and the other as slave 26 27 ADDPI N Address pins Selects the number of valid TxAddr and RxAddr signals needed in the multi PHY environment master or slave mode 00 2 address signals addr 1 0 support up to 3 PHYs 01 3 address signals addr 2...

Page 1087: ...SOC_Mux I O TxSOC_Split_M O RxSOC_Split_S O UtpClk Port D RxClk_Mux and TxClk_Mux Opt2 TxClk_Split_M Opt 2 RxClk_Split_S Opt 2 UtpClk_Aux PCMCIAPort A OP 0 RxClk_Split_M Opt3 TxClk_Split_S Opt 3 TxEnb Port D TxEnb_Mux O TxEnb_Split_M O RxEnb_Split_S I RxEnb Port D RxEnb_Mux O RxEnb_Split_M O TxEnb_Split_S I TxClav Port B TxClav_Mux I TxClav_Split_M I RxClav_Split_S O RxClav Port C RxClav_Mux I RxC...

Page 1088: ...Figure 43 2 shows the UTOPIA split bus in slave mode Figure 43 2 UTOPIA Slave Interface with Split Bus 43 3 2 UTOPIA Muxed Bus Master Operation Only The UTOPIA muxed bus UTMODE SPLIT 0 operates as a single 8 bit UTOPIA data bus UTPB on port D pins with a single SOC signal SOC on port D pins The MPC885 controls as a master the direction of transfer with no simultaneous receive and transmit transact...

Page 1089: ...v is the next PHY to be serviced The PHY polling order can be round robin or fixed priority 43 3 4 UTOPIA Multi PHY Slave Operation The MPC885 should be programmed as if in single PHY mode when operating as a slave in a multi PHY system That is if UTMODE RSL and or UTMODE TSL are set the corresponding parameter RAM address mapping mechanism RCTs TCTs APC etc should be programmed for single PHY ope...

Page 1090: ...UTOPIA Interface MPC885 PowerQUICC Family Reference Manual Rev 2 43 8 Freescale Semiconductor ...

Page 1091: ...nism Reassembly Sequence number SN and parity check for each CPS Packet Length indication LI and CRC5 check for each cell OSF of the STF check valid value is less than 48 Segmentation Perform CPS PDU padding as needed Sequence number SN and parity generation for each cell CRC5 generation for the CPS PH The following restrictions apply when AAL2 functionality is enabled Serial ATM is not available ...

Page 1092: ...le used to implement the Timer CU mechanism AAL2_TxWait_PTR The wait pointer marking expired active buffers for the Timer CU mechanism Active BD AAL0 BD that points to the active buffer Active buffer The next AAL0 buffer to be processed or the buffer currently being processed by the AAL2 functionality The active buffer may be empty or partially filled APC ATM pace control for scheduling transmissi...

Page 1093: ... buffer it marks the TPD as available R 0 If TPD INT is set and the interrupt is not masked by AAL2_TCT TPI then an entry is added to the exception queue with the AAL2 bit and TXB bit set to signal the host that this CPS Packet has been processed The global interrupt count INT_CNT is also decremented If INT_CNT reaches zero the global interrupt GINT bit in the event register is set and an interrup...

Page 1094: ... current RPD of the channel s AAL2_Rx_Queue Checks the CPS PDU for errors If an error is detected an indication is written to the associated RPD and the CPS Packet is discarded See Section 44 5 1 Receive Packet Descriptor RPD for a description of the possible errors If a complete CPS Packet is retrieved from the active buffer the RPD will be marked as available to the host E 0 If RPD INT is set an...

Page 1095: ...e ready bit R in the TPD and the empty bit E in the RPD This is the same mechanism used for SCC TxBDs and RxBDs except that the ATM exception queue is used instead of an event register to signal when the AAL2 is ready to transfer control back to the host A TPD with R 0 not ready for transmission is available to the host A TPD and its packet are only processed after the host has set TPD R TPD R is ...

Page 1096: ...e AAL2_Tx_Queue After the CPS Packet associated with this TPD is packed into the active AAL0 buffer AAL2 returns to the beginning of the queue using the TPD pointed to by AAL2_TQ_BASE The number of TPDs in the queue is programmable and is determined only by the W bit Host writes this field during initialization AAL2 does not modify this field 0x00 3 INT Determines whether interrupt is generated af...

Page 1097: ...ociated with these TPDs has been packed Figure 44 2 AAL2_Tx_Queue Example 44 4 3 AAL2 Transmit Connection Table AAL2_TCT Each channel s AAL2_TCT shown in Figure 44 3 contains all the parameters used to pack the channel s CPS Packets The host should configure all AAL2_TCT fields during initialization 0x02 0 15 Reserved should be cleared 0x04 0 31 TP_PTR Transmit CPS Packet pointer TP_PTR points to ...

Page 1098: ...sm for this channel is enabled Host writes this field AAL2 does not modify this field 7 SU Start up bit Indicates to the AAL2 that this is the first time this TCT has been accessed The AAL2 clears this bit The host must set this field during initialization 8 9 Reserved should be cleared 10 TBM AAL2 TBSY interrupt mask This bit allows the user to mask the AAL2 TBSY interrupt AAL2 1 and TBSY 1 in th...

Page 1099: ... BD in the table is AAL2_TACT_PTR 4 TBDBASE AAL2_TACT_PTR field provides bits 14 29 of the offset bits 30 31 are always 00 Host should write TBASE to this field during initialization This pointer is advanced by the AAL2 0x28 AAL2_TQ_BAS E Pointer to the first TPD in the AAL2_Tx_Queue The actual address of the first TPD is AAL2_TQ_BASE 4 AAL2_TPD_BASE AAL2_TPD_BASE is the base pointer to the TPD sp...

Page 1100: ...of channel n ATM Line AAL0 Implementation AAL2 Implementation 60X Bus channel n Tx BD table cid 1 cid 19 cid 56 cell header AAL2_TQ_BASE R 0 TPD 0 R 1 TPD 2 R 1 TPD 3 PD Memory Space AAL2_TPD_BASE AAL2_TQ_PTR CPS PDU cid 1 AAL0 buffer Active AAL0 buffer AAL2_TCT AAL2_TACT_PTR TBASE TBASE BD memory space 256KBytes 256 Kbytes w 1 R 0 TPD 1 R 1 TPD 4 W 1 R 0 TPD 20 AAL0 TCT TBD_PTR channel n channel ...

Page 1101: ...ot have enough CPS Packets to fill a partially filled active buffer the AAL2 will wait to send the buffer If the active buffer is not filled with new CPS Packets the next time this channel is activated the buffer is still delayed in hopes of achieving a better utilization of the transmission line The Timer CU mechanism limits this delay The Timer CU mechanism is implemented using a wait table AAL2...

Page 1102: ...For each bit set in the current row the AAL2 will Pad the partially filled active buffer with zeros Close its BD R 1 The cell is sent the next time the channel is scheduled by the APC or the host issues an APC BYPASS command for the channel Clear the channel s bit in the wait table The wait pointer advances to the next row of the wait table thereby decreasing the wait time of all remaining partial...

Page 1103: ...d Channel 32 expires in three RISC timer periods Channel 37 expires in four RISC timer periods Note that if the partially filled active buffer is filled before its time expires AAL2 clears the channel s bit in the wait table 44 5 AAL2 Data Structures for Receive This section describes the AAL2 data structures used for receiving AAL2 packets 44 5 1 Receive Packet Descriptor RPD Similar to buffer de...

Page 1104: ...AL2_Rx_Queue 1 This is the last RPD in the AAL2_Rx_Queue After the CPS Packet associated with this RPD is retrieved from the active AAL0 buffer the AAL2 returns to the beginning of the queue using the RPD pointed to by AAL2_RQ_BASE The number of RPDs in the queue is programmable and is determined only by the W bit This bit is configured by the host during initialization and is not modified by AAL2...

Page 1105: ...th this RPD is not valid The host should clear this bit after processing the RPD Host should clear this bit during initialization 0x02 9 E3 Indicates whether the OSF of the STF contains a value of 48 or greater 0 OSF of the STF has value smaller than 48 1 OSF of the STF contains a value of 48 or greater the complete CPS PDU is discarded When this error is indicated the CPS Packet associated with t...

Page 1106: ...S Packet header of a packet overlapping a CPS PDU boundary 0 No HEC error occurred for the overlapping packet 1 A HEC error occurred for the overlapping packet if the value of the OSF is less than 47 processing starts at the octet pointed to by the OSF When this error is indicated the CPS Packet associated with this RPD is not valid Host should clear this bit after processing the RPD Host should c...

Page 1107: ... configured by host and is not modified by AAL2 4 10 Reserved should be cleared 11 RBM RBSY interrupt mask This bit allows the user to mask the RBSY interrupt AAL2 1 and RBSY 1 in the exception queue entry 0 RBSY interrupt is disabled Exception entry with AAL2 and RBSY indication will not be generated 1 RBSY interrupt is enabled Host writes this field AAL2 does not modify this field 12 OVM OVF int...

Page 1108: ...TR 4 RBDBASE AAL2_RACT_PTR field provides bits 14 29 of the offset bits 30 31 are always 00 Host should write RBASE to this field during initialization This pointer is advanced by the AAL2 0x08 AAL2_RQ_BASE Pointer to the first RPD in AAL2_Rx_Queue The actual address of the first TPD is AAL2_RQ_BASE 4 AAL2_RPD_BASE AAL2_RPD_BASE is the base pointer to the TPD space and is defined in the parameter ...

Page 1109: ...x_Queue of channel n ATM Line AAL0 Implementation AAL2 Implementation 60X Bus channel n Rx BD table cid 1 cid 19 cid 56 cell header AAL2_RQ_BASE E 1 RPD 0 E 0 RPD 2 E 0 RPD 3 PD Memory Space AAL2_RPD_BASE AAL2_RQ_PTR CPS PDU cid 1 Previous Active AAL0 buffer AAL2_RCT AAL2_RACT_PTR RBASE RBASE BD memory space 256KBytes 256 Kbytes w 1 E 1 RPD 1 E 0 RPD 4 W 1 E 1 RPD 20 AAL0 RCT RBD_PTR channel n cha...

Page 1110: ... However the following restrictions apply Because AAL2 uses only one set of global AAL2 structures each SCC should handle a unique set of AAL2 channel numbers No two SCCs should control the same AAL2 channel n AAL2 channel numbers can only be in the range 0 255 NOTE While the internal channels 0 31 can be used as AAL2 channels care should be taken that no conflict with possibly required raw cell q...

Page 1111: ...T 10 OFFSET 12 OFFSET 14 OFFSET 16 OFFSET 18 OFFSET 1A OFFSET 1C OFFSET 1E AAL2_TxWait_BASE AAL2_SCRATCH2_BASE _ AAL2_ECT_PTR_BASE AAL2_TPD_BASE AAL2_RPD_BASE AAL2_TxWait_width AAL2_TxWait_PTR IMMR 0x3FC0 AAL2_SCRATCH1_BASE OFFSET 20 AAL2_TxWait_LAST OFFSET 22 OFFSET 24 OFFSET 26 OFFSET 28 OFFSET 2A OFFSET 2C OFFSET 2E OFFSET 30 AAL2_CRC_PTR_BASE OFFSET 32 OFFSET 34 OFFSET 36 OFFSET 38 OFFSET 3A O...

Page 1112: ...start on a word boundary AAL2_ECT_PTR_BASE 30 31 00 Host writes this field during initialization see Section 44 7 2 Mapping the AAL2 Connection Tables in External Memory AAL2 does not modify this field 0x08 0x0A Reserved should be cleared 0x0C AAL2_SCRATCH2_BASE 16 bit pointer to a 256 byte scratch area in the DPR used by AAL2 during AAL2 operation This pointer should start on a half word boundary...

Page 1113: ...a Defines the starting location in external memory for a space of up to 256 KBytes where the TPDs of all AAL2_TxQueues reside The base pointer to a specific channel s AAL2_TxQueue is located in the channel s AAL2_TCT Host writes this field during initialization AAL2 does not modify this field 0x1C AAL2_RPD_BASE 32 bit base pointer to the global RPD area Defines the starting location in external me...

Page 1114: ... the DPR are as follows AAL2_SCRATCH1 area 512 bytes cleared during initialization AAL2_SCRATCH2 area 256 bytes cleared during initialization AAL2_TxWait_table if Timer CU mechanism is used APC scheduling tables and parameters the transmit queue and the raw cell queue AAL0 channel 0 CT Any remaining empty space in the DPR can be used for other structures 44 9 AAL2 Exceptions During AAL2 processing...

Page 1115: ...TBSY 1 indicates that AAL2 cannot maintain the current transmission rate The internal structures of the AAL2 are being overwritten The host should reconfigure the system 11 RBSY AAL2 1 and RBSY 1 indicates that AAL2 cannot keep up with the current receive rate The CPS PDU of the channel described in the CHNUM field may be lost The data rate at which the application tries to receive is too high The...

Page 1116: ... the host 44 10 Initialization of MPC885 for AAL2 Operation This section describes the initialization process for ATM channels running AAL2 on the MPC885 Because the AAL2 is built upon AAL0 operation the AAL0 data structures have to be in place to support AAL2 channels The user also must configure the data structures specific to AAL2 The Timer CU structure should also be initialized if any transmi...

Page 1117: ...burst aligned buffer in external memory AAL2 uses this pointer to access the CPS Packet Wrap bit should be set in the last PD W 1 in the receive and transmit PD queues The PD interrupt bit can be set INT 1 in certain PDs When INT 1 bit the PD will trigger the host to write read data to from the AAL2_Tx_Queue AAL2_Rx_Queue For better performance it is recommended to allocate at least 10 PDs for eac...

Page 1118: ...te at http www motorola com For example if a 50 MHz system is running AAL2 at 4 Mbps aggregate using a UTOPIA interface with an average packet size of 20 bytes the AAL2 channels utilize 50 of the CPM 4 Mbps out of the possible 8 Mbps In this case the user has 50 of the CPM bandwidth available for other purposes 44 12 PHY Interface AAL2 can support only T1 E1 rates per PHY line Faster input bursts ...

Page 1119: ... new AAL2 channels errors may be detected before synchronizing with the incoming data For example if the sequence number of the first CPS PDU is set AAL2 will detect an STF error When handling the first exception event for a new channel in the interrupt service routine the host application should ignore these errors All errors detected thereafter are valid ...

Page 1120: ...AAL2 Implementation MPC885 PowerQUICC Family Reference Manual Rev 2 44 30 Freescale Semiconductor ...

Page 1121: ...ted operations full descriptions of the supporting registers and initialization information Suggested Reading This section lists additional reading that provides background for the information in this manual MPC8xx Documentation Supporting documentation for the MPC885 can be accessed through the world wide web at http www freescale com This documentation includes technical specifications reference...

Page 1122: ...In certain contexts such as in a signal encoding or a bit field indicates a don t care n Indicates an undefined numerical value NOT logical operator AND logical operator OR logical operator Acronyms and Abbreviations Table VII 1 contains acronyms and abbreviations used in this document Table VII 1 Acronyms and Abbreviated Terms Term Meaning BD Buffer descriptor CPM Communication processor module C...

Page 1123: ...two FECs support 10 100 Mbps Ethernet through a media independent interface MII and or a reduced media independent interface RMII according to the RMII Specification March 20 1998 The RMII use a single reference clock 50 MHz and seven pins which are a proper subset of the MII interface pins All fast Ethernet controller features are the same in RMII mode as in MII mode 45 1 Features The following s...

Page 1124: ...nternal bus Figure 45 1 is a block diagram of the FECs Figure 45 1 FEC Block Diagrams The FEC complies with the IEEE 802 3 specification for 10 and 100 Mbps connectivity Full duplex 100 Mbps operation is supported at system clock rates of 40 MHz and higher A 25 MHz system clock supports 10 Mbps operation or half duplex 100 Mbps operation The implementation of bursting DMA reduces bus usage Indepen...

Page 1125: ...00 Mbps Ethernet and a seven wire serial interface for 10 Mbps Ethernet The interface mode is selected by R_CNTRL MII_MODE described in Section 45 3 2 20 Receive Control Register R_CNTRL Table 45 2 shows the 18 MII and the 10 RMII interface signals that are defined by the 802 3 standard Serial mode connections to the external transceiver are shown in Table 45 3 Table 45 2 MII and RMII Signals Sign...

Page 1126: ...es a need for an immediate retransmission When the end of the current BD is reached and TxBD L is set the frame check sequence 32 bit CRC is appended if TxBD TC 1 and TX_EN is negated After the frame check sequence is sent the FEC writes the frame status bits into the BD and clears the R bit When the end of the current BD is reached and the L bit is not set a frame consists of multiple buffers onl...

Page 1127: ... received and if address recognition has not rejected the frame the FEC starts transferring the incoming frame to the RxBD s associated buffer If the frame is a too short due to collision or is rejected by address recognition no receive buffers are filled Thus no collision frames are presented to the user except for any late collisions which indicate serious LAN problems When the data buffer has b...

Page 1128: ...ddress field If the DA is the individual unicast type of address the FEC compares the destination address field of the received frame with the 48 bit address that the user programs in the ADDR_LOW and ADDR_HIGH If the DA is the group type of address the FEC determines whether the group address is a broadcast address If it is the frame is accepted unconditionally otherwise multicast address a hash ...

Page 1129: ...nerate a number between 0 and 63 Bit 31 of the CRC result selects HASH_TABLE_HIGH bit 31 1 or HASH_TABLE_LOW bit 31 0 Bits 30 26 of the CRC result select the bit in the selected register If that bit is set in the hash table the frame is accepted otherwise it is rejected The result is that if eight group addresses are stored in the hash table and random group addresses are received the hash table p...

Page 1130: ...spacing of at least 28 bit times If an interrupted gap between receive frames is less than 28 bit times the receiver may discard the next frame 45 2 8 Collision Handling If a collision occurs during frame transmission the FEC continues transmitting for at least 32 bit times sending a JAM pattern of 32 ones If the collision occurs during the preamble sequence the JAM pattern is sent after the pream...

Page 1131: ...hat frame are then flushed and closed with the LC bit set in the last TxBD for that frame The FEC then continues to the next TxBD and begins sending the next frame Note The definition of what constitutes a late collision is hard wired in the FEC Heartbeat Some transceivers have a self test feature called heartbeat or signal quality error To signify a good self test the transceiver indicates a coll...

Page 1132: ...tware model is similar to that used by the 10 Mbps Ethernet implemented on the CPM To support higher data rates the FEC has a different internal architecture which changes the programming model slightly However efforts have been taken to minimize the differences required by the interrupt handlers The FEC s registers are very different from those of the CPM based internal Ethernet controller The FE...

Page 1133: ...e cleared 16 22 SEC Bits Described in Section 52 1 Communications Processor Timing Register CPTR 23 FEC1 RMII_FEC1 RMII MII1 interface mode 0 FEC1 MII interface and RMII logic reset 1 FEC1 RMII interface 24 FEC2 RMII_FEC2 RMII MII2 interface mode 0 FEC2 MII interface and RMII logic reset 1 FEC2 RMII interface 25 1TCI RMII1_TCI RMII1 Transmit Clock Invert 0 normal mode 1 FEC1 RMII internal transmit...

Page 1134: ... R_BUFF_SIZE Receive buffer size Section 45 3 2 7 Receive Buffer Size Register R_BUFF_SIZE 0x0E40 0x1E40 ECNTRL Ethernet control register Section 45 3 2 8 Ethernet Control Register ECNTRL 0x0E44 0x1E44 IEVENT Interrupt event register Section 45 3 2 9 Interrupt Event I_EVENT Interrupt Mask Register I_MASK 0x0E48 0x1E48 IMASK Interrupt mask register Section 45 3 2 9 Interrupt Event I_EVENT Interrupt...

Page 1135: ...34 0x1F34 FUN_CODE Function code to SDMA Section 45 3 2 19 DMA Function Code Register FUN_CODE 0x0F44 0x1F44 R_CNTRL Receive control register Section 45 3 2 20 Receive Control Register R_CNTRL 0x0F48 0x1F48 R_HASH Receive hash register Section 45 3 2 21 Receive Hash Register R_HASH 0x0F84 0x1F84 X_CNTRL Transmit control register Section 45 3 2 22 Transmit Control Register X_CNTRL 0 7 8 15 Field AD...

Page 1136: ...e ADDR_HIGH fields 45 3 2 3 RAM Hash Table High HASH_TABLE_HIGH The HASH_TABLE_HIGH register shown in Figure 45 7 contains the upper 32 bits of the 64 bit hash table used in address recognition for receive frames with a multicast address It is written by and must be initialized by the user 0 7 8 15 Field ADDR_HIGH BYTE 4 ADDR_HIGH BYTE 5 Reset Undefined R W R W Addr 0x0E04 FEC1 0x1E04 FEC2 16 31 F...

Page 1137: ... HASH_HIGH Reset Undefined R W R W Addr 0x0E08 FEC1 0x1E08 FEC2 16 31 Field HASH_HIGH Reset Undefined R W R W Addr 0x0E0A FEC1 0x1E0A FEC2 Figure 45 7 HASH_TABLE_HIGH Register Table 45 10 HASH_TABLE_HIGH Field Descriptions Bits Name Description 0 31 HASH_HIGH Contains the upper 32 bits of the 64 bit hash table used in address recognition for receive frames with a multicast address HASH_HIGH 0 cont...

Page 1138: ...y other protocols It provides a pointer to the start of the circular TxBD queue in external memory Table 45 11 HASH_TABLE_LOW Field Descriptions Bits Name Description 0 31 HASH_LOW Contains the lower 32 bits of the 64 bit hash table used in address recognition for receive frames with a multicast address HASH_LOW 0 contains hash index bit 31 HASH_LOW 31 contains hash index bit 0 0 15 Field R_DES_ST...

Page 1139: ...RC is always written into the last receive buffer To support frame lengths up to 1520 bytes R_BUFF_SIZE must be at least 0x0000_05F0 To ensure that R_BUFF_SIZE is a multiple of 16 bits 28 31 are forced to zeros Using buffers smaller than the recommended minimum 256 bytes increases the risk of receive FIFO overflow due to the overhead of opening and closing buffers 0 15 Field X_DES_START Reset Unde...

Page 1140: ... Addr 0x0E18 FEC1 0x1E18 FEC2 Bits 16 20 21 27 28 31 Field R_BUFF_SIZE Reset Undefined R W R W Addr 0x0E1A FEC1 0x1E1A FEC2 Figure 45 11 R_BUFF_SIZE Register Table 45 14 R_BUFF_SIZE Field Descriptions Bits Name Description 0 20 Reserved should be cleared by the host processor 21 27 R_BUFF_SIZE Receive buffer size 28 31 Reserved should be cleared by the host processor 0 15 Field Reset 0000_0000_000...

Page 1141: ...s write these fields to zero 29 FEC_PINMUX FEC enable Read write The user must set this bit to enable the FEC function in the 885 in conjunction with 885 pin multiplexing control 30 ETHER_EN Ethernet enable 0 A transfer is stopped after a bad CRC is appended to any frame being sent 1 The FEC is enabled and reception and transmission are possible The BDs for an aborted transmit frame are not update...

Page 1142: ...mit data buffers The transmit frame is not truncated 3 GRA Graceful stop complete A graceful stop initiated by the setting of GTS is complete GRA is set when the transmitter finishes sending any frame that was in progress when GTS was set 4 TFINT Transmit frame interrupt Indicates that a frame was sent and that the last corresponding BD was updated 5 TXB Transmit buffer interrupt A transmit buffer...

Page 1143: ...red at reset and by clearing ECNTRL ETHER_EN Table 45 17 IVEC Field Descriptions Bits Name Description 0 2 ILEVEL Interrupt level The ILEVEL is used to define the interrupt level 0 7 associated with the FEC interrupt one of the SIU internal interrupt sources 3 Reserved should be cleared by the host processor 4 5 Reserved should be cleared by the host processor This field may return unpredictable v...

Page 1144: ...ce a TxBD whose R bit is not set is polled X_DES_ACTIVE is cleared and polling stops until the bit is set signifying additional BDs have been placed into the TxBD ring X_DES_ACTIVE is cleared at reset and by clearing ECNTRL ETHER_EN 45 3 2 13 MII Management Frame Register MII_DATA Table 45 19 describes X_DES_ACTIVE fields Table 45 18 R_DES_ACTIVE Field Descriptions Bits Name Description 0 6 Reserv...

Page 1145: ... frame or 10 management register read frame and TA must be 10 Table 45 19 X_DES_ACTIVE Field Descriptions Bits Name Description 0 6 Reserved 7 X_DES_ACTIVE Set when this register is written regardless of the value written Cleared whenever no additional ready descriptors remain in the transmit ring 8 31 Reserved 0 1 2 3 4 8 9 13 14 15 Field ST OP PA RA TA Reset Undefined R W R W Addr 0x0E80 FEC1 0x...

Page 1146: ...read management frame operation completes At this time the contents of MII_DATA match the original value written except for the DATA field whose contents have been replaced by the value read from the PHY register Writing to MII_DATA during frame generation alters the frame contents Software should use the MII_DATAIO_COMPL interrupt to avoid writing to the MII_DATA register during frame generation ...

Page 1147: ...tion of system clock frequency 45 3 2 15 FIFO Receive Bound Register R_BOUND The R_BOUND register Figure 45 19 is a read only register the user can read to determine the upper address bound of the FIFO RAM Drivers can use this value along with the R_FSTART and X_FSTART to appropriately divide the available FIFO RAM between the transmit and receive data paths 25 30 MII_SPEED MII_SPEED controls the ...

Page 1148: ...ddresses from R_FSTART to R_BOUND inclusive Hardware initializes R_FSTART with a value that is microcode dependent after ECNTRL ETHER_EN is set R_FSTART only needs to be written to change the default value 0 15 Field Reset 0000_0000_0000_0000 R W Read only Addr 0x0ECC FEC1 0x1ECC FEC2 16 20 21 22 29 30 31 Field 1 R_BOUND Reset 0000_0100_0000_0000 R W Read only Addr 0x0ECE FEC1 0x1ECE FEC2 Figure 4...

Page 1149: ...nsmit FIFO underrun due to system bus contention 0 15 Field Reset 0000_0000_0000_0000 R W R W Addr 0x0ED0 FEC1 0x1ED0 FEC2 16 20 21 22 29 30 31 Field 1 R_FSTART Reset 0000_0000_0000_0000 R W R W Addr 0x0ED2 FEC1 0x1ED2 FEC2 Figure 45 20 R_FSTART Register Table 45 24 R_FSTART Field Descriptions Bits Name Description 0 21 Reserved Note all bits read back as 0 except for 21 which returns a 1 22 29 R_...

Page 1150: ...uld be cleared by the host processor 30 31 X_WMRK Transmit FIFO watermark Frame transmission begins when the number of bytes selected by this field have been written into the transmit FIFO or if an end of frame has been written to the FIFO or if the FIFO is full before the selected number of bytes have been written 0x 64 bytes written to the transmit FIFO 10 128 bytes written to the transmit FIFO ...

Page 1151: ...ed This bit reads as zero 1 2 DATA_BO Byte order Supplied to the SDMA interface during receive and transmit data DMA transfers 0x Reserved 1x Big endian Motorola or true little endian DEC or Intel byte ordering Considering each word in the buffer data bytes are received or transmitted from address 0b00 to 0b11 This is because communication is byte oriented and byte reads and writes are identical i...

Page 1152: ...h DA 0xFFFF_FFFF_FFFF are rejected unless the PROM bit set If both BC_REJ and PROM 1 frames with broadcast DA are accepted and RxBD M is set 28 PROM Promiscuous mode 0 Promiscuous mode disabled 1 Promiscuous mode enabled All frames are accepted regardless of address matching 29 MII_MODE Selects external interface mode for both transmit and receive blocks 0 Selects seven wire mode used only for ser...

Page 1153: ...ddr 0x0F4A FEC1 0x1F4A FEC2 Figure 45 25 R_HASH Register Table 45 29 R_HASH Field Descriptions Bits Name Description 0 7 Reserved for internal use When read these bits are unpredictable 8 20 Reserved These bits are read as zeros 21 31 MAX_FRAME_LENGTH User read write field Resets to decimal 1518 Length is measured starting at DA and includes the CRC at the end of the frame Transmit frames longer t...

Page 1154: ... Reserved These bits read as zero 29 FDEN Full duplex enable If set frames are transmitted independently of carrier sense and collision inputs This bit should be modified only when ECNTRL ETHER_EN is cleared 30 HBC Heartbeat control If HBC 1 and FDEN 0 the heartbeat check is performed after transmission and TxBD HB and IEVENT HBERR are set if the collision input does not assert within the heartbea...

Page 1155: ...ble 45 31 Hardware Initialization User System Register Machine Reset Value User ECNTRL Cleared User IEVENT Cleared User IMASK Cleared User MII_SPEED Cleared User PORT DPAR Cleared User PORT DIR Cleared Table 45 32 ECNTRL ETHER_EN Deassertion Initialization User System Register Machine Reset Value User R_DES_ACTIVE Cleared User X_DES_ACTIVE Cleared Table 45 33 User Initialization Before Setting ECN...

Page 1156: ...r For maximum user flexibility BDs are also located in external memory A buffer is produced by setting TxBD R or RxBD E Writing to either X_DES_ACTIVE or R_DES_ACTIVE indicates that a buffer is in external memory for the transmit or receive data traffic respectively The hardware reads the BDs and processes the buffers After the DMA transfer of the data and the updating of the BD status bits hardwa...

Page 1157: ... Table 45 35 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 E RO1 W RO2 L M BC MC LG NO SH CR OV TR 2 DATA LENGTH 4 RX BUFFER POINTER A 0 15 6 RX BUFFER POINTER A 16 31 Figure 45 27 Receive Buffer Descriptor RxBD Table 45 35 Receive Buffer Descriptor RxBD Field Description Bits Name Description 0 E Empty Written by the FEC and user Note that if the software driver sets RxBD E it should then write to R_DE...

Page 1158: ... bytes The hardware truncates frames exceeding 2047 bytes so as not to overflow receive buffers This bit is valid only if the L bit is set 11 NO Rx nonoctet aligned frame written by FEC A frame that contained a number of bits not divisible by 8 was received and the CRC check that occurred at the preceding byte boundary generated an error NO is valid only if the L bit is set If this bit is set the ...

Page 1159: ... at the end of the second frame for the second BD At the end of the third frame the first BD is read for a third time but now it has the R bit cleared so the FEC stops Since the default Tx FIFO size is 192 bytes and each frame requires at least 8 bytes 1 word of data plus an EOF word there should be at least 24 Tx BDs in the ring unless The SW ensures that there is always at least one TX BD with t...

Page 1160: ... valid if L 1 Set to indicate that the collision input was not asserted within the heartbeat window after transmission completed HB can be set only if X_CNTRL HBC 1 8 LC Late collision written by FEC valid if L 1 Set to indicate that a collision occurred after 56 data bytes were transmitted The FEC terminates the transmission 9 RL Retransmission limit written by FEC valid if L 1 Set to indicate th...

Page 1161: ... empties of data before the end of the frame In this case a bad CRC is appended to the partially transmitted data In addition the UN bit is set in the last BD in the current frame This situation can occur if the FEC cannot access the U bus or if the next BD in the frame is unavailable NOTE A software driver that sets TxBD R should then write to X_DES_ACTIVE ...

Page 1162: ...Fast Ethernet Controller FEC MPC885 PowerQUICC Family Reference Manual Rev 2 45 40 Freescale Semiconductor ...

Page 1163: ...gest Execution Unit MDEU Chapter 49 SEC Lite Descriptors describes the descriptors used to take SEC Lite through the security operations Chapter 50 SEC Lite Crypto Channel describes how the crypto channel manages data associated with one of more execution units Chapter 51 SEC Lite Controller describes the responsibility of the controller within the SEC Lite to oversee the operations of the executi...

Page 1164: ... to identify a destination GPR REG FIELD Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text Specific bits fields or numerical ranges appear in brackets For example MSR LE refers to the little endian mode enable bit in the machine state register x In certain contexts such as in a signal encoding or a bit field indicates a don t care n Indicates an undefined nu...

Page 1165: ...herefore referred to as the SEC Lite 46 2 Features The SEC Lite is designed to offload computationally intensive security functions such as message authentication and bulk encryption from the processor core of the MPC885 microprocessor It is optimized to process all the algorithms associated with IPSec SRTP and 802 11i SEC Lite includes the following features DEU Data Encryption Standard execution...

Page 1166: ...ystem memory to complete the required task Figure 46 1 SEC Lite Connected to the MPC885 Internal Bus 46 4 Architectural Overview A block diagram of the SEC Lite internal architecture is shown in Figure 46 2 The bus interface module is designed to transfer 32 bit words between the bus and any register inside the SEC Lite An operation begins with a write of a pointer to the crypto channel fetch regi...

Page 1167: ...ntext to Encrypt LEN_CTXIN PTR_CTXIN Length Pointer Number of bytes to be written Pointer to Context IV to be written into DES engine LEN_KEY PTR_KEY Length Pointer Number of bytes in key Pointer to block cipher key LEN_DATAIN PTR_DATAIN Length Pointer Number of bytes of data to be ciphered Pointer to data to perform cipher upon LEN_DATAOUT PTR_DATAOUT Length Pointer Number of bytes of data after ...

Page 1168: ...criptors the crypto channel skips any pointer that has an associated length of zero 46 6 Master Slave Interface The master slave interface manages communication between the SEC Lite internal execution units and the MPC885 internal bus All on chip resources are memory mapped and the target accesses and initiator writes from the SEC Lite must be addressed on word boundaries The SEC Lite will perform...

Page 1169: ...em to external memory as indicated by the data packet descriptor buffer 6 If multiple services requested go back to step 2 7 Reset the appropriate EU 8 Perform descriptor completion notification as appropriate This notification comes in one of two forms interrupt or header writeback modification and can occur at the end of every descriptor at the end of a descriptor chain or at the end of speciall...

Page 1170: ...shing With any hash algorithm the larger message is mapped onto a smaller output space therefore collisions are possible albeit not probable The 160 bit hash value is a sufficiently large space such that collisions are extremely rare The security of the hash function is based on the difficulty of locating collisions That is it is computation infeasible to construct two distinct but similar message...

Page 1171: ...andard memory latency and unconstrained use of an 66 Mhz 32 bit bus utilizing the 8xx bus protocol CPU availability for descriptor generation is not considered although this may be a constraint in some systems 1024 byte 223 109 118 100 163 136 107 1536 byte 247 114 124 105 176 144 112 Table 46 2 Estimated Bulk Data Encryption Performance Mbps continued DES CBC 3DES CBC AES 128 AES 256 MD5 SHA 1 3D...

Page 1172: ...SEC Lite Overview MPC885 PowerQUICC Family Reference Manual Rev 2 46 8 Freescale Semiconductor ...

Page 1173: ...emory Map Register IMMR Table 47 1 Module Base Address Map SEC Lite Address hex IMMR 14 15 10 SEC Lite Module Description Type 01000 01FFF Controller Arbiter Controller Control register space resource control 02000 02FFF Channel Crypto channel data control 04000 04FFF AESU AES Execution Unit Crypto EU 05000 05FFF DEU DES Execution Unit Crypto EU 06000 06FFF MDEU Message Digest Execution Unit Crypt...

Page 1174: ... 04020 04027 Reserved 8 Bytes 04028 AESU Status Register 64 bits R 04030 AESU Interrupt Status Register 64 bits R W 04038 AESU Interrupt Control Register 64 bits R W 04040 0404F Reserved 16 bytes 04050 AESU End of Message Register 64 bits W 04058 040FF Reserved 168 bytes 04100 AESU IV Register 64 bits R W 04108 043FF Reserved 760 bytes 04400 0441F AESU Key Memory 32 bytes R W 04420 047FF Reserved ...

Page 1175: ...U Data Size Register 64 bits R W 06018 MDEU Reset Control Register 64 bits R W 06020 06027 Reserved 8 bytes 06028 MDEU Status Register 64 bits R 06030 MDEU Interrupt Status Register 64 bits R W 06038 MDEU Interrupt Control Register 64 bits R W 06040 0604F Reserved 16 Bytes 06050 MDEU EU_GO 64 bits W 06058 060FF Reserved 168 bytes 06100 0611F MDEU Context Memory 32 bytes R W 06120 063FF Reserved 73...

Page 1176: ...SEC Lite Address Map MPC885 PowerQUICC Family Reference Manual Rev 2 47 4 Freescale Semiconductor ...

Page 1177: ...upporting The MD5 generates a 128 bit hash and the algorithm is specified in RFC 1321 SHA 1 a 160 bit hash function specified by the ANSI X9 30 2 and FIPS 180 1 standards SHA 256 a 256 bit hash function that provides 256 bits of security against collision attacks The MDEU also supports HMAC computations as specified in RFC 2104 Working together the EUs can perform high level cryptographic tasks su...

Page 1178: ...ister level access from the user The DEU contains the following registers DEU Mode Register Key Size Register Data Size Register Reset Control Register Status Register Interrupt Status Register Interrupt Control Register Go Register IV Register Key Registers FIFO 48 1 2 DEU Mode Register The DEU Mode Register contains 3 bits which are used to program the DEU It also reflects the value of burst siz...

Page 1179: ... Description 0 4 Reserved 5 CE CBC ECB If set DEU operates in cipher block chaining mode If not set DEU operates in electronic codebook mode 0 ECB mode 1 CBC mode 6 TS Triple Single DES If set DEU operates the Triple DES algorithm if not set DEU operates the single DES algorithm 0 Single DES 1 Triple DES 7 ED Encrypt decrypt If set DEU operates the encryption algorithm if not set DEU operates the ...

Page 1180: ...EU must be divisible by 64 bits or a data size error will occur In normal operation the full message length data size to be encrypted or decrypted by the DEU is copied from the descriptor to the DEU Data Size Register however only bits 2 7 are checked to determine if there is a data size error If 2 7 are all zeroes the message is evenly divisible into 64 bit blocks In target mode the user must wri...

Page 1181: ...Figure 48 4 allows 3 levels of reset for the DEU as defined by the 3 self clearing bits Figure 48 4 DEU Reset Control Register 0 1 2 7 8 31 Field Data Size msb lsb Reset 0 R W R W Addr DEU 0x05010 0 31 Field Reserved Reset 0x0000_0000 R W R W Addr DEU 0x05014 0 4 5 6 7 8 31 Field RI MI SR Reset 0x0000_0000 R W R W Addr DEU 0x05018 0 31 Field Reserved Reset 0x0000_0000 R W R W Addr DEU 0x0501C ...

Page 1182: ...0 Don t reset 1 Reset interrupt logic 6 MI Module initialization is nearly the same as software reset except that the interrupt control register remains unchanged this module initialization includes execution of an initialization routine completion of which is indicated by the RESET_DONE bit in the DEU status register 0 Don t reset 1 Reset most of DEU 7 SR Software reset is functionally equivalent...

Page 1183: ...f space is available in the FIFO The documentation of this bit in the DEU status register is to avoid confusing a user who may read this register in debug mode 4 OFR Output FIFO Readable The controller uses this signal to determine if the DEU can source the next burst size block of data 0 DEU Output FIFO not ready 1 DEU Output FIFO ready Note The crypto channel implements flow control to allow lar...

Page 1184: ...write address was detected within the DEU address space 0 No error detected 1 Address error 2 OFE Output FIFO error The DEU output FIFO was detected non empty upon write of DEU data size register 0 No error detected 1 Output FIFO non empty error 3 IFE Input FIFO error The DEU input FIFO was detected non empty upon generation of DONE interrupt 0 No error detected 1 Input FIFO non empty error 4 Rese...

Page 1185: ...register 2 is checked only if key size reg 16 or 24 0 No error detected 1 Key parity error 11 IE Internal Error An internal processing error was detected while performing encryption 0 No error detected 1 Internal error Note This bit will be asserted any time an enabled error condition occurs and can only be cleared by setting the corresponding bit in the Interrupt Control Register or by resetting ...

Page 1186: ...Output FIFO Error The DEU output FIFO was detected non empty upon write of DEU data size register 0 Output FIFO non empty error enabled 1 Output FIFO non empty error disabled 3 IFE Input FIFO Error The DEU input FIFO was detected non empty upon generation of done interrupt 0 Input FIFO non empty error enabled 1 Input FIFO non empty error disabled 4 Reserved 5 IFO Input FIFO Overflow The DEU input ...

Page 1187: ...E Key Parity Error The defined parity bits in the keys written to the key registers did not reflect odd parity correctly Note that key register 2 and key register 3 are only checked for parity if the appropriate DEU mode register bit indicates triple DES 0 Key parity enabled 1 Key parity error disabled 11 IE Internal Error An internal processing error was detected while performing encryption 0 Int...

Page 1188: ...te an address error interrupt 48 1 12 DEU FIFOs DEU uses an input FIFO output FIFO pair to hold data before and after the encryption process These FIFOs are multiply addressable but those multiple addresses point only to the appropriate end of the appropriate FIFO A write to anywhere in the DEU FIFO address space causes the 64 bit word to be pushed onto the DEU input FIFO and a read from anywhere ...

Page 1189: ... also reflects the value of the burst size which is loaded by the crypto channel during normal operation with the MDEU as an initiator Burst size is not relevant to target mode operations where an external host pushes and pulls data from the execution units The mode register is cleared when the MDEU is reset or re initialized Setting a reserved mode bit will generate a data error If the mode regis...

Page 1190: ...algorithm specific initialization of the digest registers Most operations will require this bit to be set Only static operations that are continuing from a know intermediate hash value would not initialize the registers 0 Do not initialize 1 Initialize the selected algorithm s starting registers 4 HMAC Identifies the hash operation to execute 0 Perform standard hash 1 Perform HMAC operation This r...

Page 1191: ... data in bits to be processed The first three bits are used to check for a bit offset in the last byte of the message Since the engine does not support bit offsets any value other than 0 in these positions will cause a data size error The next three bits are used to identify the ending byte location in the last 8 byte dword This is used to add the data padding when auto padding is selected This re...

Page 1192: ...48 12 allows 3 levels reset of just the MDEU as defined by the 3 self clearing bits Figure 48 12 MDEU Reset Control Register 0 1 2 7 8 31 Field Data Size msb lsb Reset 0x0000_0000 R W R W Addr MDEU 0x06010 0 31 Field Reserved Reset 0x0000_0000 R W R W Addr MDEU 0x06014 0 4 5 6 7 8 31 Field RI MI SR Reset 0x0000_0000 R W R W Addr MDEU 0x06018 0 31 Field Reserved Reset 0x0000_0000 R W R W Addr MDEU ...

Page 1193: ...ion 0 4 Reserved 5 RI Reset Interrupt Writing this bit active high causes MDEU interrupts signalling DONE and ERROR to be reset It further resets the state of the MDEU interrupt status register 0 No reset 1 Reset interrupt logic 6 MI Module initialization is nearly the same as software reset except that the MDEU Interrupt control register remains unchanged 0 No reset 1 Reset most of MDEU 7 SR Soft...

Page 1194: ...SIZE block of data 0 MDEU Input FIFO not ready 1 MDEU Input FIFO ready Note The crypto channel implements flow control to allow larger than FIFO sized blocks of data to be processed with a single key IV The MDEU signals to the crypto channel that a burst size amount of space is available in the FIFO The documentation of this bit in the MDEU status register is to avoid confusing a user who may read...

Page 1195: ... the MDEU address space 0 No error detected 1 Address Error 2 4 Reserved 5 IFO Input FIFO Overflow The MDEU Input FIFO has been pushed while full 0 No overflow detected 1 Input FIFO has overflowed Note When operating as a master the crypto channel implements flow control and the FIFO size is not a limit to data input When operated as a target the MDEU cannot accept FIFO inputs larger than 512 Byte...

Page 1196: ... of the error interrupt signal and causing the module to halt processing Figure 48 15 MDEU Interrupt Control Register 13 CE Context Error The MDEU Key Register Key Size Register or Data Size Register was modified while MDEU was hashing 0 No error detected 1 Context error 14 KSE Key Size Error A value greater than 512 bits was written to the MDEU key size register 0 No error detected 1 Key size err...

Page 1197: ...ts Name Description 0 ME Mode Error An illegal value was detected in the mode register 0 Mode error enabled 1 Mode error disabled 1 AE Address Error An illegal read or write address was detected within the MDEU address space 0 Address error enabled 1 Address error disabled 2 4 Reserved 5 IFO Input FIFO Overflow The MDEU input FIFO has been pushed while full 0 Input FIFO overflow error enabled 1 In...

Page 1198: ... a previous hash Reading these registers provide the resulting message digest or HMAC along with an aggregate bit count NOTE SHA 1and SHA 256 are big endian MD5 is little endian The MDEU module internally reverses the endianness of the five registers A B C D and E upon writing to or reading from the MDEU context if the MDEU mode register indicates MD5 is the hash of choice Most other endian consid...

Page 1199: ...FIFO A write to anywhere in the MDEU FIFO address space causes the 64 bit words to be pushed onto the MDEU input FIFO and a read from anywhere in the MDEU FIFO address space causes the address error bit of the interrupt status register to be set NOTE SHA 1 and SHA 256 are big endian MD5 is little endian The MDEU module internally reverses the endianness of the key upon writing to or reading from t...

Page 1200: ...s from the user The AESU contains the following registers AESU Mode Register Key Size Register Data Size Register Reset Control Register Status Register Interrupt Status Register Interrupt Control Register End Of Message Register IV Registers Key Registers AESU FIFOs 48 3 2 AESU Mode Register The AESU Mode Register shown in Figure 48 18 contains 3 bits which are used to program the AESU It also re...

Page 1201: ...e context switch 5 6 CM Cipher Mode Controls which cipher mode the AESU will use in processing 00 ECB Electronic Codebook mode 01 CBC Cipher Block Chaining mode 10 Reserved 11 CTR Counter Mode 7 Encrypt Decrypt If set AESU operates the encryption algorithm if not set AESU operates the decryption algorithm Note This bit is ignored if CM is set to 11 CTR Mode 0 Perform decryption 1 Perform encryptio...

Page 1202: ...escriptor type used in decryption of the first portion of the message is 0100 AESU Key Expand Output The AESU mode must be Decrypt See Chapter 4 Descriptors for more information The descriptor will cause the SEC Lite to write the contents of the Context registers and the key registers containing the expanded decrypt key to memory To process the remainder of the message use a common descriptor type...

Page 1203: ...ed or decrypted with the AESU is copied from the descriptor to the AESU data size register however only bits 1 7 are checked to determine if there is a data size error If 1 7 are all zeroes the message is evenly divisible into 128 bit blocks This register is cleared when the AESU is reset or re initialized If a data size other than 128 bits is specified an illegal data size error will be generated...

Page 1204: ...ld Data Size msb lsb Reset 0x0000_0000 R W R W Addr AESU 0x04010 0 31 Field Reserved Reset 0x0000_0000 R W R W Addr AESU 0x04014 0 4 5 6 7 8 31 Field RI MI SR Reset 0x0000_0000 R W R W Addr AESU 0x04018 0 31 Field Reserved Reset 0x0000_0000 R W R W Addr AESU 0x0401C Table 48 13 AESU Reset Control Register Field Descriptions Bits Names Description 0 4 Reserved 5 RI Reset Interrupt Writing this bit ...

Page 1205: ...ich is indicated by the RESET_DONE bit in the AESU status register 0 Don t reset 1 Reset most of AESU 7 SR Software reset is functionally equivalent to hardware reset the RESET pin but only for AESU All registers and internal state are returned to their defined reset state Upon negation of SW_RESET the AESU will enter a routine to perform proper initialization of the parameter memories The RESET_D...

Page 1206: ...mount of space is available in the FIFO The documentation of this bit in the AESU status register is to avoid confusing a user who may read this register in debug mode 4 OFR Output FIFO Readable The controller uses this signal to determine if the AESU can source the next burst size block of data 0 AESU Output FIFO not ready 1 AESU Output FIFO ready Note The crypto channel implements flow control t...

Page 1207: ...as detected within the AESU address space 0 No error detected 1 Address error 2 OFE Output FIFO Error The AESU output FIFO was detected non empty upon write of AESU data size register 0 No error detected 1 Output FIFO non empty error 3 IFE Input FIFO Error The AESU input FIFO was detected non empty upon generation of done interrupt 0 No error detected 1 Input FIFO non empty error 4 Reserved 5 IFO ...

Page 1208: ... while the AESU was processing 0 No error detected 1 Internal error Note This bit will be asserted any time an enabled error condition occurs and can only be cleared by setting the corresponding bit in the Interrupt Control Register or by resetting the AESU 12 ERE Early Read Error The AESU IV Register was read while the AESU was processing 0 No error detected 1 Early read error 13 CE Context Error...

Page 1209: ... disabled 1 AE Address Error An illegal read or write address was detected within the AESU address space 1 Address error disabled 0 Address error enabled 2 OFE Output FIFO Error The AESU Output FIFO was detected non empty upon write of AESU data size register 0 Output FIFO non empty error enabled 1 Output FIFO non empty error disabled 3 IFE Input FIFO Error The AESU Input FIFO was detected non emp...

Page 1210: ...e 3 64 bit context data registers that allow the host to read write the contents of the context used to process the message The context must be written prior to the key data If the context registers are written 11 IE Internal Error An internal processing error was detected while the AESU was processing 0 Internal error enabled 1 Internal error disabled 12 ERE Early Read Error The AESU IV Register ...

Page 1211: ...significant bytes of the initialization vector bytes 9 16 The IV must be written prior to the message data If the IV registers are written during message processing or the CBC mode bit is not set a context error will be generated The IV registers may only be read after processing has completed as indicated by the assertion of Interrupt Done DONE in the AESU status register as shown in Section 48 3...

Page 1212: ... set in the mode register This eliminates the overhead of expanding the key prior to starting decryption when switching context 48 3 9 5 AESU FIFOs The AESU fetches data 128 bits at a time from the input FIFO During processing the input data is encrypted or decrypted with the key and initialization vector CBC mode only and the results are placed in the output FIFO The output size is the same as th...

Page 1213: ... the final message block must be set in the data size register Reading from the FIFO address space will pop 64 bits of message data from the output FIFO The output FIFO may be read any time the OFR signal is asserted as indicated in the AESU status register This will indicate that the number of bytes in the output FIFO is at or above the threshold specified in the mode register ...

Page 1214: ...SEC Lite Execution Units MPC885 PowerQUICC Family Reference Manual Rev 2 48 38 Freescale Semiconductor ...

Page 1215: ... Lite data packet descriptors are conceptually similar to descriptors used by most devices with DMA capability See Figure 49 1 for a conceptual data packet descriptor The descriptors are fixed length 64 bytes and consist of sixteen 32 bit fields Descriptors begin with a header that describes the security operation to be performed and the mode the execution unit will be set to while performing the ...

Page 1216: ...egister 12 23 OP_1 OP_1 contains two sub fields EU_Select and Mode_Data Figure 49 3 shows the sub field detail EU_SELECT 12 15 Programs the channel to select a secondary EU of a given type Table 49 2 lists the possible EU_SELECT values MODE_DATA 16 23 Programs the secondary EU mode data The mode data is specific to the chosen EU This data is passed directly to bits 0 7 of the specified EU mode reg...

Page 1217: ...e input FIFO of the primary EU is in progress the secondary EU always MDEU will snoop the same data into its input FIFO In snoop output data mode the secondary EU always MDEU will snoop data into its input FIFO during the bus transaction to read data out of the output FIFO of the primary EU Note When snooping is not performed this bit is ignored by the SEC Lite crypto channel 31 DN DONE_NOTIFICATI...

Page 1218: ... next pair The pointer field contains the address in global memory of the first byte of the data block Transfers with the pointer address set to zero will have the length value written to the EU and no data fetched from the memory Figure 49 4 shows the descriptor length field 0100 Reserved EU 0101 Reserved EU 0110 AESU Others Reserved EU Table 49 3 Descriptor Types Value Descriptor Type Notes 0000...

Page 1219: ...n be temporarily locked static and data only descriptors can be chained to fetch blocks larger than 32K bytes in 32K byte sub blocks without key context switching until the large original block has been completely ciphered Length fields also indicate the size of items to be written back to memory upon completion of security processing in the SEC Lite 0 31 Field DATA FIELD POINTER Reset 0 R W R W F...

Page 1220: ...d by the SEC Lite by filling the next data packet field with the address of the newly created descriptor Whether or not processing continues automatically following next descriptor fetch and whether or not an interrupt is generated depends on the programming of the Crypto Channel s Configuration Register Table 49 6 Descriptor Length Pointer Mapping Descriptor Type L P 1 L P 2 L P 3 L P 4 L P 5 L P...

Page 1221: ...T DPD DES CTX_CRYPT LEN_CTXIN PTR_CTXIN LEN_KEY PTR_KEY LEN_DATAIN PTR_DATAIN LEN_DATAOUT PTR_DATAOUT LEN_CTXOUT PTR_CTXOUT nul length nul pointer nul length nul pointer PTR_NEXT DPD DES CTX_CRYPT LEN_CTXIN PTR_CTXIN LEN_KEY PTR_KEY LEN_DATAIN PTR_DATAIN LEN_DATAOUT PTR_DATAOUT LEN_CTXOUT PTR_CTXOUT nul length nul pointer nul length nul pointer PTR_NEXT DPD DES CTX_CRYPT LEN_CTXIN PTR_CTXIN LEN_KE...

Page 1222: ...ites the permuted data back to memory and writes the HMAC and any altered context IV back to memory This may be necessary when DES is operating in CBC mode with implicit IV Upon completion of the descriptor the DEU and MDEU is cleared and released Table 49 8 Descriptor_HMAC_Snoop_Non_AFEU Field Value Type Description HMAC_Snoop_Non_AFEU 0x2073_FC20 Typical IPSec descriptor With 3DES HMAC SHA 1 LEN...

Page 1223: ...er in the assigned EU after requesting a write to EU key address space Automatically initialize data size register in the assigned EU before requesting a write to EU FIFO address space Automatically initialize the EU_GO register where applicable in the assigned EU upon completion of last EU write indicated by the descriptor The channel will wait for a indication from the EU that processing of inpu...

Page 1224: ... shown in Figure 50 1 Table 50 1 describes the CCCR Figure 50 1 Crypto Channel Configuration Register 0 31 Field Reserved Reset 0 R W R W Addr 0x02008 0 20 21 23 24 26 27 28 29 30 31 Field Burst Size WE NE NT CDIE R Reset 0 R W R W Addr 0x0200C Table 50 1 Crypto Channel Configuration Register Fields Bits Name Reset Value Description 0 20 Reserved 0 Reserved set to zero 21 23 Burst size 0 The SEC L...

Page 1225: ... descriptor chain into its descriptor buffer 0 Disable fetching of next descriptor when crypto channel has finished processing the current one 1 Enable fetching of next descriptor when crypto channel has finished processing the current one The address of the next descriptor in a multi descriptor chain is either the contents of the next descriptor pointer in the descriptor buffer or the contents of...

Page 1226: ...ne interrupt enabled When CDIE is set the NOTIFICATION_TYPE control bit determines when the CHANNEL_DONE interrupt is asserted Channel error interrupts are asserted as soon as the error is detected Refer to Section 50 2 Interrupts for complete description of crypto channel interrupt operation 31 R 0 Reset crypto channel This bit allows the crypto channel to be software reset 0 Automatically cleare...

Page 1227: ...es exactly which stage the crypto channel is in the sequence of fetching and processing data descriptors Table 50 5 shows the meaning of all possible values of the STATE field Note State is documented for information only The user will not typically care about the crypto channel state machine 0 4 5 6 7 8 9 10 11 12 13 14 15 16 23 24 31 Field Stat MI MO PR SR PG SG PRD SRD PD SD Error PAIR_PTR Rese...

Page 1228: ...t is set when descriptor processing is initiated in dynamic mode and the Op_1 field in the descriptor header contains a valid EU identifier This bit is cleared when the request is granted which will be reflected in the status register by the setting the SEC_GRANT bit 10 PRI_GRANT 0 Primary EU granted The PRI_GRANT bit reflects the state of the EU grant signal for the requested primary EU from the ...

Page 1229: ... field will reflect the source of the error The bits in the ERROR field are registered at specific stages in the descriptor processing flow Once registered an error can only be cleared only by resetting the crypto channel or writing the appropriate registers to initiate the processing of a new descriptor Table 50 6 lists the conditions which can cause a crypto channel error and how they are repres...

Page 1230: ... 0x19 Write_key_size 0x1A Write_eu_go 0x1B Delay_pri_done 0x1C Write_reset_irq_pri 0x1D Write_reset_irq_sec 0x1E Write_datasize_sec_snoopout 0x1F Trans_request_write_snoopout 0x20 Delay_sec_done 0x21 Trans_request_write 0x22 Evaluate_reset 0x23 Reset_write_reset_pri 0x24 Reset_release_pri_eu 0x25 Reset_write_reset_sec 0x26 Reset_release_sec_eu 0x27 Reset_channel 0x28 Write_datasize_pri_post 0x29 R...

Page 1231: ...an EU requested by the descriptor or the dynamic assignment request is unfillable because all suitable EUs are otherwise statically assigned 0bxxxx_x1xx Illegal descriptor header 0bxxxx_1xxx Parity error A parity error was detected on the 8xx bus by the controller on behalf of this channel 0bxxx1_xxxx Pointer not complete Caused by an invalid write to the next descriptor register in the descriptor...

Page 1232: ...eld Current Descriptor Pointer Address Reset 0x0000_0000 R W R W Addr 0x02044 Table 50 8 Crypto Channel Current Descriptor Pointer Register Fields Bits Name Reset Value Description 0 31 CUR_DES_PTR_ADRS 0 Pointer to system memory location of the current descriptor This field reflects the starting location in system memory of the descriptor currently loaded into the DB This value is updated wheneve...

Page 1233: ...e FR must be written to before the channel begins end of descriptor notification If the register is written after notification has begun the descriptor will not be considered part of the current chain and will be fetched as a new stand alone descriptor or start of chain after the notification process has completed In summary a channel is initiated by a direct write to the FR and the channel always...

Page 1234: ... system memory space Word 16 contains an extra register referred to as the Next Descriptor Pointer register which contains a pointer to the next descriptor to be processed if any The pointer is set to zero for a single descriptor or the end of a multi descriptor chain A descriptor is considered DONE only when the contents of word 16 have been processed by the channel Additional information on the ...

Page 1235: ...urst read of the next data packet descriptor This automatic load of the next descriptor is referred to as descriptor chaining Chapter 5 Descriptors contains a full description of the next descriptor pointer NOTE The next descriptor pointer address must be modulo 4 aligned if write back is enabled as the method of DONE notification 50 2 Interrupts The crypto channel can assert both DONE and ERROR i...

Page 1236: ...annel configuration register CCCR The effect of software reset on the channel varies according to what the channel is doing when the bit is set If the RESET bit is set while the crypto channel is requesting a EU assignment from the controller the crypto channel will cancel its request by asserting the release output signals The crypto channel will then reset all the registers clear the RESET bit a...

Page 1237: ...pto channel Monitor interrupts from the channel and pass to host Realign initiator read data to dword boundary 51 1 Controller Registers The Controller contains the following registers which are described in detail in the following sections Interrupt Mask Register Interrupt Status Register Interrupt Clear Register ID Register Master Control Register Master Error Address Register 51 1 1 Interrupt M...

Page 1238: ... The ISR contains fields representing all possible sources of interrupts The Interrupt Status Registers are cleared either by a reset or by writing the appropriate bits active in the Interrupt Clear Register Figure 51 3 shows the bit positions of potential interrupt sources indicated in Interrupt Status Register 1 0 1 2 3 4 15 Field CHA Definition Err Dn Reset 0x0000 R W R W Addr 0x 01008 16 31 Fi...

Page 1239: ...ers ICR The Interrupt Control Registers provides a means of clearing the Interrupt Status Registers When a bit in the ICR is written with a 1 the corresponding bit in the ISR is cleared clearing the interrupt output pin IRQ assuming the cleared bit in the ISR is the only interrupt source If the input source to the ISR is a 0 1 2 3 4 15 Field CHA Definition Err Dn Reset 0x0000 R W R W Addr 0x 01010...

Page 1240: ... cause them If the cause of an interrupt is not removed the interrupt will return a few cycles after it has been cleared using the ICR Figure 51 5 shows the bit positions of each interrupt source that can be cleared by Interrupt Clear Register 1 Figure 51 5 Interrupt Clear Register 1 Figure 51 6 shows the bit positions of potential interrupt source indicated in Interrupt Clear Register 2 A complet...

Page 1241: ...its Name Reset Value Description 0 1 0 Reserved set to zero 2 3 CHA_Err_Dn 0 The channel has Error Done bits 0 No error detected 1 Error detected Indicates that execution unit status register must be read to determine exact cause of the error 0 Not DONE 1 DONE bit indicates that the interrupting channel or EU has completed its operation 4 31 0 Reserved set to zero Table 51 2 Interrupt Mask Status ...

Page 1242: ...t execution unit status register must be read to determine exact cause of the error 0 Not DONE 1 DONE bit indicates that the AESU has completed its operation 20 21 0 Reserved set to zero 22 23 DEU_Err_Dn 0 The DEU has Error Done bits 0 No error detected 1 Error detected Indicates that execution unit status register must be read to determine exact cause of the error 0 Not DONE 1 DONE bit indicates ...

Page 1243: ...orting the TEA reset the whole SEC Lite or reset the entire system with a machine check error In any case the host may chose to preserve this TEA information prior to reset to assist in debug The MEAR only holds the address of the first error reported in the event multiple errors are received before the first is cleared Figure 51 9 Master Error Address Register 0 6 7 8 27 28 29 31 Field SWR GI Res...

Page 1244: ...nual Rev 2 51 8 Freescale Semiconductor Table 51 4 defines the Master Error Address Register bits Table 51 4 Master Error Address Register Bit Definitions Bits Name Reset Value Description 0 31 ADDRESS 0 Target address of the transaction when TEA was received ...

Page 1245: ...d Write Addr 0x0ADC 16 18 19 20 22 23 24 25 26 27 28 29 30 31 Field SEC_INT SEC_BO SEC_AT1 AT3 FEC1 FEC2 1TCI 2TCI RE1 RE2 Reset 0000_0000 R W Read Write Addr 0x0ADE Figure 52 1 CPTR Register Table 52 1 CPTR SEC Lite Related Field Descriptions Bits Name Description 0 15 Reserved should be cleared 16 18 SEC_INT SEC Lite Interrupt Level 000 Level 0 001 Level 1 010 Level 2 011 Level 3 100 Level 4 101...

Page 1246: ... read request or a write request to the Master Slave Interface Module When the bus becomes available the channel must be able to supply take data immediately NOTE Target accesses take priority over initiator accesses It is possible that an initiator access can be interrupted internal to the SEC Lite by a target access This occurs when a request has been made to the Master Interface for initiator a...

Page 1247: ...A in the Figure 51 9 52 2 4 Master Write Master writes are performed by transferring data from one of the EUs to the output FIFO in the controller then transferring the data from the FIFO to the bus when the bus is granted to the controller The sequence for a Master bus write access is as follows Channel requests the bus from controller Controller acknowledges request to channel Channel furnishes ...

Page 1248: ...he controller simply responds to read and write commands from the bus When a write command is received from the bus the controller takes the data from the Master Slave Interface Module and sends it to whichever internal location is indicated by the address For a read the controller goes to the internal location and fetches the requested data from the specified address Target accesses from the bus ...

Page 1249: ...ible with the IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Suggested Reading This section lists additional reading that provides background for the information in this manual MPC8xx Documentation Supporting documentation for the MPC885 can be accessed through the world wide web at http www freescale com This documentation includes technical specifications reference material...

Page 1250: ...cal value Acronyms and Abbreviations Table IX 1 contains acronyms and abbreviations used in this document Note that the meanings for some acronyms such as SDR1 and DSISR are historical and the words for which an acronym stands may not be intuitively obvious Table IX 1 Acronyms and Abbreviated Terms Term Meaning BIST Built in self test CPM Communication processor module IEEE Institute of Electrical...

Page 1251: ...ection 53 5 1 3 Instruction Support Control Register ICTRL describes programming of the core to operate in this mode The MPC885 implements a prefetch queue combined with parallel out of order and pipelined execution These features plus the fact that most fetch cycles are performed internally from the I cache increase performance but make it very difficult to provide the user with the real program ...

Page 1252: ...elopment port or by programming ISCT_SER in the instruction support control register ICTRL For more information on VSYNC see Section 53 3 2 Development Port Communication Both states described here are subsequently referred to as VSYNC state The VSYNC state forces all fetch cycles marked with the program trace cycle attribute to be visible on the external bus even if their data is found in one of ...

Page 1253: ...ow cycles are performed 1 X11 All indirect change of flow Table 53 2 Status Pin Groupings Pins Description VF 0 2 Instruction queue status Denotes the type of the last fetched instruction or how many instructions were flushed from the instruction queue VF 0 2 are used for both functions because queue flushes occur only in clocks in which no fetch type information is reported Table 53 3 defines ins...

Page 1254: ...ug mode VF 0b000 and VFLS 0b11 For more information on debug mode see Section 53 3 Development System Interface 100 Four instructions were flushed from the instruction queue Instruction type information 101 Five instructions were flushed from the instruction queue Instruction type information 110 Reserved Instruction type information 111 See VF 0b111 entry in Table 53 4 Table 53 4 VF Pins Encoding...

Page 1255: ...attribute Although program trace can be used in various ways the following describes only back trace and window trace 53 1 5 1 Back Trace Back trace is useful when a record of the program trace before an event occurred is needed An example of such an event is a system failure If back trace is needed external hardware should start sampling VF and VFLS and the address of all cycles marked with the p...

Page 1256: ...regular code run The first report on the VF pins is VSYNC VF 0b011 9 The external hardware starts sampling the program trace information after the VF pins indicate VSYNC 10 The hardware generates a breakpoint when the event in question is detected and the machine enters debug mode 11 Negate VSYNC 12 Return to the regular code run issue an rfi The first encoding on the VF pins is VSYNC VF 0b011 13 ...

Page 1257: ...ace Information Capture To store all information generated on the pins during program trace 5 bits per clock 30 bits per show cycle a large memory buffer is required However because this information includes events that were canceled some of this information can be discarded External hardware can be added to eliminate all canceled instructions and report only on taken not taken branches indirect f...

Page 1258: ...rable to enable breakpoints when MSR RI is clear despite the risk of a nonrestartable machine state Internal breakpoints also have a programmable nonmasked mode and an external development system can choose to assert a nonmaskable external breakpoint Watchpoints are not masked and are always reported on external pins regardless of the value of MSR RI Although they count watchpoints counters are pa...

Page 1259: ...rformed in case of recovery On the fly trap enable programming of the different internal breakpoints using the development port serial interface see Section 53 3 2 Development Port Communication Software control is also available Watchpoints do not change the timing of the machine Internal breakpoints and watchpoints are detected on the instruction during fetch Internal breakpoints and watchpoints...

Page 1260: ...point can generate an instruction breakpoint Two different events can decrement one counter When a counter on an instruction watchpoint expires the instruction breakpoint is asserted Instruction watchpoints and load store match events on address data enter the load store AND OR logic where load store watchpoints and breakpoints are generated Load store watchpoints when asserted can generate the lo...

Page 1261: ...own in Figure 53 3 each comparator generates two output signals equal and less than These signals generate one of four events from each comparator equal not equal greater than or less than See Section 53 2 4 2 Byte and Half Word Working Modes Table 53 6 Instruction Watchpoints Programming Options Name Description Programming Options IW0 First instruction watchpoint Comparator A Comparators A B IW1...

Page 1262: ...ding on the compare type programmed Therefore from the two 32 bit comparators eight match indications are generated Gmatch 0 3 and Hmatch 0 3 According to the lower bits of the address and the size of the cycle only match indications detected on bytes with valid information are validated The rest are negated If the executed cycle has a smaller size than the compare size a byte access when the comp...

Page 1263: ... the breakpoint exception routine As a side effect of this behavior the value of the counter inside the breakpoint exception routine equals one and not zero as one might expect When programmed to count load store watchpoints the last instruction that decrements the counter to zero is treated like any other load store breakpoint in that it executes before the machine branches to the breakpoint exce...

Page 1264: ...single instruction Watchpoint events are reported when the instruction that caused the event retires because more than one instruction can retire in a single clock ensuing events may be reported in the same clock Moreover an event detected on more than one instruction tight loops or range detection can only be reported once Internal counters count correctly in these cases 53 2 4 2 Byte and Half Wo...

Page 1265: ... L data comparator 0x9C409C40 and program for less than Both byte masks 0x0 Both L data comparators program to half word mode Result The event will be correctly detected as long as the compiler does not use a load store instruction with data size of byte Example 3 Looking for Data size Half word Address Greater than or equal to 0x00000002 and less than 0x0000000E Data value Greater than 0x4E204E20...

Page 1266: ...nd L breakpoints See Section 53 5 1 5 Load Store Support AND OR Control Register LCTRL2 53 2 4 4 Ignore First Match The ignore first match bit ICTRL IFM facilitates the debugger s continue and go from x utilities for instruction breakpoints When an instruction breakpoint is first enabled the first instruction cannot cause an instruction breakpoint if ICTRL IFM 1 This is used for continue utilities...

Page 1267: ...RL2 LWxLD Enable the address or data event in LCTRL2 LWxLADC or LCTRL2 LWxLDDC 5 Disable instruction events affecting load store watchpoints Clear LWxIADC LWxIA is a don t care 6 Enable the watchpoint in LCTRL2 LWxEN 7 Enable a trap on every watchpoint or every N watchpoints Option Enable trap on every load store watchpoint in LCTRL2 SLWxEN or on every N watchpoints in COUNTx Set CNTV to n and sel...

Page 1268: ...ents These events can be any interrupt or exception in the core system including the internal breakpoints in combination with two levels of development port requests generated externally Each of these can be programmed to be treated as a regular interrupt that causes the machine to branch to its interrupt vector or as a special interrupt that causes debug mode entry In debug mode the rfi instructi...

Page 1269: ...used to assert and negate VSYNC operation In debug mode the development port also controls the debug mode features of the core See Section 53 3 2 Development Port Communication 53 3 1 Debug Mode Operation Figure 53 6 shows the debug mode logic implemented in the core Figure 53 6 Debug Mode Logic Diagram The debug mode of the core provides the development system with the following functions Control...

Page 1270: ...mode access to a nonexisting memory space Caches and MMUs are frozen in debug mode All accesses made during debug mode will be to the memory Cache contents can only be accessed via SPRs 53 3 1 1 Debug Mode Enable vs Debug Mode Disable For protection purposes there are two working modes debug mode enable and debug mode disable which are selected once at reset Debug mode is enabled by asserting DSCK...

Page 1271: ...hout SRESET assertion and then past SRESET negation the processor takes a breakpoint exception and goes directly to debug mode instead of fetching the reset vector To avoid entering debug mode after reset DSCK must be negated no later than seven clock cycles after SRESET negates allowing the processor to jump to the reset vector and begin normal execution If debug mode is entered immediately after...

Page 1272: ...structions from the development port Chapter 6 Exceptions gives the exact SRR0 and SRR1 values If the core is in debug mode the freeze indication is asserted causing any properly programmed peripheral to stop The development port should read the value of the ICR to get the cause of the debug mode entry Reading the ICR clears all of its bits 53 3 1 3 Debug Mode Indication The fact that the core is ...

Page 1273: ...recognized in debug mode Hardware does not generate breakpoints and watchpoints in debug mode regardless of the value of MSR RI On entering debug mode MSR EE is cleared forcing hardware to ignore external and decrementer interrupts Note that debug software must not set MSR EE in debug mode because the external interrupt event is a level signal Because the core only reports and does not handle exce...

Page 1274: ...he development port shift register At the same time the new msb of the shift register is presented at the DSDO pin The clock may be implemented as a free running or gated clock As discussed in Section 53 3 2 4 Development Port Serial Communications Trap Enable Mode and Section 53 3 2 5 Development Port Serial Communications Debug Mode data shifting is controlled by the ready and start signals so t...

Page 1275: ...ster from the DSDI DSCK or CLKOUT is the shift clock depending on the debug port clock mode See Section 53 3 2 3 Development Port Serial Communications Clock Mode The instructions or data are then transferred in parallel to the core and TECR When the processor enters debug mode it fetches instructions from DPIR that cause an access to the development port shift register These instructions are seri...

Page 1276: ...sults do not match for example if an instruction is received when data is expected 53 3 2 3 Development Port Serial Communications Clock Mode All development port serial transmissions are synchronous communications The development port supports two ways to clock serial transmissions 53 3 2 3 1 Asynchronous Clocked Mode Using DSCK The first clock mode is called asynchronous clocked since the input ...

Page 1277: ...k Mode The selection of clocked or self clocked mode is made at reset The state of the DSDI input is latched eight clocks after negation of SRESET If it is latched low asynchronous clocked mode is enabled If it is latched high then synchronous self clocked mode is enabled The timing diagram in Figure 53 11 shows the clock mode selection after reset CLKOUT Debug port drives the ready bit onto DSDO ...

Page 1278: ...evelopment tool to the development port is signaled by a start bit A mode bit in the transmission defines it as either a trap enable mode transmission or a debug mode transmission If the mode bit is set the transmission will be 10 bits long and only seven data bits will be shifted into the shift register These seven bits will be latched into the TECR A control bit determines whether the data is la...

Page 1279: ...rt In trap enable mode there is no data from the core out of the development port Data out of the development port in the trap enable mode is shown in Table 53 12 Table 53 10 Trap Enable Data Shifted into Development Port Shift Register Start Mode Control 1st 2nd 3rd 4th 1st 2nd VSYNC Function Instruction Data Watchpoint Trap Enables 1 1 0 0 Disabled 1 Enabled Transfer data to trap enable control ...

Page 1280: ...ifted out the ready bit is not set Instead the port waits for the core to read the next instruction before asserting ready This allows duplex operation of the serial port and lets the port control all transmissions from the external development tool After detecting this ready status the external development tool begins transmitting to the development port with a start bit logic high on DSDI 53 3 2...

Page 1281: ... valid data encoding has the highest priority of all status outputs and is reported even if an interrupt occurs at the same time Because a sequencing error cannot occur when data is valid there is no priority conflict with the sequencing error status Also an interrupt recognized when there is valid data is not related to the execution of an instruction therefore a valid data status is output and t...

Page 1282: ...e system memory by repeating the sequence of transactions shown in Figure 53 12 from the development tool to the debug port for the number of data words to be downloaded Figure 53 12 Download Procedure Code Example In this example RX r31 and RY r30 The sequence is repeated until the end download procedure command is issued to the debug port GPR31 temporarily stores the data value Before issuing th...

Page 1283: ...s broadcast externally over FRZ As shown in Figure 53 6 the ICR and DER control assertion and negation of the freeze signal when debug mode is disabled To assert the freeze signal software must program the relevant DER bits but to negate the freeze line the software must read the ICR to clear it and execute an rfi If the ICR is not cleared before the rfi is executed the freeze signal is not negate...

Page 1284: ...00 10111 COUNTB Fetch sync on write 152 00100 11000 CMPE Write Fetch sync Read Sync relative to load store operations 153 00100 11001 CMPF Write Fetch sync Read Sync relative to load store operations 154 00100 11010 CMPG Write Fetch sync Read Sync relative to load store operations 155 00100 11011 CMPH Write Fetch sync Read Sync relative to load store operations 156 00100 11100 LCTRL1 Write Fetch s...

Page 1285: ...t Read register 0 0 X Read is performed When reading ICR it is also cleared 0 1 0 Read is performed When reading ICR it is not cleared 0 1 1 Read is performed When reading ICR it is also cleared 1 X X Read is not performed program interrupt is generated When reading ICR it is not cleared Write register 0 0 X Write is performed Write to ICR or DPDR is ignored the register is not modified and no int...

Page 1286: ...AR shown in Figure 53 17 is used to hold the address of the load store cycle that generated a breakpoint 0 31 Field CMPV Reset Undefined R W R W SPR 152 CMPE 153 CMPF Figure 53 15 Comparator E F Value Registers CMPE CMPF Table 53 17 CMPE CMPF Field Descriptions Bits Name Description 0 31 CMPV Address bits to be compared 0 31 Field CMPV Reset Undefined R W R W SPR 154 CMPG 155 CMPH Figure 53 16 Com...

Page 1287: ...N DIW3EN IFM ISCT_SER Reset 0000_0000_0000_0000 R W R W SPR 158 Figure 53 18 Instruction Support Control Register ICTRL Table 53 20 ICTRL Field Descriptions Bits Name Description 0 2 CTA Compare type of comparator A D 0xx Not active reset value 100 Equal 101 Less than 110 Greater than 111 Not equal 3 5 CTB 6 8 CTC 9 11 CTD 12 13 IW0 Instruction first watchpoint programming 0x Not active reset valu...

Page 1288: ...ction after the mtspr ICTRL 000 Core is fully serialized show cycle is performed for all fetched instructions reset value 001 Core is fully serialized show cycle is performed for all changes in program flow 010 Core is fully serialized show cycle is performed for all indirect changes in program flow 011 Core is fully serialized no show cycles is performed for fetched instructions 100 Illegal 101 C...

Page 1289: ... Name Description 0 2 CTE Compare type comparators E H 0xxNot active reset value 100 Equal 101 Less than 110 Greater than 111 Not equal 3 5 CTF 6 8 CTG 9 11 CTH 12 13 CRWE Select match on read write of comparators E and F 0x Don t care reset value 10 Match on read 11 Match on write 14 15 CRWF 16 17 CSG Compare size comparator G and H 00 Reserved 01 Word 10 Half word 11 Byte 18 19 CSH 20 SUSG Signe...

Page 1290: ...ore watchpoint enable bit 0 Watchpoint not enabled reset value 1 Watchpoint enabled 1 2 LW0IA First load store watchpoint instruction watchpoint selection 00 First instruction watchpoint 01 Second Instruction watchpoint 10 Third instruction watchpoint 11 Fourth Instruction watchpoint 3 LW0IADC First load store watchpoint care don t care instruction events 0 Don t care 1 Care 4 5 LW0LA First load s...

Page 1291: ... t care load store address events 0 Don t care 1 Care 17 18 LW1LD Second load store watchpoint load store data events selection 00 Match from comparator G 01 Match from comparator H 10 Match from comparators G H 11 Match from comparator G H 19 LW1LDDC Second load store watchpoint care don t care load store data events 0 Don t care 1 Care 20 BRKNOMSK Internal breakpoints nonmask bit controls both i...

Page 1292: ...ICR The ICR indicates the reason that debug mode was entered ICR bits are set by the hardware and cleared when the register is read Attempts to write to ICR are ignored All bits are cleared when exiting reset Bit 0 15 Field CNTCV Reset Undefined R W R W Bit 16 29 30 31 Field CNTC Reset 0000_0000_0000_0000 R W R W SPR 150 COUNTA 151 COUNTB Figure 53 21 Breakpoint Counter Value and Control Registers...

Page 1293: ...xternal interrupt bit Set when the external interrupt is asserted Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set 7 ALI Alignment interrupt bit Set when the alignment interrupt is asserted Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set 8 PRI Program interrupt bit Set when the program interrupt is asserted Causes deb...

Page 1294: ...corresponding enable bit is set 22 27 Reserved 28 LBRK Load store breakpoint interrupt bit Set as a result of the assertion of an load store breakpoint Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set 29 IBRK Instruction breakpoint interrupt bit Set as a result of the assertion of an instruction breakpoint Causes debug mode entry if debug mode is enabled and...

Page 1295: ...navailable interrupt enable bit 10 DECIE Decrementer interrupt enable bit 11 12 Reserved 13 SYSIE System call interrupt enable bit 14 TRE Trace interrupt enable bit 0 Debug mode entry is disabled 1 Debug mode entry is enabled reset value 15 16 Reserved 17 SEIE Software emulation interrupt enable bit 0 Debug mode entry is disabled reset value 1 Debug mode entry is enabled 18 ITLBMSE Implementation ...

Page 1296: ...egister DPDR The 32 bit development port data register DPDR SPR 630 resides in the development port logic It is used for data interchange between the core and the development system The DPDR is accessed by using mtspr and mfspr and implemented using a special bus cycle on the internal bus See Section 53 3 2 2 1 Development Port Shift Register ...

Page 1297: ...board electrical continuity Bypass the MPC885 for a given circuit board test by effectively reducing the boundary scan register to a single cell Sample the MPC885 system signals during operation and transparently shift out the result in the boundary scan register Disable the output drive to signals during circuit board testing 54 1 Overview The MPC885 TAP implementation includes a TAP controller a...

Page 1298: ...erpreting the sequence of logical values on the TMS signal It is a synchronous state machine that controls the operation of the JTAG logic The value shown adjacent to each bubble represents the value of the TMS signal sampled on the rising edge of TCK Figure 54 2 shows the MPC885 TAP controller state machine Boundary Scan Register Bypass M U X Instruction Apply Decode Register 4 Bit Instruction Re...

Page 1299: ...ed on the MPC885 This 475 bit boundary scan register can be connected between TDI and TDO when EXTEST or SAMPLE PRELOAD instructions are selected The boundary scan register is used for capturing data on the input signals forcing fixed values on the output signals and selecting the direction and drive characteristics a logic value or high impedance of the bidirectional and three state signals TEST ...

Page 1300: ... logic configuration for an observe only input signal boundary scan cell Figure 54 4 Observe Only Input Signal Boundary Scan Cell Input Cell Figure 54 5 shows the logic configuration for an output control boundary scan cell 1 1 MUX G1 1 1 MUX G1 C D C D From Last Cell Clock Dr Update Dr Shift Dr 1 Extest Clamp Data From To Output Buffer 0 Otherwise Logic System To Next Cell 1 1 MUX G1 C D From Las...

Page 1301: ...ated with them The bit order of the boundary scan chain described in the MPC885 BSDL file starts with the TDO output and ends with the TDI input The shift register cell nearest TDO first to be shifted in is defined as bit 1 and the last bit to be shifted in is bit 475 54 4 Instruction Register The MPC885 TAP implementation includes the public instructions EXTEST SAMPLE PRELOAD BYPASS and CLAMP An ...

Page 1302: ...lls before the boundary scan register is enabled by the EXTEST command This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction If the SAMPLE PRELOAD command was not issued prior to the EXTEST command the output signals will go to a random state when the boundary scan register is enabled and takes control of the output buffer The SAMPLE PRELOAD co...

Page 1303: ... circuit board testing When the HI Z instruction is invoked all output drivers including the two state drivers are placed in a high impedance state The HI Z instruction also selects the bypass register 54 5 TAP Usage Considerations The control afforded by the output enable signals using the boundary scan register and the EXTEST instruction requires a compatible circuit board test environment to av...

Page 1304: ...does not have an on chip pull up or pull down resistor it should be pulled down through a resistor To use the TAP to perform test operations select the TAP functions in the hard reset configuration word for the signals TCK DSCK TDI DSDI TDO DSDO 54 7 MPC885 BSDL Description The most current revision of the BSDL file for the MPC885 PowerQUICC is available at the Freescale web site ...

Page 1305: ... the scalar comes first in memory For modified little endian byte ordering also referred to as munged little endian the address of data is modified so that the memory structure appears little endian to the executing processor when in fact the byte ordering is big endian The address modification is called munging Note that the term munging is not defined or used in the PowerPC architecture specific...

Page 1306: ...t as set for the interrupted process is copied into MSR LE to select the endian mode for the context established by the exception For both bits a value of 0 specifies BE mode or TLE mode depending on DC_CST LES and a value of 1 specifies PPC LE mode A 4 TLE Mode When operating in TLE mode the external bus uses little endian byte ordering so any external agents should use little endian byte orderin...

Page 1307: ...ernal registers with apparent little endian byte ordering However when DC_CST LES is set for any access originating from the MPC8xx core the SIU unmunges the address and swaps the bytes of data within each word at the external bus U bus boundary The byte swapping is shown in Figure A 2 Figure A 2 Byte Swapping The unmunging and byte swapping places all external accesses by the MPC8xx core into tru...

Page 1308: ...B 0 1 2 3 0 1 2 3 3 2 1 0 Word 0 0 0 11 12 13 14 11 12 13 14 14 13 12 11 11 12 13 14 Half word 0 2 0 21 22 21 22 22 21 21 22 Half word 2 0 2 31 32 31 32 32 31 31 32 Byte 0 3 0 a a a a Byte 1 2 1 b b b b Byte 2 1 2 c c c c Byte 3 0 3 d d d d Table A 4 Little Endian Program Data Path Between the Register and 16 Bit Memory Fetch Load Store Type Little Endian Addr U bus and Cache Addr External Bus Add...

Page 1309: ...ittle Endian Program Data Path between the Register and 8 Bit Memory Fetch Load Store Type Little Endian Addr U bus and Cache Addr External Bus Addr Data in the Register U bus and Cache Format External Bus Format Little Endian Program Data MSB LSB 0 1 2 3 0 1 2 3 3 2 1 0 Word 0 0 0 11 12 13 14 11 12 13 14 14 14 1 13 13 2 12 12 3 11 11 Half word 0 2 0 21 22 21 22 22 22 1 21 21 Half word 2 0 2 31 32...

Page 1310: ...in big endian order that is MSB at the lowest address LSB at the highest address In PPC LE mode only the address is modified not the byte order Munging makes it appear to the core that individual aligned scalars are stored in little endian order when in fact they are stored in big endian order but at different byte addresses within double words Note that the instruction and data caches operate les...

Page 1311: ...r store that maps to a control register on an external device may require the bytes of the register data to be reversed If this reversal is required the load and store with byte reverse instructions lhbrx lwbrx sthbrx and stwbrx may be used A 6 Setting the Endian Mode Of Operation As shown in Table A 1 the MPC885 powers up in BE mode The endian mode should be set early in the initialization routin...

Page 1312: ...Byte Ordering MPC885 PowerQUICC Family Reference Manual Rev 2 A 8 Freescale Semiconductor ...

Page 1313: ...MPC885 PowerQUICC Family Reference Manual Rev 2 Freescale Semiconductor B 1 Appendix B Serial Communications Performance TBD ...

Page 1314: ...Serial Communications Performance MPC885 PowerQUICC Family Reference Manual Rev 2 B 2 Freescale Semiconductor ...

Page 1315: ...l Registers Description Name Comments Access Level Serialize Access General purpose registers GPRs The thirty two 32 bit GPRs are used for source and destination operands User Condition register CR See Section 4 1 1 1 1 Condition Register CR User Only mtcrf Table C 2 User Level SPRs SPR Number Name Comments Serialize Access Decimal SPR 5 9 SPR 0 4 1 00000 00001 XER See Section 4 1 1 1 3 XER Write ...

Page 1316: ...DSISR See the Programming Environments Manual and Section 4 1 2 1 DAR DSISR and BAR Operation Write Full sync Read Sync relative to load store operations 19 00000 10011 DAR See the Programming Environments Manual and Section 4 1 2 1 DAR DSISR and BAR Operation Write Full sync Read Sync relative to load store operations 22 00000 10110 DEC See Section 10 8 1 Decrementer Register DEC and Chapter 14 C...

Page 1317: ...store 569 10001 11001 DC_ADR Section 7 3 2 Data Cache Control Registers Write as a store 570 10001 11010 DC_DAT Section 7 3 2 Data Cache Control Registers Write as a store 784 11000 10000 MI_CTR Section 8 8 1 IMMU Control Register MI_CTR Write as a store 786 11000 10010 MI_AP Section 8 8 10 MMU Access Protection Registers MI_AP MD_AP Write as a store 787 11000 10011 MI_EPN Section 8 8 3 IMMU DMMU ...

Page 1318: ...a store 799 11000 11111 M_TW M_SAVE Section 8 8 11 MMU Tablewalk Special Register M_TW Write as a store 824 11001 11000 MD_CAM Section 8 8 12 4 DMMU CAM Entry Read Register MD_CAM Write as a store 825 11001 11001 MD_RAM0 Section 8 8 12 5 DMMU RAM Entry Read Register 0 MD_RAM0 Write as a store 826 11001 11010 MD_RAM1 Section 8 8 13 DMMU RAM Entry Read Register 1 MD_RAM1 Write as a store 1 Fetch onl...

Page 1319: ...100 11011 CMPH Write Fetch sync Read Sync relative to load store operations 156 00100 11100 LCTRL1 Write Fetch sync Read Sync relative to load store operations 157 00100 11101 LCTRL2 Write Fetch sync Read Sync relative to load store operations 158 00100 11110 ICTRL Fetch sync on write 159 00100 11111 BAR Write Fetch sync Read Sync relative to load store operations See Section 4 1 2 1 DAR DSISR and...

Page 1320: ...Register Quick Reference Guide MPC885 PowerQUICC Family Reference Manual Rev 2 C 6 Freescale Semiconductor ...

Page 1321: ...rcase For more information refer to Chapter 8 Instruction Set in The Programming Environments Manual The following key applies to the tables in this appendix D 1 Instructions Sorted by Mnemonic Table D 1 lists the instructions implemented in the MPC885 s in alphabetical order by mnemonic Table D 1 Complete Instruction List Sorted by Mnemonic Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23...

Page 1322: ... crbB 449 0 crorc 19 crbD crbA crbB 417 0 crxor 19 crbD crbA crbB 193 0 dcbf 31 0 0 0 0 0 A B 86 0 dcbi 1 31 0 0 0 0 0 A B 470 0 dcbst 31 0 0 0 0 0 A B 54 0 dcbt 31 0 0 0 0 0 A B 278 0 dcbtst 31 0 0 0 0 0 A B 246 0 dcbz 31 0 0 0 0 0 A B 1014 0 divdx 4 31 D A B OE 489 Rc divdux 4 31 D A B OE 457 Rc divwx 31 D A B OE 491 Rc divwux 31 D A B OE 459 Rc eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 eieio 31...

Page 1323: ... 0 0 0 0 0 B 72 Rc fmsubx6 63 D A B C 28 Rc fmsubsx6 59 D A B C 28 Rc fmulx6 63 D A 0 0 0 0 0 C 25 Rc fmulsx6 59 D A 0 0 0 0 0 C 25 Rc fnabsx6 63 D 0 0 0 0 0 B 136 Rc fnegx6 63 D 0 0 0 0 0 B 40 Rc fnmaddx 6 63 D A B C 31 Rc fnmaddsx6 59 D A B C 31 Rc fnmsubx6 63 D A B C 30 Rc fnmsubsx6 59 D A B C 30 Rc fresx 5 6 59 D 0 0 0 0 0 B 0 0 0 0 0 24 Rc frspx6 63 D 0 0 0 0 0 B 12 Rc frsqrtex 5 6 63 D 0 0 0...

Page 1324: ...d6 50 D A d lfdu6 51 D A d lfdux6 31 D A B 631 0 lfdx6 31 D A B 599 0 lfs6 48 D A d lfsu6 49 D A d lfsux6 31 D A B 567 0 lfsx6 31 D A B 535 0 lha 42 D A d lhau 43 D A d lhaux 31 D A B 375 0 lhax 31 D A B 343 0 lhbrx 31 D A B 790 0 lhz 40 D A d lhzu 41 D A d lhzux 31 D A B 311 0 lhzx 31 D A B 279 0 lmw 3 46 D A d lswi 3 31 D A NB 597 0 lswx 3 31 D A B 533 0 lwa 4 58 D A ds 2 lwarx 31 D A B 20 0 Tab...

Page 1325: ...31 D 0 SR 0 0 0 0 0 595 0 mfsrin 1 31 D 0 0 0 0 0 B 659 0 mftb 31 D tbr 371 0 mtcrf 31 S 0 CRM 0 144 0 mtfsb0x6 63 crbD 0 0 0 0 0 0 0 0 0 0 70 Rc mtfsb1x 6 63 crbD 0 0 0 0 0 0 0 0 0 0 38 Rc mtfsfx6 63 0 FM 0 B 711 Rc mtfsfix6 63 crfD 0 0 0 0 0 0 0 IMM 0 134 Rc mtmsr 1 31 S 0 0 0 0 0 0 0 0 0 0 146 0 mtspr 2 31 S spr 467 0 mtsr 1 31 S 0 SR 0 0 0 0 0 210 0 mtsrin 1 31 S 0 0 0 0 0 B 242 0 mulhdx 4 31 ...

Page 1326: ... mb 3 sh Rc rlwimix 20 S A SH MB ME Rc rlwinmx 21 S A SH MB ME Rc rlwnmx 23 S A B MB ME Rc sc 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 slbia 1 4 5 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 498 0 slbie 1 4 5 31 0 0 0 0 0 0 0 0 0 0 B 434 0 sldx 4 31 S A B 27 Rc slwx 31 S A B 24 Rc sradx 4 31 S A B 794 Rc sradix 4 31 S A sh 413 sh Rc srawx 31 S A B 792 Rc srawix 31 S A SH 824 Rc srdx 4 31 S A B ...

Page 1327: ...S A d sthbrx 31 S A B 918 0 sthu 45 S A d sthux 31 S A B 439 0 sthx 31 S A B 407 0 stmw 3 47 S A d stswi 3 31 S A NB 725 0 stswx 3 31 S A B 661 0 stw 36 S A d stwbrx 31 S A B 662 0 stwcx 31 S A B 150 1 stwu 37 S A d stwux 31 S A B 183 0 stwx 31 S A B 151 0 subfx 31 D A B OE 40 Rc subfcx 31 D A B OE 8 Rc subfex 31 D A B OE 136 Rc subfic 08 D A SIMM subfmex 31 D A 0 0 0 0 0 OE 232 Rc subfzex 31 D A ...

Page 1328: ... 0 0 0 0 0 0 0 0 0 566 0 tw 31 TO A B 4 0 twi 03 TO A SIMM xorx 31 S A B 316 Rc xori 26 S A UIMM xoris 27 S A UIMM 1 Supervisor level instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 64 bit instruction 5 Optional in the PowerPC architecture 6 Floating point instructions are not supported by the MPC885 Table D 1 Complete Instruction List Sorted b...

Page 1329: ... 0 1 0 0 1 0 LI AA LK mcrf 0 1 0 0 1 1 crfD 0 0 crfS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bclrx 0 1 0 0 1 1 BO BI 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 LK crnor 0 1 0 0 1 1 crbD crbA crbB 0 0 0 0 1 0 0 0 0 1 0 rfi 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 crandc 0 1 0 0 1 1 crbD crbA crbB 0 0 1 0 0 0 0 0 0 1 0 isync 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 crxor...

Page 1330: ...0 1 0 1 1 Rc mfcr 0 1 1 1 1 1 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 lwarx 0 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 0 0 0 ldx 4 0 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 0 1 0 lwzx 0 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 1 1 0 slwx 0 1 1 1 1 1 S A B 0 0 0 0 0 1 1 0 0 0 Rc cntlzwx 0 1 1 1 1 1 S A 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 Rc sldx 4 0 1 1 1 1 1 S A B 0 0 0 0 0 1 1 0 1 1 Rc andx 0 1 1 1 1 1 S A B 0 0 0 0 0 1 1 1...

Page 1331: ... 1 S A B 0 0 1 0 0 1 0 1 1 1 0 stdux 4 0 1 1 1 1 1 S A B 0 0 1 0 1 1 0 1 0 1 0 stwux 0 1 1 1 1 1 S A B 0 0 1 0 1 1 0 1 1 1 0 subfzex 0 1 1 1 1 1 D A 0 0 0 0 0 OE 0 1 1 0 0 1 0 0 0 Rc addzex 0 1 1 1 1 1 D A 0 0 0 0 0 OE 0 1 1 0 0 1 0 1 0 Rc mtsr 0 1 1 1 1 1 S 0 SR 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 stdcx 4 0 1 1 1 1 1 S A B 0 0 1 1 0 1 0 1 1 0 1 stbx 0 1 1 1 1 1 S A B 0 0 1 1 0 1 0 1 1 1 0 subfmex 0 1...

Page 1332: ... 0 0 0 0 0 0 0 0 0 0 B 0 1 1 0 1 1 0 0 1 0 0 ecowx 0 1 1 1 1 1 S A B 0 1 1 0 1 1 0 1 1 0 0 sthux 0 1 1 1 1 1 S A B 0 1 1 0 1 1 0 1 1 1 0 orx 0 1 1 1 1 1 S A B 0 1 1 0 1 1 1 1 0 0 Rc divdux 4 0 1 1 1 1 1 D A B OE 1 1 1 0 0 1 0 0 1 Rc divwux 0 1 1 1 1 1 D A B OE 1 1 1 0 0 1 0 1 1 Rc mtspr 2 0 1 1 1 1 1 S spr 0 1 1 1 0 1 0 0 1 1 0 dcbi 0 1 1 1 1 1 0 0 0 0 0 A B 0 1 1 1 0 1 0 1 1 0 0 nandx 0 1 1 1 1 1...

Page 1333: ... B 1 0 1 1 0 1 0 1 1 1 0 stfdux6 0 1 1 1 1 1 S A B 1 0 1 1 1 1 0 1 1 1 0 lhbrx 0 1 1 1 1 1 D A B 1 1 0 0 0 1 0 1 1 0 0 srawx 0 1 1 1 1 1 S A B 1 1 0 0 0 1 1 0 0 0 Rc sradx 4 0 1 1 1 1 1 S A B 1 1 0 0 0 1 1 0 1 0 Rc srawix 0 1 1 1 1 1 S A SH 1 1 0 0 1 1 1 0 0 0 Rc eieio 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 sthbrx 0 1 1 1 1 1 S A B 1 1 1 0 0 1 0 1 1 0 0 extshx 0 1 1 1 1 1 ...

Page 1334: ...1 0 1 0 D A ds 0 1 lwa 4 1 1 1 0 1 0 D A ds 1 0 fdivsx6 1 1 1 0 1 1 D A B 0 0 0 0 0 1 0 0 1 0 Rc fsubsx6 1 1 1 0 1 1 D A B 0 0 0 0 0 1 0 1 0 0 Rc faddsx6 1 1 1 0 1 1 D A B 0 0 0 0 0 1 0 1 0 1 Rc fsqrtsx 5 6 1 1 1 0 1 1 D 0 0 0 0 0 B 0 0 0 0 0 1 0 1 1 0 Rc fresx 5 6 1 1 1 0 1 1 D 0 0 0 0 0 B 0 0 0 0 0 1 1 0 0 0 Rc fmulsx6 1 1 1 0 1 1 D A 0 0 0 0 0 C 1 1 0 0 1 Rc fmsubsx6 1 1 1 0 1 1 D A B C 1 1 1 0...

Page 1335: ... 0 0 1 0 0 1 1 0 Rc fnegx6 1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 0 1 0 1 0 0 0 Rc mcrfs6 1 1 1 1 1 1 crfD 0 0 crfS 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 mtfsb0x6 1 1 1 1 1 1 crbD 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 Rc fmrx6 1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 1 0 0 1 0 0 0 Rc mtfsfix6 1 1 1 1 1 1 crfD 0 0 0 0 0 0 0 IMM 0 0 0 1 0 0 0 0 1 1 0 Rc fnabsx6 1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 1 0 0 0 1 0 0 0 Rc fabsx...

Page 1336: ...MPC885 PowerQUICC Family Reference Manual Rev 2 D 16 Freescale Semiconductor ...

Page 1337: ... 138 Rc addi 14 D A SIMM addic 12 D A SIMM addic 13 D A SIMM addis 15 D A SIMM addmex 31 D A 0 0 0 0 0 OE 234 Rc addzex 31 D A 0 0 0 0 0 OE 202 Rc divdx 4 31 D A B OE 489 Rc divdux 4 31 D A B OE 457 Rc divwx 31 D A B OE 491 Rc divwux 31 D A B OE 459 Rc mulhdx 4 31 D A B 0 73 Rc mulhdux 4 31 D A B 0 9 Rc mulhwx 31 D A B 0 75 Rc mulhwux 31 D A B 0 11 Rc mulld 4 31 D A B OE 233 Rc mulli 07 D A SIMM m...

Page 1338: ... B 28 Rc andcx 31 S A B 60 Rc andi 28 S A UIMM andis 29 S A UIMM cntlzdx 4 31 S A 0 0 0 0 0 58 Rc cntlzwx 31 S A 0 0 0 0 0 26 Rc eqvx 31 S A B 284 Rc extsbx 31 S A 0 0 0 0 0 954 Rc extshx 31 S A 0 0 0 0 0 922 Rc extswx 4 31 S A 0 0 0 0 0 986 Rc nandx 31 S A B 476 Rc norx 31 S A B 124 Rc orx 31 S A B 444 Rc orcx 31 S A B 412 Rc ori 24 S A UIMM oris 25 S A UIMM xorx 31 S A B 316 Rc xori 26 S A UIMM ...

Page 1339: ...4 Rc srdx 4 31 S A B 539 Rc srwx 31 S A B 536 Rc Table D 8 Floating Point Arithmetic Instructions 6 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 faddx 63 D A B 0 0 0 0 0 21 Rc faddsx 59 D A B 0 0 0 0 0 21 Rc fdivx 63 D A B 0 0 0 0 0 18 Rc fdivsx 59 D A B 0 0 0 0 0 18 Rc fmulx 63 D A 0 0 0 0 0 C 25 Rc fmulsx 59 D A 0 0 0 0 0 C 25 Rc fresx 5 59 D 0 0 0 0 0 B 0 0...

Page 1340: ...31 fcfidx 4 63 D 0 0 0 0 0 B 846 Rc fctidx 4 63 D 0 0 0 0 0 B 814 Rc fctidzx 4 63 D 0 0 0 0 0 B 815 Rc fctiwx 63 D 0 0 0 0 0 B 14 Rc fctiwzx 63 D 0 0 0 0 0 B 15 Rc frspx 63 D 0 0 0 0 0 B 12 Rc Table D 11 Floating Point Compare Instructions 6 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fcmpo 63 crfD 0 0 A B 32 0 fcmpu 63 crfD 0 0 A B 0 0 Table D 12 Floating Po...

Page 1341: ...31 D A B 21 0 lha 42 D A d lhau 43 D A d lhaux 31 D A B 375 0 lhax 31 D A B 343 0 lhz 40 D A d lhzu 41 D A d lhzux 31 D A B 311 0 lhzx 31 D A B 279 0 lwa 4 58 D A ds 2 lwaux 4 31 D A B 373 0 lwax 4 31 D A B 341 0 lwz 32 D A d lwzu 33 D A d lwzux 31 D A B 55 0 lwzx 31 D A B 23 0 Table D 14 Integer Store Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ...

Page 1342: ...Load and Store Multiple Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lmw 3 46 D A d stmw 3 47 S A d Table D 17 Integer Load and Store String Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lswi 3 31 D A NB 597 0 lswx 3 31 D A B 533 0 stswi 3 31 S A NB 725 0 stswx 3 31 S A B 661 0 Table D 18 Memory Sy...

Page 1343: ...31 D A B 535 0 Table D 20 Floating Point Store Instructions 6 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 stfd 54 S A d stfdu 55 S A d stfdux 31 S A B 759 0 stfdx 31 S A B 727 0 stfiwx 5 31 S A B 983 0 stfs 52 S A d stfsu 53 S A d stfsux 31 S A B 695 0 stfsx 31 S A B 663 0 Table D 21 Floating Point Move Instructions 6 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 ...

Page 1344: ...rbB 33 0 cror 19 crbD crbA crbB 449 0 crorc 19 crbD crbA crbB 417 0 crxor 19 crbD crbA crbB 193 0 mcrf 19 crfD 0 0 crfS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table D 24 System Linkage Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rfi 1 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 sc 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Table D 25 Trap In...

Page 1345: ... 0 A B 1014 0 icbi 31 0 0 0 0 0 A B 982 0 Table D 28 Segment Register Manipulation Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mfsr 1 31 D 0 SR 0 0 0 0 0 595 0 mfsrin 1 31 D 0 0 0 0 0 B 659 0 mtsr 1 31 S 0 SR 0 0 0 0 0 210 0 mtsrin 1 31 S 0 0 0 0 0 B 242 0 Table D 29 Lookaside Buffer Management Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 1...

Page 1346: ...13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 Notes 1 Supervisor level instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 64 bit instruction 5 Optional in the PowerPC architecture 6 Floating point instructions are not supported by the MPC885 ...

Page 1347: ...c Instruction Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bcx 16 BO BI BD AA LK OPCD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Specific Instruction Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sc 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 OPCD D A d OPCD D A SIMM OPCD S A d OPCD S A UIMM OPCD crf...

Page 1348: ...lfdu 6 51 D A d lfs6 48 D A d lfsu6 49 D A d lha 42 D A d lhau 43 D A d lhz 40 D A d lhzu 41 D A d lmw 3 46 D A d lwz 32 D A d lwzu 33 D A d mulli 7 D A SIMM ori 24 S A UIMM oris 25 S A UIMM stb 38 S A d stbu 39 S A d stfd6 54 S A d stfdu6 55 S A d stfs6 52 S A d stfsu6 53 S A d sth 44 S A d sthu 45 S A d stmw 3 47 S A d stw 36 S A d stwu 37 S A d subfic 08 D A SIMM tdi 4 02 TO A SIMM twi 03 TO A ...

Page 1349: ...D A ds 2 std 4 62 S A ds 0 stdu 4 62 S A ds 1 OPCD D A B XO 0 OPCD D A NB XO 0 OPCD D 0 0 0 0 0 B XO 0 OPCD D 0 0 0 0 0 0 0 0 0 0 XO 0 OPCD D 0 SR 0 0 0 0 0 XO 0 OPCD S A B XO Rc OPCD S A B XO 1 OPCD S A B XO 0 OPCD S A NB XO 0 OPCD S A 0 0 0 0 0 XO Rc OPCD S 0 0 0 0 0 B XO 0 OPCD S 0 0 0 0 0 0 0 0 0 0 XO 0 OPCD S 0 SR 0 0 0 0 0 XO 0 OPCD S A SH XO Rc OPCD crfD 0 L A B XO 0 OPCD crfD 0 0 A B XO 0 ...

Page 1350: ... cntlzdx 4 31 S A 0 0 0 0 0 58 Rc cntlzwx 31 S A 0 0 0 0 0 26 Rc dcbf 31 0 0 0 0 0 A B 86 0 dcbi 1 31 0 0 0 0 0 A B 470 0 dcbst 31 0 0 0 0 0 A B 54 0 dcbt 31 0 0 0 0 0 A B 278 0 dcbtst 31 0 0 0 0 0 A B 246 0 dcbz 31 0 0 0 0 0 A B 1014 0 eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 eieio 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 854 0 eqvx 31 S A B 284 Rc extsbx 31 S A 0 0 0 0 0 954 Rc extshx 31 S A 0 0 0 0 0 ...

Page 1351: ...1 D A B 599 0 lfsux6 31 D A B 567 0 lfsx6 31 D A B 535 0 lhaux 31 D A B 375 0 lhax 31 D A B 343 0 lhbrx 31 D A B 790 0 lhzux 31 D A B 311 0 lhzx 31 D A B 279 0 lswi 3 31 D A NB 597 0 lswx 3 31 D A B 533 0 lwarx 31 D A B 20 0 lwaux 4 31 D A B 373 0 lwax 4 31 D A B 341 0 lwbrx 31 D A B 534 0 lwzux 31 D A B 55 0 lwzx 31 D A B 23 0 mcrfs 63 crfD 0 0 crfS 0 0 0 0 0 0 0 64 0 mcrxr 31 crfD 0 0 0 0 0 0 0 ...

Page 1352: ...a 1 4 5 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 498 0 slbie 1 4 5 31 0 0 0 0 0 0 0 0 0 0 B 434 0 sldx 4 31 S A B 27 Rc slwx 31 S A B 24 Rc sradx 4 31 S A B 794 Rc srawx 31 S A B 792 Rc srawix 31 S A SH 824 Rc srdx 4 31 S A B 539 Rc srwx 31 S A B 536 Rc stbux 31 S A B 247 0 stbx 31 S A B 215 0 stdcx 4 31 S A B 214 1 stdux 4 31 S A B 181 0 stdx 4 31 S A B 149 0 stfdux6 31 S A B 759 0 stfdx6 31 S A B 727 0 ...

Page 1353: ... crbB XO 0 OPCD crfD 0 0 crfS 0 0 0 0 0 0 0 XO 0 OPCD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XO 0 Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bcctrx 19 BO BI 0 0 0 0 0 528 LK bclrx 19 BO BI 0 0 0 0 0 16 LK crand 19 crbD crbA crbB 257 0 crandc 19 crbD crbA crbB 129 0 creqv 19 crbD crbA crbB 289 0 crnand 19 crbD crbA crbB 225 0 crnor 19 crbD crbA c...

Page 1354: ... Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mtfsfx6 63 0 FM 0 B 711 Rc OPCD S A sh XO sh Rc Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sradix 4 31 S A sh 413 sh Rc OPCD D A B OE XO Rc OPCD D A B 0 XO Rc OPCD D A 0 0 0 0 0 OE XO Rc Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1...

Page 1355: ...c subfmex 31 D A 0 0 0 0 0 OE 232 Rc subfzex 31 D A 0 0 0 0 0 OE 200 Rc OPCD D A B 0 0 0 0 0 XO Rc OPCD D A B C XO Rc OPCD D A 0 0 0 0 0 C XO Rc OPCD D 0 0 0 0 0 B 0 0 0 0 0 XO Rc Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 faddx6 63 D A B 0 0 0 0 0 21 Rc faddsx6 59 D A B 0 0 0 0 0 21 Rc fdivx6 63 D A B 0 0 0 0 0 18 Rc fdivsx6 59 D A B 0...

Page 1356: ... 63 D A B 0 0 0 0 0 20 Rc fsubsx6 59 D A B 0 0 0 0 0 20 Rc OPCD S A SH MB ME Rc OPCD S A B MB ME Rc Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rlwimix 20 S A SH MB ME Rc rlwinmx 21 S A SH MB ME Rc rlwnmx 23 S A B MB ME Rc OPCD S A sh mb XO sh Rc OPCD S A sh me XO sh Rc Specific Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19...

Page 1357: ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rldclx 4 30 S A B mb 8 Rc rldcrx 4 30 S A B me 9 Rc Notes 1 Supervisor level instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 64 bit instruction 5 Optional in the PowerPC architecture 6 Floating point instructions are not supported by the MPC885 ...

Page 1358: ...MPC885 PowerQUICC Family Reference Manual Rev 2 D 38 Freescale Semiconductor ...

Page 1359: ... MPC885 such as the architectural level privilege level and form Table D 44 Instruction Set Legend UISA VEA OEA Supervisor Level 64 Bit Optional Form addx XO addcx XO addex XO addi D addic D addic D addis D addmex XO addzex XO andx X andcx X andi D andis D bx I bcx B bcctrx XL bclrx XL cmp X cmpi D cmpl X cmpli D cntlzdx 4 X cntlzwx X crand XL crandc XL creqv XL crnand XL crnor XL cror XL ...

Page 1360: ...cbz X divdx 4 XO divdux 4 XO divwx XO divwux XO eciwx X ecowx X eieio X eqvx X extsbx X extshx X extswx 4 X fabsx6 X faddx6 A faddsx6 A fcfidx 4 6 X fcmpo6 X fcmpu6 X fctidx 4 6 X fctidzx 4 6 X fctiwx6 X fctiwzx6 X fdivx6 A fdivsx6 A fmaddx6 A Table D 44 Instruction Set Legend continued UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1361: ...6 X fnegx6 X fnmaddx 6 A fnmaddsx6 A fnmsubx6 A fnmsubsx6 A fresx 5 6 A frspx6 X frsqrtex 5 6 A fselx 5 6 A fsqrtx 5 6 A fsqrtsx 5 6 A fsubx6 A fsubsx6 A icbi X isync XL lbz D lbzu D lbzux X lbzx X ld 4 DS ldarx 4 X ldu 4 DS ldux 4 X ldx 4 X lfd6 D Table D 44 Instruction Set Legend continued UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1362: ...fsu6 D lfsux6 X lfsx6 X lha D lhau D lhaux X lhax X lhbrx X lhz D lhzu D lhzux X lhzx X lmw 3 D lswi 3 X lswx 3 X lwa 4 DS lwarx X lwaux 4 X lwax 4 X lwbrx X lwz D lwzu D lwzux X lwzx X mcrf XL mcrfs6 X mcrxr X mfcr X Table D 44 Instruction Set Legend continued UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1363: ...FX mtfsb0x6 X mtfsb1x 6 X mtfsfx6 XFL mtfsfix6 X mtmsr 1 X mtspr 2 XFX mtsr 1 X mtsrin 1 X mulhdx 4 XO mulhdux 4 XO mulhwx XO mulhwux XO mulldx 4 XO mulli D mullwx XO nandx X negx XO norx X orx X orcx X ori D oris D rfi 1 XL rldclx 4 MDS rldcrx 4 MDS Table D 44 Instruction Set Legend continued UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1364: ...winmx M rlwnmx M sc SC slbia 1 4 5 X slbie 1 4 5 X sldx 4 X slwx X sradx 4 X sradix 4 XS srawx X srawix X srdx 4 X srwx X stb D stbu D stbux X stbx X std 4 DS stdcx 4 X stdu 4 DS stdux 4 X stdx 4 X stfd6 D stfdu6 D stfdux6 X stfdx6 X stfiwx 5 6 X Table D 44 Instruction Set Legend continued UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1365: ...x X sthu D sthux X sthx X stmw 3 D stswi 3 X stswx 3 X stw D stwbrx X stwcx X stwu D stwux X stwx X subfx XO subfcx XO subfex XO subfic D subfmex XO subfzex XO sync X td 4 X tdi 4 D tlbia 1 5 X tlbie 1 5 X tlbsync 1 5 X tw X twi D Table D 44 Instruction Set Legend continued UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1366: ...evel instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 64 bit instruction 5 Optional in the PowerPC architecture 6 Floating point instructions are not supported by the MPC885 Table D 44 Instruction Set Legend continued UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1367: ...entical to the MPC885 except for the following features The MPC880 contains two SCCs SCC3 and SCC4 instead of three This affects the documentation in the following ways Signals that support SCC2 are not implemented as described in Section E 2 1 Unimplemented Signals Certain bits and register resources defined for SCC2 are not implemented as described in Section E 2 3 General Set Up The MPC880 does...

Page 1368: ...O Memory Controller 4 Timers Interrupt Controllers 8 Kbyte Dual Port RAM System Functions 8 Kbyte Instruction Cache 32 Entry ITLB Instruction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Program ROM Serial Interface I2 C SP...

Page 1369: ... to SCC2 See Section 20 2 3 7 Programming the SI RAM Also ensure that the serial interface clock routing invokes proper routing as desired for SCC3 and SCC4 and that bits in the SICR pertaining to SCC2 are cleared See Section 20 2 4 3 SI Clock Route Register SICR E 2 3 General Set Up Although most SCC registers contain configuration bits for four SCCs ensure that these are only configuring SCC3 an...

Page 1370: ...MPC880 MPC885 PowerQUICC Family Reference Manual Rev 2 E 4 Freescale Semiconductor ...

Page 1371: ...and SCC3 are not implemented The time slot assigner is not implemented The MPC875 contains one SMC SMC1 instead of two Signals that support SCM2 are not implemented Certain bits and register resources defined for SMC2 are not implemented The MPC875 has a time slot assigner TSA that supports one TDM bus TDMb The MPC875 supports one PCMCIA channel The MPC875 does not include ATM support The MPC875 d...

Page 1372: ...e Unit SIU Embedded Parallel I O Memory Controller 4 Timers Interrupt Controllers 8 Kbyte Dual Port RAM System Functions 8 Kbyte Instruction Cache 32 Entry ITLB Instruction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port Internal Bus Interface Unit External Bus Interface Unit Timers 32 Bit RISC Controller and Progr...

Page 1373: ...ST3 BRGO2 RXADDR1 TXADDR1 PB17 PHREQ 0 L1ST4 L1RQA RTS4 RXADDR0 TXADDR0 PB16 RXCLAV TXCLAV TOUT2 PB15 RXADDR2 TXADDR2 PB14 CTS2 PC9 TGATE2 CD2 PC8 CTS3 SDACK2 L1TSYNCA PC5 CD3 L1RSYNCA PC4 UTPB 0 L1TSYNCA PD15 UTPB 1 L1RSYNCA PD14 UTPB 2 L1TSYNCB PD13 UTPB 3 L1RSYNCB PD12 RXENB RxD3 PD11 TXENB TxD3 PD10 UTPCLK TxD4 PD9 UTPB 4 RTS3 PD7 UTPB 5 RTS4 PD6 UTPB 6 CLK8 L1TCKB PD5 UTPB 7 CLK4 PD4 SOC CLK7...

Page 1374: ...lit7 UtpClk_Split F 2 3 SCC and SMC General Set Up Although most SCC registers contain configuration bits for three SCCs ensure that these are only configuring SCC4 Refer to Chapter 21 Serial Communications Controllers Registers affected include the GSMR PSMR DSR and TODR If interrupts are used ensure that only SCCE SCCM SCCS are manipulated or observed See Section 21 4 2 Handling SCC Interrupts w...

Page 1375: ... instead of two Signals that support SCM2 are not implemented Certain bits and register resources defined for SMC2 are not implemented The MPC870 supports one PCMCIA channel The MPC870 does not include ATM support The MPC870 does not include UTOPIA mode The MPC870 does not include the security engine The signals that are missing are described in Section G 2 1 Unimplemented Pins and in Section G 2 ...

Page 1376: ...2 PA13 TxD2 PA12 L1TXDA RXD3 PA9 Bus System Interface Unit SIU Embedded Parallel I O Memory Controller 4 Timers Interrupt Controllers 8 Kbyte Dual Port RAM System Functions 8 Kbyte Instruction Cache 32 Entry ITLB Instruction MMU 8 Kbyte Data Cache 32 Entry DTLB Data MMU Instruction Bus Load Store Bus Unified 4 Baud Rate Generators Parallel Interface Port Internal Bus Interface Unit External Bus In...

Page 1377: ...LAV TXCLAV TOUT2 PB15 RXADDR2 TXADDR2 PB14 CTS2 PC9 TGATE2 CD2 PC8 CTS3 SDACK2 L1TSYNCA PC5 CD3 L1RSYNCA PC4 UTPB 0 L1TSYNCA PD15 UTPB 1 L1RSYNCA PD14 UTPB 2 L1TSYNCB PD13 UTPB 3 L1RSYNCB PD12 RXENB RxD3 PD11 TXENB TxD3 PD10 UTPCLK TxD4 PD9 UTPB 4 RTS3 PD7 UTPB 5 RTS4 PD6 UTPB 6 CLK8 L1TCKB PD5 UTPB 7 CLK4 PD4 SOC CLK7 TIN4 PD3 WAIT_B IP_B2 IOIS16_B AT2 IP_B3 WP2 VF2 IP_B4 LWP0 VF0 IP_B5 LWP1 VF1 ...

Page 1378: ...D2 RTS3 L1RSYNCA SMTXD2 CTS3 L1TXDB L1TSYNCA SMSYN1 L1RCLKB TXD3 SOC_Split UTPB_Split 0 1 UTPB_Split2 UTPB_Split3 UTPB_Split4 UTPB_Split6 UTPB_Split7 UtpClk_Split G 2 3 SMC General Set Up Registers for the SMCs should only contain configuration bits for SMC1 Refer to Chapter 29 Serial Management Controllers SMCs The SMC1 register affected is the SMCMR1 and for interrupts ensure that only SMCE1 and...

Page 1379: ...connections the scrambling mechanism ignores this H 2 Receiving Serial ATM Cells Figure H 2 shows the serial ATM receive procedure After start up when MRBLR is zero the HEC delineation procedure begins see below Once complete cell reception commences For each cell received the HEC is checked If the HEC is incorrect the cell is still received unless the receiver loses cell delineation If the cell i...

Page 1380: ...ATM Receive Procedure ATM Rx Start Receive Cell Header Receive and Store Cell Payload MRBLR 0 Yes No Goto Transparent Mode ROM Microcode Cell Delineated Yes No HEC Correct Yes No Empty Cell No Header Match Yes No Buffer Available Yes Close Buffer and Update BD Apply HEC Delineation Mechanism Loss of Delineation Yes No Discard Cell Payload No Yes ...

Page 1381: ...single cell with an incorrect HEC is received or the RESTART RECEIVE command is given When six consecutive cells with valid HECs are received the ATM controller jumps to the sync state and begins reception The state machine advances immediately after reception of the sixth correct HEC and is not delayed until the end of the cell This means that five cells with valid HECs are discarded and the sixt...

Page 1382: ... Other SCCs and TDM B may be used For debug purposes all four SI strobes are asserted during various timeslots L1ST1 during cell header transmission L1ST2 on HEC transmission L1ST3 during cell header reception and L1ST4 on HEC reception Table H 1 Serial Interface Register Programming Example for Serial ATM Register User Writes hex SIMODE Serial interface mode register 0000 0058 SIGMR Serial interf...

Page 1383: ... Input L1RSYNCA PC4 Input L1RCLKA PA7 Input L1ST1 PB19 Output L1ST2 PB18 Output L1ST3 PB17 Output L1ST4 PB16 Output SDACK1 PC5 Output SDACK2 PC7 Output Table H 4 Port Register Programming Example Register User Writes hex PIPC PIP configuration register 0000 PADIR Port A data direction register 00C0 PAPAR Port A pin assignment register 01C0 PAODR Port A open drain register 0000 PBDIR Port B data di...

Page 1384: ...Serial ATM Scrambling Reception and SI Programming MPC885 PowerQUICC Family Reference Manual Rev 2 H 6 Freescale Semiconductor ...

Page 1385: ...ws Section Page Changes 54 6 54 8 Revised second paragraph of section before bulleted list to read as follows If TRST is not properly terminated it may be mistaken as set during slow power ramp and the chip will appear to be locked The TRST signal must be configured as follows to reset the scan chain logic I 2 Revision Changes from Revision 0 1 to Revision 1 Major changes to the MPC885 PowerQUICC ...

Page 1386: ...Revision History MPC885 PowerQUICC Family Reference Manual Rev 2 I 2 Freescale Semiconductor ...

Page 1387: ...the term refers to the fact that the transactions are indivisible The PowerPC architecture implements atomic accesses through the lwarx stwcx instruction pair Autobaud The process of determining a serial data rate by timing the width of a single bit B Big endian A byte ordering method in memory where the address n of a word corresponds to the most significant byte In an addressed memory word the b...

Page 1388: ...ration is generated typically by a Data Cache Block Flush dcbf instruction Caching inhibited A memory update policy in which the cache is bypassed and the load or store is performed to or from main memory Cast outs Cache blocks that must be written to memory when a cache miss causes a cache block to be replaced Changed bit One of two page history bits found in each page table entry PTE The process...

Page 1389: ...cessing Exception handler A software routine that executes when an exception is taken Normally the exception handler corrects the condition that caused the exception or performs some other meaningful task that may include aborting the program that caused the exception The address for each exception handler is identified by an exception vector offset defined by the architecture and a prefix selecte...

Page 1390: ...tructions that are defined only for 32 bit implementations are considered to be illegal instructions Implementation A particular processor that conforms to the PowerPC architecture but may differ from other architecture compliant implementations for example in design feature set and implementation of optional features Implementation dependent An aspect of a feature in a processor s design that is ...

Page 1391: ...trol the external bus memories and I O devices Memory coherency An aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory Memory consistency Refers to agreement of levels of memory with respect to a single processor and system memory for example on chip cache secondary cache and system memory Memory management unit MMU The funct...

Page 1392: ...wn to be required by the sequential execution model See In order Out of order execution A technique that allows instructions to be issued and completed in an order that differs from their sequence in the instruction stream Overflow An error condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register s For example if two 32 bit numbers ...

Page 1393: ...is used to specify a GPR to be used as a destination rS The rS instruction field is used to specify a GPR to be used as a source Real address mode An MMU mode when no address translation is performed and the effective address specified is the same as the physical address The processor s MMU is operating in real address mode if its ability to perform address translation has been disabled through th...

Page 1394: ...a bit or bit field the opposite of clear The term set may also be used to generally describe the updating of a bit or bit field Set n A subdivision of a cache Cacheable data can be stored in a given location in any one of the sets typically corresponding to its lower order address bits Because several memory locations can map to the same location cached data is typically placed in the set whose ca...

Page 1395: ...truction set user level registers data types floating point memory conventions and exception model as seen by user programs and the memory and programming models User mode The unprivileged operating state of a processor used typically by application software In user mode software can only access certain control registers and can access only user memory space No privileged operations can be perform...

Page 1396: ...olicy in which processor write cycles are directly written only to the cache External memory is updated only indirectly for example when a modified cache block is cast out to make room for newer data Write through A cache memory update policy in which all processor write cycles are written to both the cache and memory ...

Page 1397: ... 2 11 2 16 3 35 2 44 2 52 2 Address map SEC Lite 47 1 Address mapping CAM method 39 5 OAM screening 39 5 Address maps ATM 39 1 channel entries adding removing 39 2 VCI VPI look up table 39 1 Address multiplexing 15 46 Address translation mechanism initialization 44 27 Addressing ATM first level 39 3 ATM second level 39 3 Addressing compression ATM 39 4 Advanced Encryption Standard execution unit A...

Page 1398: ...eduling of cells 40 10 scheduling tables 40 13 timer 4 42 2 use without SCC4 or UTOPIA 40 11 with port to port programming 40 20 buffer descriptions overview 37 1 37 8 buffers port to port 39 17 channel aliasing prevention 39 4 commands 39 21 connection tables receive and transmit 37 10 receive port to port 37 15 transmit 37 20 37 24 transmit extensions 37 27 features 36 3 interface with UTOPIA pa...

Page 1399: ...stem linkage D 24 trap D 24 Branch prediction timing 9 5 Branch processing unit 3 9 Breakpoint counters 53 13 debug support 53 7 features list 53 8 load store example 53 17 operation details 53 14 BRn base registers 15 8 BS_An byte select signals 12 7 12 29 BSYNC BISYNC SYNC register 26 7 Buffer SPI Buffer Descriptor Ring 31 21 SPI Receive Buffer Descriptor 31 23 Buffer descriptors ATM overview 37...

Page 1400: ...nable command 7 15 flush cache block command 7 17 invalidate all command 7 16 load lock cache block command 7 15 load hit 7 23 memory coherency 7 6 operations 7 22 organization 7 4 read miss 7 23 reading tags 7 14 registers 7 11 snooping 7 6 store hit write back mode 7 25 store hit write through mode 7 24 store miss write back mode 7 25 store miss write through mode 7 24 unlock all commands 7 16 u...

Page 1401: ...unications processor CP command execution latency 18 10 communicating with peripherals 18 2 communicating with the core 18 2 dual port RAM 18 10 features list 18 1 host command opcodes 18 8 microcode revision number 18 4 overview 18 1 parameter RAM 18 13 PWM mode 18 18 registers 18 5 RISC timer initialization 18 18 RISC timer tables 18 14 SET TIMER command 18 15 tracking CP loading 18 19 Communica...

Page 1402: ...nter status register 50 4 registers 50 2 CSn chip select signals 12 6 12 28 D Data and control signals UTOPIA 42 5 Data bus contents for write cycles 13 25 requirements for read cycles 13 25 Data cache miss timing 9 3 Data Encryption Standard execution units DEUs 46 5 48 2 DC_ADR data cache address register 7 13 DC_CST data cache control and status register 7 11 DC_CST commands 7 15 DC_DAT data ca...

Page 1403: ... DSI 6 6 DTLB error 6 14 8 31 DTLB miss 6 13 8 31 exception handling 6 1 15 46 exception latency 6 18 exception priority 6 4 external interrupt 6 6 external reset 19 18 floating point assist 6 11 instruction offset 6 2 instruction related 5 6 integer alignment 6 8 ISI 6 6 ITLB error 6 13 8 31 ITLB miss 6 12 8 31 list 6 2 machine check interrupt 6 5 MMU exceptions 8 31 ordering 6 3 overview 41 1 pa...

Page 1404: ...9 2 transparent mode 29 20 UART mode 29 10 UART mode features not supported 29 9 serial peripheral interface SPI 30 1 system interface unit 10 1 UTOPIA 43 1 watchpoint debug support 53 8 Frame reception FEC 45 5 Frame transmission 45 4 Freeze operation 10 28 FRZ freeze signal 12 6 12 28 Full completion queue timing 9 3 G General purpose chip select machine GPCM 15 18 General purpose signals 15 43 ...

Page 1405: ...er RAM 19 7 registers 19 7 suspending 19 13 TEA signal 19 19 transfers 19 14 dual address 19 15 external recognition 19 18 IDMA request for peripheral to memory transfers 19 14 interrupts during a bus transfer 19 18 single address 19 15 IDMR1 IDMA1 mask register 19 9 IDMR2 IDMA2 mask register 19 9 IDSR1 41 2 IDSR1 IDMA1 status register 19 9 IDSR2 IDMA2 status register 19 9 IEEE 1149 1 test access ...

Page 1406: ...17 sorted by mnemonic D 1 reserved 5 4 SAMPLE PRELOAD 54 6 segment register manipulation D 25 stwcx 7 26 summary of instructions 5 2 system linkage 5 20 D 24 TAP instructions 54 5 TLB management instructions D 25 trap 5 15 trap instructions D 24 UISA 5 7 Integer arithmetic instructions D 17 Integer compare instructions D 18 Integer load instructions D 21 Integer logical instructions D 18 Integer m...

Page 1407: ...atus register 48 17 MDR memory data register 15 17 Memory controller basic architecture 15 4 block diagram single UPM 15 3 external master support 15 55 features summary 15 1 memory system interface 15 63 overview 15 1 page mode extended data out interface 15 74 registers 15 8 Memory maps CP dual port RAM 18 12 FEC parameter RAM 45 12 IDMA channel 19 7 internal 2 1 PIP 2 11 reference 2 1 RISC time...

Page 1408: ...5 E 1 Signals 12 1 MPC885 application example 36 5 basic core structure 3 5 block diagram 3 4 comparison with MPC860 36 1 comparison with MPC870 G 1 comparison with MPC875 F 1 comparison with MPC880 E 1 features 1 2 1 6 features lists 36 3 PowerPC architecture adherence 3 1 3 14 programming model 45 10 Signals 12 1 System Interface Unit 1 16 MPC885 PowerPC quad integrated communications controller...

Page 1409: ...terface 33 17 Centronics interface implementation 33 19 Centronics receive errors 33 22 Centronics receiver 33 21 Centronics transmit errors 33 21 Centronics transmitter 33 20 control character table 33 6 core control vs CP control 33 2 CP commands 33 14 features 33 1 handshaking I O modes 33 15 interlocked handshake mode 33 15 overview 33 1 parameter RAM 33 3 pulsed handshake mode 33 16 RCCM RCCR...

Page 1410: ...R periodic interrupt timer register 10 28 PLPRCR PLL low power and reset control register 14 21 PORESET power on reset signal 12 8 12 30 PORn PCMCIA option register 16 14 Port D pin assignment register PDPAR 34 20 42 1 port to port 37 24 Port to port switching ATM 39 15 Power control disabling SCC 21 26 low power modes 14 17 overview 14 1 Power supply signals 12 23 12 39 Power on reset reset seque...

Page 1411: ...EC frame reception 45 5 reception errors 45 9 Register set 3 9 Registers AESU context 48 34 data size 48 27 end of message 48 34 interrupt control 48 32 interrupt status 48 30 key 48 36 key size 48 26 mode 48 24 reset control 48 28 AFEU status 48 29 APCST 38 14 38 15 AppleTalk mode GSMR 24 3 PSMR 24 4 TODR 24 4 ASTATUS 38 16 asynchronous HDLC mode DSR 25 6 GSMR 25 6 PSMR 25 10 SCCE 25 8 SCCM 25 8 ...

Page 1412: ...eneral descriptions 45 12 general SCC mode GSMR 42 7 GSMR asynchronous HDLC mode 25 6 overview 21 3 HDLC mode PSMR 23 7 SCCE 23 12 SCCM 23 12 SCCS 23 14 I_EVENT interrupt event I_MASK interrupt mask 45 19 I_VEC ethernet intrrupt vector 45 20 I2C controller I2ADD 32 7 I2BRG 32 7 I2CER 32 7 I2CMR 32 7 I2COM 32 8 I2MOD 32 6 IC_ADR 7 7 7 8 IC_CST 7 6 7 9 IC_DAT 7 8 ICR 53 42 ICTRL 53 37 IDMA channels ...

Page 1413: ... 1 PISCR 10 26 PITC 10 27 PITR 10 28 supervisor level MSR 4 6 PVR 4 8 summary 4 4 4 9 C 2 TBREFU TBREFL 10 24 TBSCR 10 25 TBU TBL 10 23 user level CR 4 2 summary 4 1 C 1 TBU TBL 4 4 XER 4 3 PSMR asynchronous HDLC mode 25 10 BISYNC mode 26 10 Ethernet mode 27 15 overview 21 10 transparent mode 28 7 UART mode 22 13 quick reference guide C 1 R_BUFF_SIZE receive buffer size 45 17 R_DES_ACTIVE RxBD Act...

Page 1414: ...SMCE 29 29 SMCM 29 29 UART mode RxBD 29 14 SMCE 29 18 SMCM 29 18 TxBD 29 17 serial peripheral interface RFCR 30 11 SPCOM 30 9 SPIE 30 8 SPIM 30 8 SPMODE 30 6 TFCR 30 11 settings after alignment exception 6 7 debug exception 6 15 decrementer exception 6 10 DTLB error exception 6 14 DTLB miss exception 6 13 external interrupt 6 7 ITLB error exception 6 14 ITLB miss exception 6 13 program exception 6...

Page 1415: ...nd status register 38 11 SCC1 memory map 2 8 SCC4 memory map 2 9 SCCE 41 3 SCCE SCC event register asynchronous HDLC 25 8 HDLC mode 23 12 SCCE SCC event register BISYNC mode 26 14 Ethernet mode 27 20 transparent mode 28 10 UART mode 22 19 SCCM SCC mask register asynchronous HDLC 25 8 BISYNC mode 26 14 Ethernet mode 27 20 HDLC mode 23 12 transparent mode 28 10 UART mode 22 19 SCCR system clock and ...

Page 1416: ...ing 26 9 frame reception 26 3 frame transmission 26 2 frames classes 26 1 memory map 26 3 overview 26 1 parameter RAM 26 3 programming example 26 17 programming the controller 26 16 receiving synchronization sequence 26 8 RxBD 26 11 sending synchronization sequence 26 8 TxBD 26 13 Ethernet mode address recognition 27 11 collision handling 27 13 commands 27 10 connecting 27 5 error handling 27 14 e...

Page 1417: ...us implementation activation 20 32 deactivation 20 32 overview 20 31 programming example 20 33 programming GCI 20 32 SI RAM settings 20 33 signals 20 31 IDL bus implementation overview 20 27 programming the IDL 20 30 SI RAM settings 20 30 signals 20 28 ISDN terminal adaptor 20 27 NMSI configuration features list 20 4 overview 20 34 overview 20 1 registers 20 15 serial ATM configuration with 42 8 S...

Page 1418: ...ster SCCE 41 3 Serial peripheral interface SPI block diagram 30 1 buffer descriptors 30 12 clocking functions 30 2 commands 30 12 configuring the controller 30 3 examples using SPMODE 30 8 features list 30 1 interrupt handling 30 17 master mode overview 30 3 programming example 30 15 memory structure 30 12 multi master operation 30 4 overview 30 1 parameter RAM 30 10 registers 30 6 RxBD 30 13 sign...

Page 1419: ...EA 12 5 12 27 13 5 13 33 termination signals protocol 13 33 TEXP 12 9 12 31 TMS 12 22 12 38 TRST 12 22 12 38 TS 12 4 12 26 13 4 13 29 TSA 29 23 TSIZn 12 4 12 26 13 4 13 30 UPWAITx 12 8 12 30 Utopia data and control 42 5 UTOPIA TxClav 42 3 VF 53 3 VFLS 53 3 WAIT_x 12 9 12 31 WEn 12 7 12 29 XTAL 12 9 12 31 signals multiplexing PCMIA 42 6 SIMASK SIU interrupt mask register 10 16 SIMODE SI mode regist...

Page 1420: ... features summary 10 1 overview 10 1 programming the interrupt controller 10 14 programming the SIU 10 4 System linkage instructions D 24 System protection overview 10 2 System reset interrupt 4 12 T TA transfer acknowledge signal 12 5 12 27 13 5 13 33 TAP test access port see IEEE 1149 1 test access port TBREFU TBREFL timebase reference upper lower registers 10 24 TBSCR timebase status and contro...

Page 1421: ...l 40 9 PHY APC 40 14 restart command 39 23 SAR transmit function code and status register 38 10 38 11 transmitter UTOPIA mode 36 7 Transmit activate channel command 39 23 Transmit buffer descriptor 45 36 Transmit deactivate channel command 39 23 Transparent mode achieving synchronization 28 2 commands 28 6 error handling 28 7 frame reception 28 2 frame transmission 28 1 overview 28 1 programming e...

Page 1422: ...36 7 supporting expanded cells 36 8 transmit 36 7 signals data and control 42 5 split bus 43 6 UTOPIA mode IDSR1 register 41 2 initialization 42 6 overview 36 6 parameter RAM configuration 38 1 registers 42 2 single PHY 43 5 UTOPIA mode event register IDSR1 41 2 V Virtual environment architecture VEA description 3 3 MPC885 adherence 3 16 W WAIT mechanism 15 52 Watchpoint counters 53 13 debug suppo...

Page 1423: ... Control 14 Memory Controller 15 PCMCIA Interface 16 Part V Communications Processor Module V Communications Processor Module and CPM Timers 17 Communications Processor 18 SDMA Channels and IDMA Emulation 19 Serial Interface 20 Serial Communications Controllers 21 SCC UART Mode 22 SCC HDLC Mode 23 SCC AppleTalk Mode 24 SCC Asynchronous HDLC Mode and IrDA 25 SCC BISYNC Mode 26 SCC Ethernet Mode 27 ...

Page 1424: ...wer Control 15 Memory Controller 16 PCMCIA Interface V Part V Communications Processor Module 17 Communications Processor Module and CPM Timers 18 Communications Processor 19 SDMA Channels and IDMA Emulation 20 Serial Interface 21 Serial Communications Controllers 22 SCC UART Mode 23 SCC HDLC Mode 24 SCC AppleTalk Mode 25 SCC Asynchronous HDLC Mode and IrDA 26 SCC BISYNC Mode 27 SCC Ethernet Mode ...

Page 1425: ...III SEC Lite Overview 46 SEC Lite Address Map 47 SEC Lite Execution Units 48 SEC Lite Descriptors 49 SEC Lite Crypto Channel 50 SEC Lite Controller 51 Fast Ethernet Controller FEC 52 Part IX System Debugging and Testing Support IX System Development and Debugging 53 IEEE 1149 1 Test Access Port 54 Byte Ordering A Serial Communications Performance B Register Quick Reference Guide C Instruction Set ...

Page 1426: ...ite 46 SEC Lite Overview 47 SEC Lite Address Map 48 SEC Lite Execution Units 49 SEC Lite Descriptors 50 SEC Lite Crypto Channel 51 SEC Lite Controller 52 Fast Ethernet Controller FEC IX Part IX System Debugging and Testing Support 53 System Development and Debugging 54 IEEE 1149 1 Test Access Port A Byte Ordering B Serial Communications Performance C Register Quick Reference Guide D Instruction Se...

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