Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Memory Map
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 2-11
A9A SMCM2—SMC2 mask register 8 bits 29.3.12/29-18 (UART)
29.4.11/29-29 (Transparent)
29.5.9/29-35 (GCI)
A9B–A9F Reserved 5 bytes —
Serial Peripheral Interface (SPI)
AA0 SPMODE—SPI mode register 16 bits 30.4.1/30-6
AA2–AA5 Reserved 4 bytes —
AA6 SPIE—SPI event register 8 bits 30.4.2/30-8
AA7–AA9 Reserved 3 bytes —
AAA SPIM—SPI mask register 8 bits 30.4.2/30-8
AAB–AAC Reserved 2 bytes —
AAD SPCOM—SPI command register 8 bits 30.4.3/30-9
AAE–AB1 Reserved 4 bytes —
Parallel Interface Port (PIP) and Port B
AB2 PIPC—PIP configuration register 16 bits 33.4.1/33-8
AB4–AB5 Reserved 2 bytes —
AB6 PTPR—PIP timing parameters register 16 bits 33.4.4/33-10
Port B Registers
AB8 PBDIR—Port B data direction register 32 bits 34.3.1.3/34-10
ABC PBPAR—Port B pin assignment register 32 bits 34.3.1.4/34-11
AC0 PBODR—Port B open drain register 32 bits 34.3.1.1/34-9
AC4 PBDAT—Port B data register 32 bits 34.3.1.2/34-9
Port E Registers
AC8 PEDIR — Port E data direction register 32 bits 34.6.1.3/34-23
ACC PEPAR — Port E data assignment register 32 bits 34.6.1.4/34-24
ADO PESO — Port E special options 32 bits 34.6.2/34-25
AD4 PEODR — Port E open drain register 32 bits 34.6.1.1/34-22
AD8 PEDAT — Port E data register 32 bits 34.5.1.1/34-18
Communications Processor Timing Register - Contains RMII Timing for the FECs
ADC CPTR — CPTR Register 32 bits 45.3.1/45-11 ,
52.1/52-1
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset Name Size Section/Page