Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 13-1
Chapter 13
External Bus Interface
The MPC885 bus is a synchronous, burstable bus that can support multiple masters. Signals driven on this
bus are required to make the setup and hold time relative to the bus clock’s rising edge. The MPC885
architecture supports byte, half-word, and word operands allowing access to 8-, 16-, and 32-bit data ports
through the use of synchronous cycles controlled by the size outputs (TSIZ0, TSIZ1). Access to 16- and
8-bit ports is done for slaves controlled by the memory controller.
13.1 Features
The MPC885 bus interface features are listed as follows:
• 32-bit address bus with transfer size indication
• 32-bit data bus
• Dynamic bus sizing to 32-, 16-, or 8-bit ports accessed through the memory controller
• TTL-compatible interface
• Bus arbitration supported optionally by internal or external logic
• Bus arbitration logic on-chip supports an external master with programmable priority
• Compatible with PowerPC architecture
• Easy to interface to slave devices
• Bus is synchronous (all signals are referenced to rising edge of bus clock)
13.2 Bus Transfer Overview
The bus transfers information between the MPC885 and external memory or a peripheral device. External
devices can accept or provide 8, 16, and 32 bits in parallel and must follow the handshake protocol
described in this section. The maximum number of bits accepted or provided during a bus transfer is
defined as port width.
The MPC885’s address bus specifies the address for the transfer and its data bus transfers the data. Control
signals indicate the beginning of the cycle and the type of cycle, as well as the address space and size of
the transfer. The selected device controls cycle length with signal(s) used to terminate the cycle. A strobe
signal for the address bus indicates the validity of the address and gives data timing information. The
MPC885 bus is synchronous, therefore, the bus and control input signals must be timed to setup and hold
times relative to the rising edge of the clock. At minimum, single-beat bus cycles can be completed in two
clock cycles.
Furthermore, for all inputs, the MPC885 latches the input’s level during a sample window, shown in
Figure 13-1 , around the rising clock edge. To ensure that an input signal is recognized on a specific rising
clock edge, that input must be stable during the sample window. If an input changes during the window,