Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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SEC Lite Crypto-Channel
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 50-11
50.1.4 Fetch Register (FR)
The FR, displayed in Figure 50-5 , contains the address of the first byte of a descriptor to be processed. In
typical operation, the host CPU will create a descriptor in memory containing all relevant mode and
location information for the SEC Lite, and then “launch” the SEC Lite by writing the address of the
descriptor to the fetch register.
Writes to the FR, while the channel is already processing a different descriptor, will be registered and held
pending until the channel finishes processing the current descriptor or chain of descriptors. When the end
of the current descriptor or chain of descriptors is reached, the descriptor pointed to by the FR will be
treated as the next descriptor in a multi-descriptor chain. In this case, the FR must be written to before the
channel begins end of descriptor notification. If the register is written after notification has begun, the
descriptor will not be considered part of the current chain and will be fetched as a new stand alone
descriptor or start of chain after the notification process has completed.
In summary, a channel is initiated by a direct write to the FR, and the channel always checks the FR before
determining if it has truly reached the end of a chain.
NOTE
End of descriptor notification consists of modified header writeback or
channel DONE interrupt. The fetch address must be modulo-4 aligned if
writeback is enabled as the method of DONE notification.
Figure 50-5. Fetch Register
Table 50-9 describes the fetch register fields.
0 31
Field Reserved
Reset 0x0000_0000
R/W R/W
Addr 0x02048
0 31
Field Fetch Address
Reset 0x0000_0000
R/W R/W
Addr 0x0204C
Table 50-9. Fetch Register Fields
Bits Name Reset Value Description
0–31 FETCH ADRS 0x0000_0000 Pointer to system memory location of a descriptor the host wants the SEC Lite to
fetch.