Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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SEC Lite Master/Slave Interface Module
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 52-3
• When bus read begins, controller receives data from the Master/Slave interface module and
performs a master write to the appropriate internal address using the address supplied by the
channel. Data always goes through the misalignment block.
• Transfer continues until the bus burst read is completed and the controller has written all data to
the appropriate internal address. The Master/Slave interface module will continue making bus
requests until the full data length has been read. The Master/Slave interface module will also make
single reads when the amount of data remaining to be fetched is less than an 8xx burst (less than a
full cache line.)
52.2.3.1 Target Aborts
It is possible for the intended target of an SEC Lite master initiated transaction to terminate the transfer
due to an error. Every time a Transfer Error Acknowledge is received from a target, the TEA bit in
Figure 51-4 is set, and, unless masked by Figure 51-2 , the SEC Lite channel that requested the transfer will
signal interrupt through Figure 51-4 . The host will be able to determine which channel generated the
interrupt by checking the ISR for the channel ERROR bit. The controller will also log the target address
which terminated with a TEA in the
Figure 51-9 .
52.2.4 Master Write
Master writes are performed by transferring data from one of the EUs to the output FIFO in the controller,
then transferring the data from the FIFO to the bus when the bus is granted to the controller. The sequence
for a Master bus write access is as follows:
• Channel requests the bus from controller.
• Controller acknowledges request to channel.
• Channel furnishes address, transfer length.
• Controller loads the write data into its FIFO, and waits for the bus to become available.
• When the bus becomes available, controller writes data from its FIFO to the Master/Slave Interface
Module.
• Transfer continues until the bus burst write is completed and the controller has read all data from
the appropriate internal address. The Master/Slave interface module will continue making bus
requests until the full data length has been written. The Master/Slave Interface Module will also
make single reads when the amount of data remaining to be written is less than an 8xx burst (less
than a full cache line.)
52.2.5 Misaligned Data
The controller has the ability to initiate a bus read. In some cases, the address for the read may not be
aligned to a modulo 8 boundary. In these cases, the controller will realign the data to a modulo 8 boundary
as it comes in from the Master/Slave Interface Module.
The data alignment block will fetch the data from the bus at modulo 8 addresses. This block will continue
fetching data until the number of bytes left to read is equal to or less than the width of the master data bus.