Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Memory Controller
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 15-51
15.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3)
During a memory access, the UTA bit of the RAM word controls the state of TA driven by the UPM. TA
is driven on the rising edge of GCLK2_50. Therefore, because TA is also sampled on the rising edge of
GCLK2_50, programming UTA to assert in the RAM word causes the bus master to sample TA as asserted
in the next cycle.
When a read access is handled by the UPM and the UTA bit is 0, the value of the DLT3 bit in the same
RAM word indicates when the data input is sampled by the internal bus master, assuming that
MxMR[GPLx4DIS] = 1.
• If G4T4/DLT3 functions as DLT3 and DLT3 = 1 in the RAM word, data is latched on the falling
edge of GCLK2_50 instead of the rising edge, which is normal. This feature lets the user speed up
the memory interface by latching data 1/2 clock early, which can be useful during burst reads. This
feature should be used only in systems without external synchronous bus devices.
32 bits 256 Kbyte 8 8 A22:A29 000
512 Kbyte 9 A21:A29
1 Mbyte 10 A20:A29
2 Mbyte 11 A19:A29
4 Mbyte 12 A18:A29
1 Mbyte 9 9 A21:A29 001
2 Mbyte 10 A20:A29
4 Mbyte 11 A19:A29
8 Mbyte 12 A18:A29
16 Mbyte 13 A17:A29
4 Mbyte 10 10 A20:A29 010
8 Mbyte 11 A19:A29
16 Mbyte 12 A18:A29
32 Mbyte 13 A17:A29
64 Mbyte 14 A16:A29
16 Mbyte 11 11 A19:A29 011
32 Mbyte 12 A18:A29
64 Mbyte 13 A17:A29
64 Mbyte 12 12 A18:A29 100
128 Mbyte 13 A17:A29
256 Mbyte 14 A16:A29
256 Mbyte 13 13 A17:A29 101
Table 15-19. AMA/AMB Definition for DRAM Interface (continued)
Data Bus Width Memory Size
DRAM Address Pin Number
MPC885 Address
Pin Connection
AM
x
Row Column