Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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System Development and Debugging
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 53-31
Transmissions from the debug port on DSDO begin with a zero or ready bit, indicating that the core is
trying to read an instruction or data from the port. The external development tool must wait until it sees
DSDO go low before sending the next transmission. The control bit distinguishes instructions from data,
allowing the development port to detect that an instruction was entered when the core was expecting data
and vice versa. If this occurs, a sequence error indication is shifted out in the next serial transmission. The
trap enable function allows the development port to transfer data to the trap enable control register. The
debug port command function allows the development tool to either negate breakpoint requests, reset the
processor, activate, or deactivate the fast download procedure. The NOP function provides a null operation
for use when there is data or a response to be shifted out of the data register. The appropriate next
instruction or command will be determined by the value of the response or data shifted out.
53.3.2.5.2 Serial Data Out of Development Port
The encoding of data shifted out of the development port shift register in debug mode is the same as for
trap enable mode, as shown in
Table 53-12 . The valid data encoding is used when data has been transferred
from the core to the development port shift register as the result of an instruction to move the contents of
a GPR to the DPDR. The valid data encoding has the highest priority of all status outputs and is reported
even if an interrupt occurs at the same time. Because a sequencing error cannot occur when data is valid,
there is no priority conflict with the sequencing error status. Also, an interrupt recognized when there is
valid data is not related to the execution of an instruction, therefore, a valid data status is output and the
interrupt status is saved for the next transmission.
The sequencing error encoding indicates that the inputs from the external development tool are not what
the development port and/or the core was expecting. There are two possible causes for this error:
• The processor was trying to read instructions and data was shifted into the development port.
• The processor was trying to read data and an instruction was shifted into the development
port.
Nonetheless, the port terminates the read cycle with a bus error. In turn, this bus error causes the core to
signal that an interrupt exception occurred. Because a status of sequencing error is of higher priority than
an exception, the port reports the sequencing error first and the core interrupt on the next transmission. The
development port ignores the command, instruction, or data shifted in while the sequencing error or core
Table 53-13. Debug Instructions/Data Shifted Into Development Port Shift Register
Start Mode Control
Instruction/Data (32 Bits)
Function
Bits 0–6 Bits 7–31
1 0 0 Core instruction Transfer instruction to core
1 0 1 Core data Transfer data to core
1 1 0 Trap enable bits Not exist Transfer data to trap enable control register
1 1 1 0b001_1111 Not exist Negate breakpoint requests to core
1 1 1 0 Not exist NOP
Note: See Table 53-10 for details on trap enable bits.