Freescale Semiconductor PowerQUICC MPC870, Reference Manual

Page: 1077 / 1426

Interface Configuration
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 42-3
The fields related to the internal UTOPIA clock in the SCCR register are described in Table 42-2 .
42.2.2 Port B—MasterTxClav/Slave RxClav and PHY Address Signals
Port B provides the PHY address signals for multi-PHY operation and one of the UTOPIA cell-available
control signals. In master mode, PB15 acts as the TxClav input signal; in slave mode (MPC885 split bus
mode only), PB15 acts as the RxClav output signal.
UTOPIA multi-PHY operations use port B for RxAddr[4:0] and TxAddr[4:0] signals. The number of
active PHY address signals is programmed in UTMODE; see
Section 43.2, “UTOPIA Mode Register
(UTMODE).” Table 42-3 shows the port programming to enable the UTOPIA signals on port B.
0 26 27 29 30 31
Field As described in
Section 14.6.1, “System Clock and Reset Control Register (SCCR).”
DFUTP DFAUTP
Reset 0 0 0 0 0
Oper R/W R/W R/W R/W R/W
Addr Offset to IMMR: 0x280 (SCCR)
Figure 42-2. System Clock Control Register (SCCR)
Table 42-2. SCCR Field Descriptions for the Internal UTOPIA Clock
Bits Name Description
0–26 See “ Section 14.6.1, “System Clock and Reset Control Register (SCCR),” for field names
and definitions.
27–29 DFUTP Division factor for UTPCLK. Divide the system clock by 2
DFUTP
.
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
1xx Reserved
30–31 DFAUTP Additional division factor for UTPCLK. Divide the system clock by (2 x 1)
00 Divide by 1
01 Divide by 3
10 Divide by 5
11 Divide by 7