Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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ATM Exceptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 41-3
41.1.2 Serial ATM Event Register (SCCE)
The SCCEs act as the ATM event registers for serial mode and are used to report events and generate
interrupt requests. Note that in serial ATM mode, interrupts from the ATM port are reported with the
appropriate SCC vector in the CIVR, and the appropriate SCC bit is set in the CIPR. Setting the
corresponding bit in the mask register SCCM enables the actual generation of the interrupt request. Event
bits are cleared by writing ones; writing zeros has no effect.
Figure 41-3 shows the serial ATM event and
mask registers.
Table 41-2 describes the serial ATM event register fields.
6 GUN Global transmitter underrun. Indicates that an underrun occurred in the UTOPIA’s transmitter cell
FIFO in case the UTOPIA transmitter is used in slave mode. This underrun can occur only if an
external UTOPIA master attempts to read a cell by asserting TxEnb (transition from high to low)
while the internal FIFO is not ready (TxClav is deasserted). In this case, a GUN interrupt will be
issued to indicate that the master is reading an invalid cell.
7 GOV Global receiver overrun. Indicates that an overrun occurred in the cell FIFO of the UTOPIA slave
receiver. This overrun occurs only if an external UTOPIA master attempts to write a cell to the
MPC885 by asserting RxEnb while the internal FIFO is not ready (RxClav is not asserted). In this
case, a GOV interrupt is issued to indicate that the write attempt failed and the cell has been
dropped.
0 2 3 4 5 6 10 11 12 13 14 15
Field — GLR GLT DCC — SYNC IQOV GINT GUN GOV
Figure 41-3. Serial ATM Event Register (SCCE) and Mask Register (SCCM)
Table 41-2. Serial ATM Event Register (SCCE) Field Descriptions
Bits Name Description
0–2 — Reserved
3 GLR Glitch on receive. A clock glitch has been detected by the SCC on the receive clock.
4 GLT Glitch on transmit. A clock glitch has been detected by the SCC on the transmit clock.
5 DCC DPLL carrier sense status change. Indicates carrier sense status generated by the DPLL has
changed state. The value of the DCC bit is valid only when the DPLL is enabled.
6–10 — Reserved
11 SYNC Cell synchronization changed status. Indicates that the receiver has lost or gained cell delineation.
The SYNC interrupt is signaled whenever the receiver changes lock status (refer to the ASTATUS
lock bit in
Section 38.7, “Multi-PHY State Register (MPHYST) (UTOPIA Master Only).”
If synchronization is lost (lock bit is cleared), the SYNC interrupt indicates a fatal ATM reassembly
error because the affected channels are unknown. When this happens, the receiver stops receiving
data from all channels and all data transfers to memory halt. After re-initializing the channels, the
host may resume receiving cells by executing the
RESTART RECEIVE
command (see Section 39.7,
“ATM Commands” ) for each channel.
Table 41-1. UTOPIA Event Register (IDSR1) Field Descriptions (continued)
Bits Name Description