Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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SEC Lite Execution Units
MPC885 PowerQUICC Family Reference Manual, Rev. 2
48-28 Freescale Semiconductor
Figure 48-20. AESU Data Size Register
48.3.5 AESU Reset Control Register
This register allows 3 levels reset of just AESU, as defined by the 3 self-clearing bits:
Figure 48-21. AESU Reset Control Register
Table 48-3 describes AESU reset control register fields.
0 1 7 8 31
Field — Data Size —
— msb<—lsb
Reset 0x0000_0000
R/W R/W
Addr AESU 0x04010
0 31
Field Reserved
Reset 0x0000_0000
R/W R/W
Addr AESU 0x04014
0 4 5 6 7 8 31
Field — RI MI SR —
Reset 0x0000_0000
R/W R/W
Addr AESU 0x04018
0 31
Field Reserved
Reset 0x0000_0000
R/W R/W
Addr AESU 0x0401C
Table 48-13. AESU Reset Control Register Field Descriptions
Bits Names Description
0–4 — Reserved
5 RI Reset Interrupt. Writing this bit active high causes AESU interrupts signalling DONE and
ERROR to be reset. It further resets the state of the AESU interrupt status register.
0 Don’t reset
1 Reset interrupt logic