Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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External Bus Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
13-32 Freescale Semiconductor
Show cycles are accesses to the core’s internal bus devices. These accesses are made visible externally for
emulation and debugging. A show cycle can have one address phase and one data phase (or just an address
phase for the instruction show cycles). The cycle can be a write or a read access. The address of the show
cycle is valid on the bus for one clock and the data of the show cycle is valid on the bus for one clock. The
data phase does not require a transfer acknowledge to terminate the bus-show cycle. In a burst-show cycle,
only the first data beat is shown externally.
When AT3 = 0 for an access from the core, it indicates either program trace (for an instruction cycle) or
reservation (for a data cycle). These indications can also be monitored on two separate signals (PTR and
RSV), if desired.
• PTR is low when the following is true:
— AT0 = 0 (Core access)
— AT2 = 0 (Instruction)
— AT3 = 0 (Program Trace)
x 1 0 0 0 0 0 1 Core-initiated, show cycle
address instruction,
program trace, supervisor
mode
1 1 1 Core-initiated, show cycle
address instruction,
supervisor mode
1 0 1 0 Core-initiated, reservation
show cycle data, supervisor
mode
1 1 1 Core-initiated, show cycle
data, supervisor mode
1 0 0 0 1 Core-initiated, show cycle
address instruction,
program trace, user mode
1 1 1 Core-initiated, show cycle
address instruction, user
mode
1 0 1 0 Core-initiated, reservation
show cycle data, user mode
1 1 1 Core-initiated, show cycle
data, user mode
1 AT1 AT2 AT3 1 1 DMA-initiated, normal,
AT[1:3] user-programmable
(see IDMA and DMA
function code registers)
Table 13-5. Address Types Definition (continued)
STS TS
Core/
CPM
(AT0)
User/
Supervisor
(AT1)
Instruction/
Data (AT2)
Reservation/
Program Trace
(AT3)
Program
Trace
(PTR)
Reservation
(RSV)
Address Space
Definitions