Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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SEC Lite Execution Units
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 48-35
during message processing, a context error will be generated. All context registers are cleared when a
hard/soft reset or initialization is performed.
The context registers must be read when changing context and restored to their original values to resume
processing an interrupted message (CBC and CTR modes). Although there are 7 64-bit context register
fields, only those fields containing data must be read and restored during context switching.
Context should be loaded with the lower bytes in the lowest 64-bit context register. The Context registers
are summarized in
Figure 48-26 .
1
Must be written at the start of a new message
Figure 48-26. AESU Context Register
48.3.9.2 Context for CBC Mode
Within the Context register, for use in CBC mode, are two 64-bit context data registers that allow the host
to read/write the contents of the initialization vector (IV):
• IV1 holds the least significant bytes of the initialization vector (bytes 1–8).
• IV2 holds the most significant bytes of the initialization vector (bytes 9–16).
The IV must be written prior to the message data. If the IV registers are written during message processing,
or the CBC mode bit is not set, a context error will be generated.
The IV registers may only be read after processing has completed, as indicated by the assertion of Interrupt
Done DONE in the AESU status register as shown in
Section 48.3.6, “AESU Status Register”. If the IV
registers are read prior to assertion of Interrupt Done, an early read error will be generated.
The IV registers must be read when changing context and restored to resume processing an interrupted
message (CBC mode only).
48.3.9.3 Context for Counter Mode
In counter mode, a random 128-bit initial counter value is incremented modulo 2
n
with each block
processed. The modulus size can be set between 2
8
through 2
128
, by powers of 8. The running counter is
encrypted and eXclusive-ORed with the plaintext to derive the ciphertext, or with the ciphertext to recover
the plaintext.
In CTR mode, the block counter is incremented modulo 2
M
. The value of M is specified by writing to
Context Register 3 as described in Table 48-17 .
Context Register (64-bits each)
Cipher Mode
1 2 3 4 5 6 7
ECB — — — — — — —
CBC IV1
1
IV2
1
— — — — —
CTR Counter
1
Counter
Modulus
1
(msb<--lsb)
— — — —