Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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AAL2 Implementation
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 44-13
then, if the active buffer for channel n is only partially filled, AAL2 sets the nth bit in the 9th row of the
wait table (6 rows from the position of the wait pointer).
44.4.5.2 Example of Timer CU Implementation
In Figure 44-5 , the wait table is implemented with 10 rows. There are six AAL2 channels (channels
32-37). The width of the wait table is three half-word (48 bits). Columns 0-31, 38-47 of the wait table are
unused (must be cleared by the host during initialization). The table width is programmable in 16-bit
increments.
Figure 44-5. Example of the Wait Table
The wait pointer points to row 6. Channels 32, 34 and 37 have partially filled active buffers:
• Channel 34 expires in one RISC timer period
• Channel 32 expires in three RISC timer periods
• Channel 37 expires in four RISC timer periods
Note that if the partially filled active buffer is filled before its time expires, AAL2 clears the channel’s bit
in the wait table.
44.5 AAL2 Data Structures for Receive
This section describes the AAL2 data structures used for receiving AAL2 packets.
44.5.1 Receive Packet Descriptor (RPD)
Similar to buffer descriptors, each receive packet descriptor (RPD), shown in Figure 44-6 , contains control
bits and the pointer to the CPS_Packet. However, the RPD does not contain status bits. The status feedback
from the CP is given through the exception queue; see
Section 44.9, “AAL2 Exceptions.” The host should
program all RPD fields during initialization.
AAL2_TxWait_BASE
.
AAL2_TxWait_PTR
0-31 33 34 35 32 36 3738-47
0 0
0 0 0 0 0 0 1
1 0
0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0
6 0
0 0 0 0 0 0 0
7 0 0 0 1 0 0 0 0
8 0
0 0 0 0 0 0 0
9 0 1 0 0 0 0
0 0
AAL2_TxWait_LAST