Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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MPC885 Instruction Set
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 5-13
big-endian and little-endian byte ordering, see “Byte Ordering” in Chapter 3, “Operand Conventions,” in
The Programming Environments Manual.
5.2.4.2.5 Integer Load and Store Multiple Instructions
The integer load/store multiple instructions move blocks of data to and from the GPRs. In some
implementations, these instructions are likely to have greater latency and take longer to execute, perhaps
much longer, than a sequence of individual load or store instructions that produce the same results.
When the MPC885 is operating with little-endian byte order, execution of a load or store multiple
instruction causes the system alignment error handler to be invoked; see “Byte Ordering” in Chapter 3,
“Operand Conventions,” in the Programming Environments Manual for more information.
Table 5-10 lists
the integer load and store multiple instructions for the MPC885.
5.2.4.2.6 Integer Load and Store String Instructions
The integer load and store string instructions allow movement of data from memory to registers or from
registers to memory without concern for alignment. These instructions can be used for a short move
between arbitrary memory locations or to initiate a long move between misaligned memory fields.
When the MPC885 is operating with little-endian byte order, execution of a load or store string instruction
causes the system alignment error handler to be invoked; see “Byte Ordering” in Chapter 3, “Operand
Conventions,” in the Programming Environments Manual for more information.
Table 5-11 lists the
integer load and store string instructions.
Table 5-9. Integer Load and Store with Byte-Reverse Instructions
Name Mnemonic Syntax
Load Half Word Byte-Reverse Indexed lhbrx r D, r A, r B
Load Word Byte-Reverse Indexed lwbrx r D, r A, r B
Store Half Word Byte-Reverse Indexed sthbrx r S, r A, r B
Store Word Byte-Reverse Indexed stwbrx r S, r A, r B
Table 5-10. Integer Load and Store Multiple Instructions
Name Mnemonic Syntax
Load Multiple Word lmw r D,d( r A)
Store Multiple Word stmw r S,d( r A)
Table 5-11. Integer Load and Store String Instructions
Name Mnemonic Syntax
Load String Word Immediate lswi r D, r A,NB
Load String Word Indexed lswx r D, r A, r B
Store String Word Immediate stswi r S, r A,NB
Store String Word Indexed stswx r S, r A, r B