Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Parallel I/O Ports
MPC885 PowerQUICC Family Reference Manual, Rev. 2
34-2 Freescale Semiconductor
34.1 Features
The following lists the main features of the parallel I/O ports:
• Port A is 16 bits.
• Port B is 18 bits. Port B is shared with the PIP, which is described in Chapter 33, “Parallel Interface
Port (PIP).”
• Port C is 12 bits.
• Port D is 13 bits.
• Port E is 18 bits.
• All ports are bidirectional.
• At Power-ON Reset, CPM Port-B pins states are not predictable and are in an undefined state. CPM
Port-B pins require an output clock in order to be initialized, and therefore will be configured to
three-state mode after the DPLL is locked and output clock is present for two clock cycles. Ports
A, C, D and E are initialized asynchronously, and will therefore power-up in the three-state mode
immediately after power is applied and Power-ON Reset (POR) is asserted.
• All ports have alternate on-chip peripheral functions and all signal values can be read while the
signal is connected to an on-chip peripheral.
• Ports A, B, and E have open-drain capability.
• Port C has 12 interrupt input signals.
34.2 Port A
Port A signals are configured as follows in the port A pin assignment register (PAPAR):
• General-purpose I/O signal (the corresponding PAPAR[DDn] = 0)
• Dedicated on-chip peripheral signal (PAPAR[DDn] = 1)
PAPAR and the port A data direction register (PADIR) are cleared at reset, thus configuring all port A
signals as general-purpose input signals.
Table 34-1 shows defaults for port A signal options.
Table 34-1. Port A Pin Assignment
Signal
Pin Function
PAPAR[DD n] = 0
(General I/O)
1
PAPAR[DD
n] = 1
Input to On-Chip Peripherals
(Default)
PADIR[DR n] = 0 PADIR[DR n] = 1
PA15 PORT A15 USBRXD — GND
PA14 PORT A14 USBOE — —
PA13 PORT A13 RXD2 — GND
PA12 PORT A12 TXD2 — —
PA11 PORT A11 RXD4 MII1-TXD0
RMII1-TXD0
RXD4 = GND
PA10 PORT A10 TIN4/CLK7 MII1-TXER TIN4/CLK7 = BRG04