Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor C-1
Appendix C
Register Quick Reference Guide
This section provides a brief guide to the core registers.
C.1 User Registers
The MPC885 implements the user-level registers defined by the PowerPC architecture except those
required for supporting floating-point operations (the floating-point register file (FPRs) and the
floating-point status and control register (FPSCR)). User-level registers are listed in
Table C-1 .
Table C-2 lists those user-level SPRs defined by the PowerPC architecture that are implemented on the
MPC885.
Table C-1. User-Level Registers
Description Name Comments Access Level
Serialize
Access
General-purpose
registers GPRs The thirty-two 32-bit (GPRs) are used for source
and destination operands. User —
Condition register CR See Section 4.1.1.1.1, “Condition Register (CR).” User Only mtcrf
Table C-2. User-Level SPRs
SPR Number
Name Comments Serialize Access
Decimal SPR [5–9] SPR [0–4]
1 00000 00001 XER See Section 4.1.1.1.3, “XER.” Write: Full sync
Read: Sync relative to load/store
operations
8 00000 01000 LR See the Programming
Environments Manual.
No
9 00000 01001 CTR See the
Programming
Environments Manual.
No
268 01000 01100 TBL read
1
1
Extended opcode for mftb, 371 rather than 339.
Section 10.9, “Timebase.” Write (as a store)
269 01000 01101 TBU read
2
2
Any write ( mtspr ) to this address causes an implementation-dependent software emulation exception.