Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Fast Ethernet Controller (FEC)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 45-13
45.3.2.1 RAM Perfect Match Address Low Register (ADDR_LOW)
The ADDR_LOW register, shown in Figure 45-5 , is written by and must be initialized by the user. It
contains the lower 32 bits of the 48-bit address used in the address recognition process to compare with
the destination address field of the receive frames.
Table 45-8 describes the ADDR_LOW fields.
0x0EE4
0x1EE4 X_WMRK Transmit watermark Section 45.3.2.17, “Transmit Watermark
Register (X_WMRK)”
0x0EEC
0x1EEC X_FSTART Transmit FIFO start address Section 45.3.2.18, “FIFO Transmit Start
Register (X_FSTART)”
0x0F34
0x1F34 FUN_CODE Function code to SDMA Section 45.3.2.19, “DMA Function Code
Register (FUN_CODE)”
0x0F44
0x1F44 R_CNTRL Receive control register Section 45.3.2.20, “Receive Control
Register (R_CNTRL)”
0x0F48
0x1F48 R_HASH Receive hash register Section 45.3.2.21, “Receive Hash
Register (R_HASH)”
0x0F84
0x1F84 X_CNTRL Transmit control register Section 45.3.2.22, “Transmit Control
Register (X_CNTRL)”
0 7 8 15
Field ADDR_LOW BYTE 0 ADDR_LOW BYTE 1
Reset Undefined
R/W R/W
Addr 0x0E00 (FEC1) & 0x1E00 (FEC2)
16 23 24 31
Field ADDR_LOW BYTE 2 ADDR_LOW BYTE 3
Reset Undefined
R/W R/W
Addr 0x0E02 (FEC1) & 0x1E02 (FEC2)
Figure 45-5. ADDR_LOW Register
Table 45-8. ADDR_LOW Field Descriptions
Bits Name Description
0–31 ADDR_LOW Bytes in the 6-byte address: 0 (bits 0–7), 1 (bits 8–15), 2 (bits 16–23) and 3 (bits 24–31)
Table 45-7. FEC Parameter RAM Memory Map (continued)
Address
FEC1
FEC2 Name Description Section