Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Exceptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 6-5
6.1.2.2 Machine Check Interrupt (0x00200)
A machine check interrupt indication is received from the U bus in response to an address or data tenure.
It is typically caused by an access for which the address does not exist or a data error occurs.
As defined in the OEA, machine check interrupts are enabled when MSR[ME] = 1. If MSR[ME] = 0 and
a machine check condition is detected, the processor enters the checkstop state. The behavior of the core
in checkstop state is dependent on the working mode as defined in
Section 53.3.1.1, “Debug Mode Enable
vs. Debug Mode Disable.” When debug mode is enabled, debug mode is entered instead of checkstop state.
When debug mode is disabled, instruction processing is suspended and cannot be restarted without
resetting the core.
An indication that can generate an automatic reset in this condition is sent to the system interface unit. See
Section 11.1.3.2, “Checkstop Reset,” and Section 14.6.2, “PLL and Reset Control Register (PLPRCR),”
for more details. If MSR[ME] = 1, the machine check interrupt is taken. If SRR1[30] = 1, the interrupt is
recoverable. Instruction fetching begins at offset 0x00200 and the registers are set as shown in Table 6-5 .
Table 6-4. Register Settings After a System Reset Interrupt Exception
Register Setting
SRR0 Set to the EA of the next instruction of the interrupted process.
SRR1 Saves the machine status before exceptions and to restore status when an rfi instruction is executed.
1–4 0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Value of MSR[ILE] of the interrupted process.
Other 0
Table 6-5. Register Settings After a Machine Check Interrupt Exception
Register Setting
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 1 1 for instruction fetch-related errors; 0 for load/store-related errors.
2–4 0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME 0
LE Copied from the ILE setting of the interrupted process
Other 0
DSISR Set when the load/store bus is used:
0–14
0
15–16 Set to bits 29-30 of the instruction if X-form instruction and to 0b00 if D-form.
17 Set to bit 25 of the instruction if X-form instruction and to bit 5 if D-form.
18–21 Set to bits 21-24 of the instruction if X-form instruction and to bits 1-4 if D-form.
22–31 Set to bits 6-15 of the instruction.
DAR When the load/store bus is used, DAR holds the EA of the data access that caused the exception.