Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Memory Management Unit
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 8-17
Table 8-9 describes Mx_EPN fields.
8.8.4 IMMU Tablewalk Control Register (MI_TWC)
The IMMU tablewalk control register (MI_TWC), shown in Figure 8-9 , contains the access protection
group and page size of the entry to be loaded into the TLB.
Table 8-10 describes MI_TWC fields.
Table 8-9. M
x
_EPN Field Descriptions
Bits Name Description
0–19 EPN Effective page number for TLB entry. Default value is the EA of the last ITLB/DTLB miss
20–21 — Reserved. Ignored on write, undefined on read
22 EV TLB entry valid bit.
0 TLB entry is invalid
1 TLB entry is valid. EV is set to 1 on each ITLB/DTLB miss.
23–27 — Reserved. Ignored on write, returns 0 on read
28–31 ASID Address space ID of the ITLB/DTLB entry to be compared with M_CASID[CASID]. Loaded with
M_CASID on a TLB miss.
0 15
Field —
Reset 0000_0000_0000_0000
R/W R/W
16 22 23 26 27 28 29 30 31
Field — APG G PS — V
Reset 0 — — — 0 —
R/W R/W R/W R/W R/W R/W R/W
SPR 789
Figure 8-9. IMMU Tablewalk Control Register (MI_TWC)
Table 8-10. MI_TWC Field Descriptions
Bits Name Description
0–22 — Reserved. Ignored on write, returns 0 on read.
23–26 APG Access protection group. Up to 16 protection groups supported. Default for ITLB miss is 0
27 G Guarded memory attribute for entry
0 Nonguarded memory (default for ITLB miss)
1 Guarded memory