Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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The MPC8xx Core
MPC885 PowerQUICC Family Reference Manual, Rev. 2
3-12 Freescale Semiconductor
3.6.3.2 Serializing Load/Store Instructions
The following load/store instructions are not executed until all previous instructions have finished:
• Load/store multiple instructions—lmw, stmw
• Memory synchronization instructions—lwarx, stwcx., sync
• String instructions—lswi, lswx, stswi, stswx
• Move to SPRs
The following load/store instructions must finish before more instructions can be issued:
• Load/store multiple instructions—lmw, stmw
• Memory synchronization instructions—lwarx, stwcx., sync
• String instructions—lswi, lswx, stswi, stswx
3.6.3.3 Store Accesses
Because the core supports the precise exception model, a new store instruction cannot update the data
cache until all prior instructions have finished without an exception. If a store instruction follows a load
instruction, a one-clock delay is inserted between the load bus cycle termination and the store cycle issue.
3.6.3.4 Nonspeculative Load Instructions
Load instructions targeted at nonspeculative memory are identified as nonspeculative one clock cycle after
the previous load/store bus cycle ends, only if all prior instructions have finished without an exception.
The nonspeculative identification relates to the state of the cycle’s associated instruction. For lmw,
although the accesses are pipelined into the bus, they are all marked as nonspeculative because the
instruction is nonspeculative. If a single-register load instruction generates more than one bus cycle, some
of the cycles can be marked as speculative and later cycles can be marked as nonspeculative after all prior
instructions end. Speculative load accesses to external memory marked nonspeculative cannot occur until
the load instruction becomes nonspeculative.
3.6.3.5 Unaligned Accesses
Although the 32-bit U-bus supports only naturally aligned transfers, the LSU supports unaligned accesses
in hardware by breaking them into a pipelined series of aligned transfers.
Table 3-2 shows the number of
bus cycles needed for single-register load/store accesses.
Table 3-2. Bus Cycles Needed for Single-Register Load/Store Accesses
Transfer Size Transfer Address (Last Two Bits) Number of Bus Cycles Transfer Type Address/Size
Byte 0x00 1 Aligned 0x00/byte
0x01 1 Aligned 0x01/byte
0x02 1 Aligned 0x02/byte
0x03 1 Aligned 0x03/byte