Freescale Semiconductor PowerQUICC MPC870, Reference Manual

Page: 380 / 1426

External Bus Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
13-6 Freescale Semiconductor
13.4 Bus Operations
This section provides a functional description of the system bus, the signals that control it, and the bus
cycles provided for data transfers. It also describes error conditions, bus arbitration, and the reset
operation. The MPC885 generates a system clock output (CLKOUT), which directly sets the bus interface
operation frequency. Internally, the MPC885 uses a phase-lock loop (PLL) circuit to generate a master
clock for all core circuitry (including the bus interface), which is phase-locked to CLKOUT.
MPC885 bus interface signals are specified with respect to the rising edge of the external CLKOUT and
are guaranteed to be sampled as inputs or changed as outputs with respect to that edge. Because the same
clock edge is used for driving or sampling bus signals, clock skew may occur between various modules in
a system due to routing or the use of multiple clock lines. The system must handle any clock skew
problems that could occur as a result of layout, lead length, and physical routing.
13.4.1 Basic Transfer Protocol
The basic transfer protocol defines the sequence of actions required for a complete MPC885 bus
transaction.
Figure 13-3 shows a simplification of the basic transfer protocol.
• Arbitration—A device requests bus access
• Address phase—The address and the transfer attributes are generated.
• Data phase—Any data to be transferred is transferred. The data phase may transfer a single beat of
data (4 bytes or less) for nonburst operations, a 4-beat data burst (4
×
4 bytes), an 8-beat data burst
(8
×
2 bytes), or a 16-beat data burst (16
×
1 bytes).
• Termination—The transfer completes successfully or it was aborted.
13.4.2 Single-Beat Transfer
During the data transfer, the master writes data to the slave or reads data from the slave. On a write cycle,
the master drives the data as soon as it can, but not before the cycle after the address transfer phase. The
master must consider the one dead clock cycle switching between drivers to avoid electrical contention.
BB
Bus Busy 1 O When the internal arbiter is enabled, the MPC885 asserts BB to indicate it is bus master.
When the internal arbiter is disabled, the MPC885 asserts BB after the external arbiter
granted mastership to the chip and it is ready to start the transfer.
I When the internal arbiter is enabled, the MPC885 samples this signal to get indication
of when the external master ended its bus tenure (BB negated).
When the internal arbiter is disabled, the BB is sampled, to properly qualify the BG line,
when an external bus transaction is to be executed by the chip.
1
O= Output from the MPC885; I= Input to the MPC885
Arbitration Address transfer Data transfer Termination
Figure 13-3. Basic Transfer Protocol
Table 13-1. MPC885 Signal Overview (continued)
Signal Pins I/O
1
Description