Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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System Development and Debugging
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 53-9
• Two L-data comparators supporting equal, not equal, greater than, and less than. Includes byte,
half-word, and word operating modes, and four byte mask bits for each comparator. It can be used
for integer data. A match is detected only on the valid part of the data bus (according to the cycle’s
size and the two address lsbs).
• No internal breakpoint/watchpoint support for unaligned words and half words.
• L-data comparators can be programmed to treat integers as signed or unsigned.
• Combined comparator pairs to detect in and out of range conditions, including either signed or
unsigned values on the L-data.
• A programmable AND-OR logic structure between the four instruction comparators results in five
outputs, four instruction watchpoints, and one instruction breakpoint.
• A programmable AND-OR logic structure between the four instruction watchpoints and the four
load/store comparators results in three outputs, two load/store watchpoints, and one load/store
breakpoint.
• Five watchpoint pins, three for instructions and two for loads/stores.
• Two dedicated 16-bit down counters. Each can count either an instruction watchpoint or load/store
watchpoint. Only architecturally executed events are counted (count up is performed in case of
recovery).
• On-the-fly trap enable programming of the different internal breakpoints using the development
port serial interface (see
Section 53.3.2, “Development Port Communication” ). Software control is
also available.
• Watchpoints do not change the timing of the machine.
• Internal breakpoints and watchpoints are detected on the instruction during fetch.
• Internal breakpoints and watchpoints are detected on the load/store during load/store bus cycles.
• Instruction and load/store breakpoints and watchpoints are handled on retirement and then
reported.
• Breakpoints and watchpoints on recovered instructions (due to exceptions or missed predictions)
are not reported and do not change the machine’s timing.
• Instructions with instruction breakpoints are not executed. The machine branches to the breakpoint
exception routine before it executes the instruction.
• Instructions with load/store breakpoints are executed. The machine branches to the breakpoint
exception routine after it executes the instruction. The address of the access is placed in the BAR.
• Load/store multiple/string instructions with load/store breakpoints finish execution before the
machine branches to the breakpoint exception routine.
• Load/store data compare is accomplished on the load/store, after swap in store accesses and before
swap in load accesses (as the data appears on the bus).
• Internal breakpoints may operate either in masked mode or in nonmasked mode.
• “Go to x” and “continue” working modes are supported for instruction breakpoints.