Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Interface Configuration
MPC885 PowerQUICC Family Reference Manual, Rev. 2
42-2 Freescale Semiconductor
42.1.2 APC Timer (CPM Timer 4)
The CPM general-purpose timer number 4 is used internally by the ATM pace controller as the APC timer
for both serial ATM and UTOPIA modes. The APC timer should be programmed to run in active-low pulse
and restart mode (see
Section 17.2, “CPM General-Purpose Timers” ). The APC timer period should be
programmed according the required APC rate, which is discussed in Section 40.1, “APC Algorithm.”
42.1.3 RISC Timer
A dedicated RISC timer programmed by host software with the desired time-out interval can be optionally
used to implement a receiver time-out error check. The RISC timer is specified in TSTA (time-stamp timer
address) in the ATM parameter RAM. See
Section 18.8, “The RISC Timer Table,” for additional
information.
42.2 UTOPIA Mode Registers
When operating in UTOPIA mode the PHY layer is connected to the MPC885 UTOPIA interface. The
UTOPIA data signals and some of the control signals are connected to port D. In UTOPIA split bus mode
additional pins taken from the PCMCIA interface are used.The remaining UTOPIA control signals are
connected to ports B and C. The UTOPIA mode requires several registers to be configured as described in
the following sections.
42.2.1 System Clock Control Register (SCCR)
The receive and transmit UTOPIA clocks can be either internal or external and are selected in the UTOPIA
mode register; see
Section 43.2, “UTOPIA Mode Register (UTMODE).” When an internal clock is used,
the system clock control register (SCCR) must be programmed to generate the desired UTOPIA clock
frequency. (If both receive and transmit clocks are external, there is no need to program SCCR.) SCCR is
described in
Section 14.6.1, “System Clock and Reset Control Register (SCCR).” SCCR[27–31] control
the internal UTOPIA clock (UTPCLK).
The frequency of the internal UTPCLK defaults to system frequency. The frequency ratio between the
system clock and UTPCLK is an integer value (freq
sys
/freq
utopia
= integer
>
0). The UTOPIA clock has a
50% duty cycle and is derived from the system frequency divided by two dividers. Note that the UTOPIA
clock must be programmed to operate at a frequency less than or equal to 50 MHz. The SCCR[DFUTP]
and SCCR[DFAUTP] fields should be programmed such that the total UTOPIA clock division factor never
exceeds 10 (that is, the bounds of UTPCLK are 50 MHz > UTPCLK > SYSCLK/10). The UTOPIA clock
frequency can be determined using the following formula:
For example, to achieve a 25-MHz UTOPIA clock with a 50-MHz system clock, DFUTP should be
programmed to 0b001, and DFAUTP should be cleared. The SCCR is shown in
Figure 42-2 .
FREQutopia
FREQsys
2
DFU TP
( )
2 DFAUTP
×
1 +
( ) ×
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