Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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System Interface Unit
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 10-19
Figure 10-14. Interrupt Table Handling Example
The interrupt to be serviced can be determined by reading SIVEC[INTC]. For example, if IRQ3, level 3,
and IRQ6 interrupts occur simultaneously and IRQ3 is masked, INTC = 0b0001_1100 (0x1C), indicating
that the level 3 interrupt should be handled.
Note that SIVEC[INTC] contains the encoding for a level-7 interrupt (see Table 10-7 ) by default, even
when no interrupts are pending. Thus, polling SIVEC when all interrupts are masked returns the level-7
vector. Therefore, the level-7 interrupt vector may indicate a spurious interrupt in the following cases:
• Polling SIVEC returns a level 7 interrupt, but nothing is programmed to interrupt at level 7.
• Polling SIVEC returns a level 7 interrupt, but SIPEND[LV7] is not set (assuming something is
programmed to interrupt at level 7).
10.6 The Bus Monitor
Control of the bus monitor is provided in the SYPCR. The bus monitor ensures that each bus cycle initiated
by the MPC885 terminates within a reasonable time. The MPC885’s bus monitor does not monitor
accesses initiated by external masters. At the start of the transfer start signal (TS), the monitor begins
counting and stops when transfer acknowledge (TA), retry (RETRY) or transfer error (TEA) is asserted.
For burst cycles, this action is also performed between subsequent TA assertions for each data beat. If the
monitor times out, the bus monitor terminates the cycle by internally asserting TEA. The programmability
of the timeout allows for a variation in system peripheral response time. The timing mechanism is clocked
by the system clock divided by eight. The maximum value is 2,040 system clocks. The bus monitor is
always active when FRZ is asserted or when a debug mode request is pending, regardless of the state of
the SYPCR[BME] bit.
Intr: • • •
Save State
R3 <– @ SIVEC
R4 <– Base of Branch Table
• • •
lbz
add
mtspr
bctr Rx, R3 (0)
Rx, Rx, R4
CTR, Rx # Load as Byte
b Routine1 Base
Intr: • • •
Save State
R3 <– @ SIVEC
R4 <– Base of Branch Table
• • •
lhz
add
mtspr
bctr Rx, R3 (0)
Rx, Rx, R4
CTR, Rx # Load as half word
1st Instruction of Routine1
1st Instruction of Routine2
1st Instruction of Routine3
1st Instruction of Routine4
•
•
Base
Base + 400
Base + 800
Base + C00
Base + 1000
Base + n
b Routine2 Base + 4
b Routine3 Base + 8
b Routine4 Base + C
• Base + 10
• Base + n
•
•
•
•
•
•