Freescale Semiconductor PowerQUICC MPC870, Reference Manual

Page: 1243 / 1426

SEC Lite Controller
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 51-7
Figure 51-8. Master Control Register
Table 51-3 describes the Master Control Register signals.
51.1.6 Master Error Address Register (MEAR)
This register saves the address of the transaction whose data phase was terminated with a TEA or Master
Parity Error. A Transfer Error Acknowledge (TEA) signal indicates a fatal error has occurred during the
data phase of a bus transaction. Invalid data may have been received and stored prior to the receipt of the
TEA. The channel that was initiating the transaction will be evident from that channel’s error interrupt.
The PowerQUICC 1 PPC core may chose to reset the channel reporting the TEA, reset the whole SEC Lite,
or reset the entire system with a machine check error. In any case, the host may chose to preserve this TEA
information prior to reset to assist in debug.
The MEAR only holds the address of the first error reported, in the event multiple errors are received
before the first is cleared.
Figure 51-9. Master Error Address Register
0 6 7 8 27 28 29 31
Field — SWR — GI —
Reset 0x0000_0000
R/W R/W
Addr 0x 01030
Table 51-3. Master Control Register Signals
Bits Name
Reset
Value
Description
0–6 — 0 Reserved
7 SWR 0 Software Reset. Writing 1 to this bit will cause a global software reset.
Upon completion of the reset, this bit will be automatically cleared.
0 Don’t reset
1 Global Reset
8–27 — 0 Reserved
28 GI 0 Global Inhibit.
0 - Master will always drive GBL_B active (low).
1 - Master will always drive GBL_B inactive (high).
29–31 — 0 Reserved
0 31
Field ADDRESS
Reset 0x0000_0000
R/W R
Addr 0x 01038