Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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SDMA Channels and IDMA Emulation
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 19-9
19.3.3.2 IDMA Status Registers (IDSR1 and IDSR2)
The IDMA status registers (IDSR1 and IDSR2) report transfer events. When the IDMA controller
recognizes an event, it sets the corresponding event bit in the IDSR. IDSR bits are cleared by writing ones;
writing zeros has no effect.
Figure 19-6 shows the register format.
These registers are affected by HRESET and SRESET. Table 19-6 describes the IDSR fields.
19.3.3.3 IDMA Mask Registers (IDMR1 and IDMR2)
The read/write IDMA mask registers (IDMR1 and IDMR2) have the same format as IDSR, shown in
Figure 19-6 . If an IDMR bit is set, the corresponding interrupt is enabled in IDSRn; if it is cleared, the
corresponding interrupt is masked. Reset clears IDMR. IDMR1’s internal address (IMMR offset) is 0x914;
IDMR2’s is 0x91C. These registers are affected by HRESET and SRESET.
19.3.4 IDMA Buffer Descriptors (BD)
An IDMA buffer descriptor contains the specific transfer information needed for its buffer. IDMA BDs
contain a status-and-control field, the function code registers, the buffer length, and the source and
destination buffer pointers. The BDs are grouped together in contiguous dual-port RAM to form a standard
BD table; see
Figure 19-7 .
0 4 5 6 7
Field — AD DONE OB
Reset 0 0 0 0
R/W R R/W R/W R/W
Addr IMMR + 0x910 (IDSR1); 0x918 (IDSR2)
Figure 19-6. IDMA Status Registers (IDSR1/IDSR2)
Table 19-6. IDSR1/IDSR2 Field Descriptions
Bits Name Description
0–4 — Reserved
5 AD Auxiliary done. Set after processing a BD that has its I bit (interrupt) set.
6 DONE Buffer chain done. Indicates IDMA transfer termination. Set after servicing a BD that has its L bit
(last) set, regardless of the I bit setting.
7 OB Out of buffers. Indicates that the IDMA channel has no valid BDs left in the BD table.