Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Serial Communications Controllers
MPC885 PowerQUICC Family Reference Manual, Rev. 2
21-4 Freescale Semiconductor
Table 21-2 describes GSMR_H fields.
0 12 13 14 15
Field — IRP — GDE
Reset 0
R/W R/W
Addr 0xA24 (GSMR_H2), 0xA44 (GSMR_H3), 0xA64 (GSMR_H4)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field TCRC REVD TRX TTX CDP CTSP CDS CTSS TFL RFW TXSY SYNL RTSM RSYN
Reset 0
R/W R/W
Addr 0xA26 (GSMR_H2), 0xA46 (GSMR_H3), 0xA66 (GSMR_H4)
Figure 21-2. GSMR_H—General SCC Mode Register (High Order)
Table 21-2. GSMR_H Field Descriptions
Bits Name Description
0–12 — Reserved, should be cleared.
13 IRP Infrared Rx polarity. Determines the polarity of the received signal when SCC2 uses IrDA
encoding/decoding—for SCC2 only. See
Section 25.18, “IrDA Encoder/Decoder (SCC2 Only).”
0 Active high polarity. An active high pulse is decoded as 0.
1 Active low polarity. An active low pulse is decoded as 0.
14 — Reserved, should be cleared.
15 GDE Glitch detect enable. Determines whether the SCC searches for glitches on the external Rx and Tx
serial clock lines. Regardless of the GDE setting, a Schmitt trigger on the input lines is used to
reduce signal noise.
0 No glitch detection. Clear GDE if the external serial clock exceeds the limits of glitch detection
logic (6.25 MHz assuming a 25-MHz system clock), if an internal BRG supplies the SCC clock,
or if external clocks are used and glitch detection matters less than power consumption.
1 Glitches can be detected and reported as maskable interrupts in the SCC event register (SCCE).
16–17 TCRC Transparent CRC (valid for totally transparent channel only). Selects the frame checking provided
on transparent channels of the SCC (either the receiver, transmitter, or both, as defined by TTX and
TRX). Although this configuration selects a frame check type, the decision to send the frame check
is made in the TxBD. Thus, frame checks are not needed in transparent mode and frame check
errors generated on the receiver can be ignored.
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1)
01 CRC16 (BISYNC). (X16 + X15 + X2 + 1)
10 32-bit CCITT CRC (Ethernet and HDLC)
(X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1)
11 Reserved
18 REVD Reverse data (valid for a totally transparent channel only)
0 Normal operation
1 Reverses the bit order for totally transparent channels on the SCC (either the receiver,
transmitter, or both, as defined by TTX and TRX) and sends the msb of each byte first.
Section 26.11, “BISYNC Mode Register (PSMR),” describes reversing bit order in a BISYNC
protocol.