Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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IEEE 1149.1 Test Access Port
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 54-5
Figure 54-5. Input/Output Control Boundary Scan Cell (I/O Control Cell)
Figure 54-6 shows the logic configuration of bidirectional signal boundary scan cells.
Figure 54-6. Bidirectional (I/O) Signal Boundary Scan Cell
The value of the control bit controls the output function of the bidirectional signal. One or more
bidirectional data cells can be serially connected to a control cell. Bidirectional signals include two scan
cells for data (input and output buffers) and an I/O control block.
It is important to know the boundary scan bit order and the signals that are associated with them. The bit
order of the boundary scan chain (described in the MPC885 BSDL file) starts with the TDO output and
ends with the TDI input. The shift register cell nearest TDO (first to be shifted in) is defined as bit 1 and
the last bit to be shifted in is bit 475.
54.4 Instruction Register
The MPC885 TAP implementation includes the public instructions EXTEST, SAMPLE/PRELOAD,
BYPASS and CLAMP. An optional public instruction (HI-Z) provides the capability for disabling all
device output drivers. The MPC885 TAP implements a 4-bit instruction register (no parity). The 4-bit TAP
MUX
G1
1
1
To Next Cell
G1
1
1
D
C
D
C
From Last Cell Clock DR
Update DR
Shift DR
Output Control
from System
1 – Extest | Clamp
0 – Otherwise
MUX
To Output
Buffer
Logic
To Next Cell
O.PIN
Output Enable
from System
From Last Cell
I/O
Pin
I.OBS
I/O Control
To Next Pin Pair
EN
Output Data
Input Data
Logic