Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Buffer Descriptors and Connection Tables
MPC885 PowerQUICC Family Reference Manual, Rev. 2
37-2 Freescale Semiconductor
Figure 37-1. Transmit Buffer and TxBD Table Example
In the example of Figure 37-1 , when the transmitter encounters channel number 1 in the transmit queue, it
sends a cell using transmit buffer 4 because TxBD 4 is the active BD in channel number 1’s TxBD table.
As the cell is sent, the transmit buffer pointer TB_PTR tracks the current data position. After the cell is
sent, the transmitter advances the channel’s TBD_PTR to the next BD in the table (unless the current buffer
is a multiple-cell AAL5 frame in which case TBD_PTR is not advanced and the current data position is
kept in TB_PTR) and moves on to the next channel in the transmit queue. When the end of the BD table
is reached (TxBD[W] = 1), the transmitter returns to the head of the table by re-initializing TBD_PTR to
the channel’s TBASE address.
37.1.1 AAL5 Buffers
Each AAL5 buffer can hold either a whole frame or part of it. During transmit or receive operations,
interrupts are optionally generated at the closing of each buffer or at the end of a frame.
The last buffer of a frame is padded automatically by the transmitter to fit an AAL5 cell payload according
to ITU specification I.363. The transmit buffer data length for AAL5 transmit buffers must be greater than
or equal to 48 bytes for all buffers except the first and last buffer of a frame; the first and last buffers of a
frame must have a data length greater than zero. Note that AAL5 transmit buffers have no alignment
restrictions.
Receive buffers, however, must start on a burst-aligned address (divisible by 16) and their lengths should
be a multiple of 48 bytes (that is, the value of SMRBLR in the SCC parameter RAM should be a multiple
of 48). The buffers are filled with multiples of 48 bytes, except for the last buffer in a frame from which
the AAL5 pads are removed.
BD Memory Space (up to 256 KByte)
TBASE
Pointers from
Ch1 TCT
Tx BD Table
of Ch1
Tx BD Table
of Ch4
Buffer Memory Space (4 Gbyte)
Ch1TB_PTR
TBD_PTR
TBD_BASE
TBASE
TBD_PTR
Pointers from
Ch4 TCT
Tx BD 1
Tx BD 2
Tx BD 3
Tx BD 4
Tx BD 5
Tx BD 6
Tx BD 7
Tx BD 8
Tx BD 9
Tx BD 1
Tx BD 2
Tx BD 3
Tx BD 4
Tx BD 5
Tx BD 6
Tx Buffer3 of
Channel1
Tx Buffer4 of
Channel1
Tx Buffer1 of
Channel4
Tx Buffer2 of
Channel4
Tx Buffer3 of
Channel4
Ch4TB_PTR
Tx Buffer2 of
Channel1
Tx Buffer8 of
Channel4
Tx Buffer1 of
Channel1
Pointer from
Parameter RAM