Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Parallel I/O Ports
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 34-23
Table 34-24 describes PEDAT bits.
34.6.1.3 Port E Data Direction Register (PEDIR)
Port E data direction register (PEDIR) bits configure port E signals as general-purpose inputs or outputs.
If a signal is not programmed for general-purpose I/O, PEDIR, depending also on PESO register, selects
the peripheral function to be performed.
m
Bits
0 13 14 15
Field — D14 D15
Reset Undefined
R/W — R/W R/W
Addr 0xAD8
Bits
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
Reset Undefined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Addr 0xADA
Figure 34-20. Port E Data Register (PEDAT)
Table 34-24. PEDAT Bit Descriptions
Bits Name Description
0–13 — Reserved
14–31 D n Contains the data on the corresponding signal
0 13 14 15
Field — DR14 DR15
Reset — — — — — — — — — — — — — — 0 0
R/W — R/W R/W
Addr 0xAC8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field DR16 DR17 DR18 DR19 DR20 DR21 DR22 DR23 DR24 DR25 DR26 DR27 DR28 DR29 DR30 DR31
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Addr 0xACA
Figure 34-21. Port E Data Direction Register (PEDIR)