Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Memory Controller
MPC885 PowerQUICC Family Reference Manual, Rev. 2
15-64 Freescale Semiconductor
3. Translate the timing diagrams into RAM words for each type of memory access. The bottom half
of the figures represent the RAM array contents that handle each of the possible cycles and each
column represents a different word in the RAM array. A blank cell in the figures indicates a don’t
care bit, which is typically programmed to logic 1 to conserve power.
4. Define the UPM parameters that control the memory system in the following sequence. For
additional details, see Table 15-20 .
— Program the RAM array using MCR and MDR. The RAM word must be written into the MDR
before a
WRITE
command is issued to the MCR. Repeat this step for all RAM word entries.
— Initialize the option and base registers of the specific bank according to the address mapping
of the DRAM device chosen.
— Use ORx[MS] to select the machine to control the cycles. Notice that ORx[SAM] determines
address multiplexing for the first clock cycle and subsequent cycles are controlled by the UPM
RAM words. Also notice that the AMX field in the UPM RAM word controls address
multiplexing for the next clock cycle rather than the current one.
— Program MAMR to select the number of columns and refresh timer parameters.
Table 15-20. UPMA Register Settings
Register Field Value Comments
BR1 MS 10 Selects UPMA
PS 00 Selects 32-bit bus width
WP 0 Allows read and write accesses
MPTPR PTP 0010_0000 Prescaler divided by two
MAMR PTA 0000_1100 15.6 µs at a 25-MHz clock
PTAE 1 Enables periodic timer A
AMA 001 Selects nine column address pins
DSA 01 Selects two disable timer clock cycles
GPLA4DIS 0 Disables the UPWAITA signal
RLFA 0011 Selects three loop iterations for read
WLFA 0011 Selects three loop iterations for write
OR1 SAM 1 Selects column address on first cycle
BIH 0 Supports burst accesses