Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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MPC885 PowerQUICC Family Reference Manual, Rev. 2
48-36 Freescale Semiconductor
48.3.9.4 AESU Key Registers
The AESU Key Registers hold from 16, 24, or 32 bytes of key data, with the first 8 bytes of key data
written to Key 1. Any key data written to bytes beyond the value written to the key size register will be
ignored. The key data registers are cleared when the AESU is reset or re-initialized. If these registers are
modified during message processing, a context error will be generated.
The key data registers may be read when changing context in decrypt mode. To resume processing, the
value read must be written back to the key registers and the “restore decrypt key” bit must be set in the
mode register. This eliminates the overhead of expanding the key prior to starting decryption when
switching context.
48.3.9.5 AESU FIFOs
The AESU fetches data 128 bits at a time from the input FIFO. During processing, the input data is
encrypted or decrypted with the key and initialization vector (CBC mode only) and the results are placed
in the output FIFO. The output size is the same as the input size.
Writing to the FIFO address space places 64 bits of message data into the input FIFO. The input FIFO may
be written any time the IFW signal is asserted (as indicated in the AESU status register). This will indicate
that the number of bytes of available space is at or above the threshold specified in the mode register. There
Table 48-17. Counter Modulus
Value
Written
Modulus
8 2
8
16 2
16
24 2
24
32 2
32
40 2
40
48 2
48
56 2
56
64 2
64
72 2
72
80 2
80
88 2
88
96 2
96
104 2
104
112 2
112
120 2
120
128 2
128