Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Clocks and Power Control
MPC885 PowerQUICC Family Reference Manual, Rev. 2
14-8 Freescale Semiconductor
the design is performed; if potential manufacturing downtime due to redesign of crystal circuits is
unacceptable, a canned oscillator circuit should be used instead.
Figure 14-3. Crystal Circuit Examples
14.3 Clock Signals
The MPC885 uses the following clocks, summarized in Table 14-4 . These clocks are described in the
following three sections, grouped by their different sources.
.
Table 14-4. Functionality Summary of the Clocks
Clock Description
GCLK1C/GCLK2C Basic clocks supplied to the core, the data and instruction caches, and MMUs
GCLK1/GCLK2 Basic clocks supplied to the SIU, clock module, CP, and most other features in the CPM
GCLK1_50/GCLK2_50 Optionally divided versions of GCLK1/GCLK2 that clock the GPCM and UPM in the
memory controller and provide the CLKOUT output for the external bus
UTPCLK Clocks the Utopia Module
BRGCLK Clocks the four baud rate generators and the memory controller refresh timer. This allows
the serial ports to operate at a fixed frequency and the memory refresh to continue at a
uniform rate even when the rest of the MPC885 is operating at a reduced frequency.
SYNCCLK Used by the serial synchronization circuitry in the serial ports of the CPM, and includes the
SI, SCC, and SMCs. SYNCCLK performs the function of synchronizing externally
generated clocks before they are used internally. SYNCCLK allows the SI, SCC, and SMCs
to continue operating at a fixed frequency.
CLKOUT Clock out is an external clock signal used to drive other devices, and thus provide the ability
to operate synchronously with those devices. Equivalent to the internal GCLK2_50 signal.
TMBCLK Clocks the time base and decrementer
PITCLK Clocks the periodic interrupt timer
XTAL EXTAL
A5 A4
OSCM
Crystal = 10 MHz
C1 R2
R1
C2
R1=10M
Ω
, R2=1K
Ω
, C1=47pf, C2=56pf