Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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External Signals
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 12-39
12.3 Reset Behavior
The reset behavior of a subset of multiple-function pins depends on which signal function is active. The
SIU module configuration register (SIUMCR) programming determines which signal functions of this pin
subset are activated at reset; see
Section 10.4.2, “SIU Module Configuration Register (SIUMCR).” Some
(but not all) of the SIUMCR default values are determined by the user-controlled hardware reset
configuration word; see
Section 11.3.1.1, “Hard Reset Configuration Word.” When HRESET (or
PORESET) is asserted, these pins immediately begin functioning as the signals selected in the SIUMCR.
The behavior of these signals is shown in
Table 12-3 .
MII1_COL Hi-Z R10 Input MII1_COL —Media-independent interface 1, collision
Power supply See
Figure 12-3
Power VDDL—Power supply for the internal logic
VDDH—Power supply for the I/O buffers and certain parts of the
clock control
VDDSYN—Power supply of the PLL circuitry
GND—Ground for circuits, except for the PLL circuitry
VSSSYN, VSSSYN1—Ground for the PLL circuitry
1
Pulled low if RSTCONF pulled down.
2
High until DPLL locked, then oscillates.
3
See Section 11.4, “TRST Considerations ,” and Section 54.6, “Recommended TAP Configuration . ”
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Name
Hard
Reset
Number Type Description