Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Parallel Interface Port (PIP)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 33-3
DMA. Blocks of data can be transferred without interrupting the core. The data block can span several
linked buffers (a buffer chain), and an entire block can be transferred without core intervention.
CP-controlled transparent transfers are described in
Section 33.8, “Transparent Transfers.”
For a CP-controlled PIP:
• Initialize the PIPC and parameter RAM to configure the channel.
• Set up buffer descriptors and buffers for the DMA.
• Use PIPM and PIPE to control and monitor events reported.
33.3 The PIP Parameter RAM
The PIP remaps the SMC2 parameter RAM. The following subsections describe the PIP parameter RAM
for sending and receiving.
33.3.1 PIP Transmitter Parameter RAM
The PIP transmitter uses the parameter RAM mapping shown in Table 33-1 . Certain parameter RAM
values must be initialized before the transmitter is enabled; others are initialized or written by the CP. Most
software does not need access to parameter RAM values after initialization because activity centers around
the buffer descriptors
Table 33-1. PIP Transmitter Parameter RAM Memory Map
Offset
1
Name Width Description
0x00 — Hword Reserved for receiving.
0x02 TBASE Hword PIP TxBD table base offset from the beginning of dual-port RAM. Initialize TBASE before
enabling the channel. TBASE should be divisible by 8.
0x04 PFCR Byte PIP function code. Appears on AT[1-3] when the associated SDMA channel accesses
memory. Also controls byte ordering for the transfers. See
Section 33.3.1.1, “PIP Function
Code Register (PFCR).”
0x05 SMASK Byte Status mask. Controls which, if any, printer status lines are checked before each transfer.
See
Section 33.3.1.2, “Status Mask Register (SMASK).”
0x06–
0x17
— — Reserved for receiving.
0x18 TSTATE Word Tx internal state.
0x1C T_PTR Word Tx internal data pointer
0x20 TBPTR Hword TxBD pointer. Points to the current Tx BD during frame transmission or the next BD to be
processed when idle. After reset or when the end of the Tx BD table is reached, the CP
initializes TBPTR to the TBASE value. Most applications do not need to write TBPTR, but
it can be updated when the transmitter is disabled or when no Tx buffer is in use.
0x22 T_CNT Hword Tx internal byte count
0x24 TTEMP Word Tx temporary
1
From PIP base address. PIP base = IMMR + 0x3F80 (SMC2)