Freescale Semiconductor PowerQUICC MPC870, Reference Manual

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Fast Ethernet Controller (FEC)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
45-28 Freescale Semiconductor
Table 45-25 bit field descriptions for X_WMRK.
45.3.2.18 FIFO Transmit Start Register (X_FSTART)
The X_FSTART register, shown in Figure 45-22 , can be programmed by the user to indicate the starting
address of the transmit FIFO. X_FSTART is reset to the first available RAM address. The specific reset
value is microcode-dependent. Users do not normally need to program X_FSTART. If users want to
reserve RAM locations for other purposes, X_FSTART should never be set to value less than reset value.
Table 45-26 describes X_FSTART fields.
Table 45-25. X_WMRK Field Descriptions
Bits Name Description
0–29 — Reserved, should be cleared by the host processor.
30–31 X_WMRK Transmit FIFO watermark. Frame transmission begins when the number of bytes selected by this
field have been written into the transmit FIFO or if an end of frame has been written to the FIFO
or if the FIFO is full before the selected number of bytes have been written.
0x 64 bytes written to the transmit FIFO
10 128 bytes written to the transmit FIFO
11 192 bytes written to the transmit FIFO
0 15
Field —
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0EEC (FEC1) & 0x1EEC (FEC2)
16 20 21 22 29 30 31
Field — 1 X_FSTART —
Reset 0000_0 1 Microcode dependent 00
R/W R/W
Addr 0x0EEE (FEC1) & 0x1EEE (FEC2)
Figure 45-22. X_FSTART Register
Table 45-26. X_FSTART Field Descriptions
Bits Name Description
0–21 — Reserved. Note that all bits read back as 0 except for 21, which returns a 1.
22–29 X_FSTART Address of first transmit FIFO location
30–31 — Reserved, should be cleared by the host processor.